Second Round of Renesas ARM64 Based SoC DT Updates for v4.10

---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 94 ++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796.dtsi +94 -0

index f9cb7796ad49..2e940ff61378 100644
@@ -17,6 +17,16 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";

@@ -239,6 +249,90 @@
 			#power-domain-cells = <1>;
 		};
 
+		i2c0: i2c at e6500000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe6500000 0 0x40>;
+			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 931>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at e6508000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe6508000 0 0x40>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 930>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at e6510000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe6510000 0 0x40>;
+			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 929>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at e66d0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe66d0000 0 0x40>;
+			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 928>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c4: i2c at e66d8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe66d8000 0 0x40>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 927>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c5: i2c at e66e0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe66e0000 0 0x40>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 919>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c6: i2c at e66e8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a7796";
+			reg = <0 0xe66e8000 0 0x40>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
 		scif2: serial at e6e88000 {
 			compatible = "renesas,scif-r8a7796",
 				     "renesas,rcar-gen3-scif", "renesas,scif";

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #2 lore raw

PATCH 2/18 arm64: dts: r8a7796: Enable I2C DMA

From: Ulrich Hecht <[email protected]>

Signed-off-by Ulrich Hecht <[email protected]>

Reviewed-by Geert Uytterhoeven <[email protected]>

Tested-by Wolfram Sang <[email protected]>

---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796.dtsi +17 -0

index 2e940ff61378..9599f5691099 100644
@@ -257,6 +257,9 @@
 			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 931>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+			       <&dmac2 0x91>, <&dmac2 0x90>;
+			dma-names = "tx", "rx", "tx", "rx";
 			i2c-scl-internal-delay-ns = <110>;
 			status = "disabled";
 		};

@@ -269,6 +272,9 @@
 			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 930>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+			       <&dmac2 0x93>, <&dmac2 0x92>;
+			dma-names = "tx", "rx", "tx", "rx";
 			i2c-scl-internal-delay-ns = <6>;
 			status = "disabled";
 		};

@@ -281,6 +287,9 @@
 			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 929>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+			       <&dmac2 0x95>, <&dmac2 0x94>;
+			dma-names = "tx", "rx", "tx", "rx";
 			i2c-scl-internal-delay-ns = <6>;
 			status = "disabled";
 		};

@@ -293,6 +302,8 @@
 			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 928>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+			dma-names = "tx", "rx";
 			i2c-scl-internal-delay-ns = <110>;
 			status = "disabled";
 		};

@@ -305,6 +316,8 @@
 			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 927>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+			dma-names = "tx", "rx";
 			i2c-scl-internal-delay-ns = <110>;
 			status = "disabled";
 		};

@@ -317,6 +330,8 @@
 			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 919>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+			dma-names = "tx", "rx";
 			i2c-scl-internal-delay-ns = <110>;
 			status = "disabled";
 		};

@@ -329,6 +344,8 @@
 			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 918>;
 			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+			dma-names = "tx", "rx";
 			i2c-scl-internal-delay-ns = <6>;
 			status = "disabled";
 		};

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #3 lore raw

PATCH 3/18 arm64: dts: r8a7796: salvator-x: enable I2C

From: Ulrich Hecht <[email protected]>

Signed-off-by Ulrich Hecht <[email protected]>

Reviewed-by Geert Uytterhoeven <[email protected]>

Tested-by Wolfram Sang <[email protected]>

---
 arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +12 -0

index a9c296b1e1b7..f35e96ca7d60 100644
@@ -111,6 +111,11 @@
 		function = "scif_clk";
 	};
 
+	i2c2_pins: i2c2 {
+		groups = "i2c2_a";
+		function = "i2c2";
+	};
+
 	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";

@@ -208,6 +213,13 @@
 	status = "okay";
 };
 
+&i2c2 {
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
 &wdt0 {
 	timeout-sec = <60>;
 	status = "okay";

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #4 lore raw

PATCH 4/18 arm64: dts: h3ulcb: update documentation with official board name

From: Vladimir Barinov <[email protected]>

This updates H3ULCB Device tree bindings Documentation with official board name

---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Documentation/devicetree/bindings/arm/shmobile.txt +1 -1

index 2f0b7169f132..1c2499ca1bee 100644
@@ -49,7 +49,7 @@ Boards:
     compatible = "renesas,genmai", "renesas,r7s72100"
   - Gose
     compatible = "renesas,gose", "renesas,r8a7793"
-  - H3ULCB (RTP0RC7795SKB00010S)
+  - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S)
     compatible = "renesas,h3ulcb", "renesas,r8a7795";
   - Henninger
     compatible = "renesas,henninger", "renesas,r8a7791"

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #5 lore raw

PATCH 5/18 arm64: dts: h3ulcb: update header

From: Vladimir Barinov <[email protected]>

This updates H3ULCB device tree header with official board name

---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +1 -1

index bcb11a868343..f178fe1730de 100644
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for the H3ULCB board
+ * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
  *
  * Copyright (C) 2016 Renesas Electronics Corp.
  * Copyright (C) 2016 Cogent Embedded, Inc.

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #6 lore raw

PATCH 6/18 arm64: dts: m3ulcb: add M3ULCB board DT bindings

From: Vladimir Barinov <[email protected]>

Add M3ULCB Device tree bindings Documentation, listing it as a supported board.

---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 1 file changed, 2 insertions(+)

Documentation/devicetree/bindings/arm/shmobile.txt +2 -0

index 1c2499ca1bee..29bf24ca0b7b 100644
@@ -61,6 +61,8 @@ Boards:
     compatible = "renesas,kzm9g", "renesas,sh73a0"
   - Lager (RTP0RC7790SEB00010S)
     compatible = "renesas,lager", "renesas,r8a7790"
+  - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S)
+    compatible = "renesas,m3ulcb", "renesas,r8a7796";
   - Marzen
     compatible = "renesas,marzen", "renesas,r8a7779"
   - Porter (M2-LCDP)

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #7 lore raw

PATCH 7/18 arm64: dts: m3ulcb: initial device tree

From: Vladimir Barinov <[email protected]>

Add the initial device tree for the R8A7796 SoC based M3ULCB low cost board (R-Car Starter Kit Pro)

This commit supports the following peripherals:
- SCIF (console)

---
 arch/arm64/boot/dts/renesas/Makefile           |  2 +-
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 51 ++++++++++++++++++++++++++
 2 files changed, 52 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts

arch/arm64/boot/dts/renesas/Makefile +1 -1

index eb72830ec9eb..1618e0a3c81d 100644
@@ -1,5 +1,5 @@
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
-dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb
+dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
 
 always		:= $(dtb-y)
 clean-files	:= *.dtb

arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts new file +51 -0

51 lines not on this page · raw message

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #8 lore raw

PATCH 8/18 arm64: dts: m3ulcb: enable SCIF clk and pins

From: Vladimir Barinov <[email protected]>

This enables the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +13 -0

index 1ae0708bb495..96cda59c2698 100644
@@ -37,10 +37,18 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif2_pins: scif2 {
 		groups = "scif2_data_a";
 		function = "scif2";
 	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk_a";
+		function = "scif_clk";
+	};
 };
 
 &scif2 {

@@ -49,3 +57,8 @@
 
 	status = "okay";
 };
+
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #9 lore raw

PATCH 9/18 arm64: dts: m3ulcb: enable GPIO leds

From: Vladimir Barinov <[email protected]>

This supports GPIO leds on M3ULCB board

---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +11 -0

index 96cda59c2698..49162bd488f8 100644
@@ -30,6 +30,17 @@
 		/* first 128MB is reserved for secure area. */
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led5 {
+			gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+		};
+		led6 {
+			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
+		};
+	};
 };
 
 &extal_clk {

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #10 lore raw

PATCH 10/18 arm64: dts: m3ulcb: enable GPIO keys

From: Vladimir Barinov <[email protected]>

This supports GPIO keys on M3ULCB board

---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +13 -0

index 49162bd488f8..2f8f183ea0cd 100644
@@ -12,6 +12,7 @@
 /dts-v1/;
 #include "r8a7796.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "Renesas M3ULCB board based on r8a7796";

@@ -41,6 +42,18 @@
 			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
 		};
 	};
+
+	keyboard {
+		compatible = "gpio-keys";
+
+		key-1 {
+			linux,code = <KEY_1>;
+			label = "SW3";
+			wakeup-source;
+			debounce-interval = <20>;
+			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+		};
+	};
 };
 
 &extal_clk {

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #11 lore raw

PATCH 11/18 arm64: dts: m3ulcb: enable EXTALR clk

From: Vladimir Barinov <[email protected]>

This enables EXTALR clock that can be used for the watchdog.

---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 4 ++++
 1 file changed, 4 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +4 -0

index 2f8f183ea0cd..5567c46f3753 100644
@@ -60,6 +60,10 @@
 	clock-frequency = <16666666>;
 };
 
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
 &pfc {
 	pinctrl-0 = <&scif_clk_pins>;
 	pinctrl-names = "default";

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #12 lore raw

PATCH 12/18 arm64: dts: m3ulcb: enable WDT

From: Vladimir Barinov <[email protected]>

This supports watchdog timer for M3ULCB board

---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 5 +++++
 1 file changed, 5 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +5 -0

index 5567c46f3753..593d0b4ab31a 100644
@@ -90,3 +90,8 @@
 	clock-frequency = <14745600>;
 	status = "okay";
 };
+
+&wdt0 {
+	timeout-sec = <60>;
+	status = "okay";
+};

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #13 lore raw

PATCH 13/18 arm64: dts: m3ulcb: enable SDHI0

From: Vladimir Barinov <[email protected]>

This supports SDHI0 on M3ULCB board SD card slot

---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 49 ++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +49 -0

index 593d0b4ab31a..d209e5480ff6 100644
@@ -54,6 +54,30 @@
 			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 		};
 	};
+
+	vcc_sdhi0: regulator-vcc-sdhi0 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI0 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vccq_sdhi0: regulator-vccq-sdhi0 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI0 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
 };
 
 &extal_clk {

@@ -77,6 +101,31 @@
 		groups = "scif_clk_a";
 		function = "scif_clk";
 	};
+
+	sdhi0_pins: sd0 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
+
+	sdhi0_pins_uhs: sd0_uhs {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <1800>;
+	};
+};
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-1 = <&sdhi0_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&vcc_sdhi0>;
+	vqmmc-supply = <&vccq_sdhi0>;
+	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	status = "okay";
 };
 
 &scif2 {

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #14 lore raw

PATCH 14/18 arm64: dts: m3ulcb: enable SDHI2

From: Vladimir Barinov <[email protected]>

This supports SDHI2 for M3ULCB onboard eMMC

---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +43 -0

index d209e5480ff6..c3f064ac2cb4 100644
@@ -55,6 +55,24 @@
 		};
 	};
 
+	reg_1p8v: regulator0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator1 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	vcc_sdhi0: regulator-vcc-sdhi0 {
 		compatible = "regulator-fixed";

@@ -113,6 +131,18 @@
 		function = "sdhi0";
 		power-source = <1800>;
 	};
+
+	sdhi2_pins: sd2 {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <3300>;
+	};
+
+	sdhi2_pins_uhs: sd2_uhs {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <1800>;
+	};
 };
 
 &sdhi0 {

@@ -128,6 +158,19 @@
 	status = "okay";
 };
 
+&sdhi2 {
+	/* used for on-board 8bit eMMC */
+	pinctrl-0 = <&sdhi2_pins>;
+	pinctrl-1 = <&sdhi2_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
 &scif2 {
 	pinctrl-0 = <&scif2_pins>;
 	pinctrl-names = "default";

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #15 lore raw

PATCH 15/18 arm64: dts: h3ulcb: enable SDHI2

From: Vladimir Barinov <[email protected]>

This supports SDHI2 for H3ULCB onboard eMMC

---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +43 -0

index f178fe1730de..8d0ac076d8e2 100644
@@ -62,6 +62,24 @@
 		clock-frequency = <24576000>;
 	};
 
+	reg_1p8v: regulator0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator1 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	vcc_sdhi0: regulator-vcc-sdhi0 {
 		compatible = "regulator-fixed";

@@ -157,6 +175,18 @@
 		power-source = <1800>;
 	};
 
+	sdhi2_pins: sd2 {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <3300>;
+	};
+
+	sdhi2_pins_uhs: sd2_uhs {
+		groups = "sdhi2_data8", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <1800>;
+	};
+
 	sound_pins: sound {
 		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
 		function = "ssi";

@@ -273,6 +303,19 @@
 	status = "okay";
 };
 
+&sdhi2 {
+	/* used for on-board 8bit eMMC */
+	pinctrl-0 = <&sdhi2_pins>;
+	pinctrl-1 = <&sdhi2_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
 &ssi1 {
 	shared-pin;
 };

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #16 lore raw

PATCH 16/18 arm64: dts: h3ulcb: rename SDHI0 pins

From: Vladimir Barinov <[email protected]>

This changes SDHI0 pin names for H3ULCB board

---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +4 -4

index 8d0ac076d8e2..6ffb0517421a 100644
@@ -163,13 +163,13 @@
 		function = "avb";
 	};
 
-	sdhi0_pins_3v3: sd0_3v3 {
+	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
 		power-source = <3300>;
 	};
 
-	sdhi0_pins_1v8: sd0_1v8 {
+	sdhi0_pins_uhs: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
 		power-source = <1800>;

@@ -291,8 +291,8 @@
 };
 
 &sdhi0 {
-	pinctrl-0 = <&sdhi0_pins_3v3>;
-	pinctrl-1 = <&sdhi0_pins_1v8>;
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-1 = <&sdhi0_pins_uhs>;
 	pinctrl-names = "default", "state_uhs";
 
 	vmmc-supply = <&vcc_sdhi0>;

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Sergei Shtylyov

2016-11-21 13:13 UTC #17 lore raw

PATCH 16/18 arm64: dts: h3ulcb: rename SDHI0 pins

Hello.

Quoted 17 lines · Simon Horman

From: Vladimir Barinov <[email protected]>
This changes SDHI0 pin names for H3ULCB board
Signed-off-by Vladimir Barinov <[email protected]>
Signed-off-by Simon Horman <[email protected]>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +0 -0
index 8d0ac076d8e2..6ffb0517421a 100644
@@ -163,13 +163,13 @@
 		function = "avb";
 	};

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts line 172

Quoted 10 lines

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +2 -2

 
-	sdhi0_pins_3v3: sd0_3v3 {
+	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
 		power-source = <3300>;
 	};
 
-	sdhi0_pins_1v8: sd0_1v8 {
+	sdhi0_pins_uhs: sd0 {

I'm afraid the following will just override the props of the node above
which is not what we ant.

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts line 175

Quoted 3 lines

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +0 -0

 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
 		power-source = <1800>;

[...]

MBR, Sergei

Vladimir Barinov

2016-11-22 11:22 UTC #18 lore raw

PATCH 16/18 arm64: dts: h3ulcb: rename SDHI0 pins

Hi Sergei,

Quoted 30 lines · Sergei Shtylyov

Hello.
Quoted 26 lines · Simon Horman
From: Vladimir Barinov <[email protected]>
This changes SDHI0 pin names for H3ULCB board
Signed-off-by Vladimir Barinov <[email protected]>
Signed-off-by Simon Horman <[email protected]>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +1 -1
index 8d0ac076d8e2..6ffb0517421a 100644
@@ -163,13 +163,13 @@
         function = "avb";
     };
 
-    sdhi0_pins_3v3: sd0_3v3 {
+    sdhi0_pins: sd0 {
         groups = "sdhi0_data4", "sdhi0_ctrl";
         function = "sdhi0";
         power-source = <3300>;
     };
 

Quoted 5 lines

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts line 172
Quoted 2 lines
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +1 -1
-    sdhi0_pins_1v8: sd0_1v8 {
+    sdhi0_pins_uhs: sd0 {
I'm afraid the following will just override the props of the node
above which is not what we ant.

Thank you for pointing to this.

This is my typo.
I will rework the patch to have different node names.

Regards,
Vladimir

Quoted 8 lines

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts line 175
Quoted 4 lines
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +0 -0
         groups = "sdhi0_data4", "sdhi0_ctrl";
         function = "sdhi0";
         power-source = <1800>;
[...]
MBR, Sergei

Sergei Shtylyov

2016-11-22 11:40 UTC #19 lore raw

PATCH 16/18 arm64: dts: h3ulcb: rename SDHI0 pins

Quoted 31 lines · Vladimir Barinov

Quoted 26 lines
Quoted 26 lines
From: Vladimir Barinov <[email protected]>
This changes SDHI0 pin names for H3ULCB board
Signed-off-by Vladimir Barinov <[email protected]>
Signed-off-by Simon Horman <[email protected]>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +1 -1
index 8d0ac076d8e2..6ffb0517421a 100644
@@ -163,13 +163,13 @@
         function = "avb";
     };
 
-    sdhi0_pins_3v3: sd0_3v3 {
+    sdhi0_pins: sd0 {
         groups = "sdhi0_data4", "sdhi0_ctrl";
         function = "sdhi0";
         power-source = <3300>;
     };
 
Quoted 5 lines
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts line 172
Quoted 2 lines
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +1 -1
-    sdhi0_pins_1v8: sd0_1v8 {
+    sdhi0_pins_uhs: sd0 {
I'm afraid the following will just override the props of the node above
which is not what we ant.

Quoted 4 lines

Thank you for pointing to this.
This is my typo.
I will rework the patch to have different node names.

The patch had been already merged by Simon and was posted a s apart of a
pull request (if I don't mistake), so I guess an incremental patch needed now...

Quoted 2 lines

Regards,
Vladimir

MBR, Sergei

Vladimir Barinov

2016-11-22 12:08 UTC #20 lore raw

PATCH 16/18 arm64: dts: h3ulcb: rename SDHI0 pins

Hi Sergei,

Quoted 34 lines · Sergei Shtylyov

Quoted 32 lines · Vladimir Barinov
Quoted 32 lines
Quoted 18 lines
From: Vladimir Barinov <[email protected]>
This changes SDHI0 pin names for H3ULCB board
Signed-off-by Vladimir Barinov <[email protected]>
Signed-off-by Simon Horman <[email protected]>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +0 -0
index 8d0ac076d8e2..6ffb0517421a 100644
@@ -163,13 +163,13 @@
         function = "avb";
     };
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts line 172
Quoted 10 lines
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +2 -2
 
-    sdhi0_pins_3v3: sd0_3v3 {
+    sdhi0_pins: sd0 {
         groups = "sdhi0_data4", "sdhi0_ctrl";
         function = "sdhi0";
         power-source = <3300>;
     };
 
-    sdhi0_pins_1v8: sd0_1v8 {
+    sdhi0_pins_uhs: sd0 {
I'm afraid the following will just override the props of the node
above
which is not what we ant.

Quoted 8 lines

Quoted 4 lines
Thank you for pointing to this.
This is my typo.
I will rework the patch to have different node names.
The patch had been already merged by Simon and was posted a s apart
of a pull request (if I don't mistake), so I guess an incremental patch needed now...

Thanks for clarification.

I will make incremental patch.

Regards,
Vladimir

Quoted 6 lines

Quoted 3 lines
Regards,
Vladimir
MBR, Sergei

Simon Horman

2016-11-30 10:07 UTC #21 lore raw

PATCH 16/18 arm64: dts: h3ulcb: rename SDHI0 pins

Quoted 42 lines · Vladimir Barinov

Hi Sergei,
Quoted 39 lines · Sergei Shtylyov
Quoted 36 lines · Vladimir Barinov
Quoted 26 lines
Quoted 26 lines
From: Vladimir Barinov <[email protected]>
This changes SDHI0 pin names for H3ULCB board
Signed-off-by Vladimir Barinov <[email protected]>
Signed-off-by Simon Horman <[email protected]>
---
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +1 -1
index 8d0ac076d8e2..6ffb0517421a 100644
@@ -163,13 +163,13 @@
        function = "avb";
    };
 
-    sdhi0_pins_3v3: sd0_3v3 {
+    sdhi0_pins: sd0 {
        groups = "sdhi0_data4", "sdhi0_ctrl";
        function = "sdhi0";
        power-source = <3300>;
    };
 
Quoted 6 lines
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts line 172
Quoted 2 lines
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +1 -1
-    sdhi0_pins_1v8: sd0_1v8 {
+    sdhi0_pins_uhs: sd0 {
I'm afraid the following will just override the props of the node
above
which is not what we ant.
Thank you for pointing to this.
This is my typo.
I will rework the patch to have different node names.

Quoted 6 lines

Quoted 3 lines
The patch had been already merged by Simon and was posted a s apart of
a pull request (if I don't mistake), so I guess an incremental patch needed now...
Thanks for clarification.
I will make incremental patch.

Please do.

Simon Horman

author

2016-11-21 12:05 UTC #22 lore raw

PATCH 17/18 arm64: dts: r8a7795: Add device node for PRR

From: Geert Uytterhoeven <[email protected]>

Add a device node for the Product Register, which provides SoC product and revision information.

Signed-off-by Geert Uytterhoeven <[email protected]>

---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

arch/arm64/boot/dts/renesas/r8a7795.dtsi +5 -0

index 681f54422375..a39a702b904d 100644
@@ -321,6 +321,11 @@
 			#power-domain-cells = <0>;
 		};
 
+		prr: chipid at fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+
 		sysc: system-controller at e6180000 {
 			compatible = "renesas,r8a7795-sysc";
 			reg = <0 0xe6180000 0 0x0400>;

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Simon Horman

author

2016-11-21 12:05 UTC #23 lore raw

PATCH 18/18 arm64: dts: r8a7796: Add device node for PRR

From: Geert Uytterhoeven <[email protected]>

Add a device node for the Product Register, which provides SoC product and revision information.

Signed-off-by Geert Uytterhoeven <[email protected]>

---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

arch/arm64/boot/dts/renesas/r8a7796.dtsi +5 -0

index 9599f5691099..41a050d2f192 100644
@@ -243,6 +243,11 @@
 			#power-domain-cells = <0>;
 		};
 
+		prr: chipid at fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+
 		sysc: system-controller at e6180000 {
 			compatible = "renesas,r8a7796-sysc";
 			reg = <0 0xe6180000 0 0x0400>;

Signature · 1 line

2.7.0.rc3.207.g0ac5344

Arnd Bergmann

2016-11-30 15:51 UTC #24 lore raw