arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm

PATCH Superseded Jyri Sarha 2 participants 3 messages Dec 8, 2016

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Arm (32-bit) Arm sub-architectures OMAP2+ support

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Jyri Sarha

author

2016-12-08 10:19 UTC #0 lore raw

PATCH v2 1/1 arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm

Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock.

Signed-off-by Jyri Sarha <[email protected]>

---
Changes since v2:
- Move board specific EMIF_OCP_CONFIG_* definitions to board/ti/am335x/board.h and improve the related comment
- Handle also am335x-evms older than revision 1.5

 arch/arm/include/asm/emif.h      |  1 +
 arch/arm/mach-omap2/am33xx/ddr.c |  4 ++++
 board/ti/am335x/board.c          | 15 +++++++++++++++
 board/ti/am335x/board.h          | 10 ++++++++++
 4 files changed, 30 insertions(+)

arch/arm/include/asm/emif.h +1 -0

index b00dece..9a46340 100644
@@ -1171,6 +1171,7 @@ struct emif_regs {
 	u32 sdram_tim1;
 	u32 sdram_tim2;
 	u32 sdram_tim3;
+	u32 ocp_config;
 	u32 read_idle_ctrl;
 	u32 zq_config;
 	u32 temp_alert_config;

arch/arm/mach-omap2/am33xx/ddr.c +4 -0

index 6acf30c..690487e 100644
@@ -180,6 +180,10 @@ void config_sdram(const struct emif_regs *regs, int nr)
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+	/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
+	if (regs->ocp_config)
+		writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
 }
 
 /**

board/ti/am335x/board.c +15 -0

index da9eab4..b994b42 100644
@@ -109,6 +109,16 @@ static const struct emif_regs ddr2_emif_reg_data = {
 	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 };
 
+static const struct emif_regs ddr2_evm_emif_reg_data = {
+	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
+	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41J128MJT125_RD_DQS,
 	.datawdsratio0 = MT41J128MJT125_WR_DQS,

@@ -198,6 +208,7 @@ static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 };

@@ -208,6 +219,7 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
 	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 				PHY_EN_DYN_PWRDN,

@@ -486,6 +498,9 @@ void sdram_init(void)
 		config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 			   &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 			   0);
+	else if (board_is_gp_evm())
+		config_ddr(266, &ioregs, &ddr2_data,
+			   &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 	else
 		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);

board/ti/am335x/board.h +10 -0

index 9776df7..7caaee2 100644
@@ -11,6 +11,16 @@
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
+/**
+ * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
+ * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
+ * Synchronization Lost errors. The values are the biggest that work
+ * reliably with offered video modes and the memory subsystem on the
+ * boards.
+ */
+#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK       0x00141414
+#define EMIF_OCP_CONFIG_AM335X_EVM             0x003d3d3d
+
 static inline int board_is_bone(void)
 {
 	return board_ti_is("A335BONE");

Signature · 1 line

1.9.1

Tom Rini

2016-12-08 14:30 UTC #1 lore raw

PATCH v2 1/1 arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm

Quoted 10 lines · Jyri Sarha

Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock.
Signed-off-by Jyri Sarha <[email protected]>

Reviewed-by Tom Rini <[email protected]>

But, does TI have a whitepaper or tech pub or anything that describes how one would calculate that value on a custom design? Tweaking that for optimal usage is something I know happens in some cases and could be used in a lot more. If there's a doc that explains how to figure it out, it would be good to link to it in the comments in the patch as well. Since I don't know that such a thing does exist I'll reviewed-by it now tho. Thanks!

Signature · 8 lines

Tom
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Jyri Sarha

author

2016-12-08 20:53 UTC #2 lore raw

PATCH v2 1/1 arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm

Quoted 15 lines · Tom Rini

Quoted 10 lines · Jyri Sarha
Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock.
Signed-off-by Jyri Sarha <[email protected]>
Reviewed-by Tom Rini <[email protected]>

Quoted 8 lines

But, does TI have a whitepaper or tech pub or anything that describes how one would calculate that value on a custom design? Tweaking that for optimal usage is something I know happens in some cases and could be used in a lot more. If there's a doc that explains how to figure it out, it would be good to link to it in the comments in the patch as well. Since I don't know that such a thing does exist I'll reviewed-by it now tho. Thanks!

No there is no such thing. Actually the documentation of the whole feature is quite limited in the public documentation. I could add a reference to "7.3.3.5.2 Command Starvation" in am335x TRM with a remark that "advanced bandwidth/prioritization control" the section mentions is broken in all currently available am3 revisions and only REG_PR_OLD_COUNT has real effect.

In practice the only rule to find an optimal value is to find as high as possible REG_PR_OLD_COUNT value that does not produce LCDC FIFO underflows under worst case scenario. The worst case happens when the highest pixel clock videomode with maximum bpp is used while memory subsystem is stressed by endless stream of writes hitting the same memory memory bank (can be the same address).

Best regards,
Jyri