clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk
Subsystems (4)
PATCH 1/1 clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk
bcm2835_pll_divider_off() is resetting the divider field in the A2W reg to zero when disabling the clock.
Make sure we preserve this value by reading the previous a2w_reg value first and ORing the result with A2W_PLL_CHANNEL_DISABLE.
--- drivers/clk/bcm/clk-bcm2835.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/clk/bcm/clk-bcm2835.c +3 -1
@@ -751,7 +751,9 @@ static void bcm2835_pll_divider_off(struct clk_hw *hw)cprman_write (cprman, data->cm_reg, (cprman_read (cprman, data->cm_reg) & ~data->load_mask) | data->hold_mask); -cprman_write (cprman, data->a2w_reg,A2W_PLL_CHANNEL_DISABLE ); +cprman_write (cprman, data->a2w_reg, +cprman_read (cprman, data->a2w_reg) | +A2W_PLL_CHANNEL_DISABLE );spin_unlock (&cprman->regs_lock); }
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2.7.4
PATCH 1/1 clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk
Quoted 9 lines · Boris Brezillon
bcm2835_pll_divider_off()is resetting the divider field in the A2W reg to zero when disabling the clock.Make sure we preserve this value by reading the previous
a2w_regvalue first and ORing the result withA2W_PLL_CHANNEL_DISABLE.Signed-off-by Boris Brezillon <[email protected]>Fixes 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")Cc <[email protected]>
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Stephen Boyd
AppliedPATCH 1/1 clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk
In reply to Boris BrezillonQuoted 10 lines · Boris Brezillon
bcm2835_pll_divider_off()is resetting the divider field in the A2W reg to zero when disabling the clock.Make sure we preserve this value by reading the previous
a2w_regvalue first and ORing the result withA2W_PLL_CHANNEL_DISABLE.Signed-off-by Boris Brezillon <[email protected]>Fixes 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")Cc <[email protected]>---
Applied to clk-next
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