add initial RISC-V architecture support
Subsystems (6)
v3 cover add initial RISC-V architecture support
This patchseries adds initial RISC-V architecture support for barebox.
See Documentation/boards/riscv.rst for instructions.
You can obtain this patchseries from github:
$ git clone -b 20161212.riscv https://github.com/frantony/barebox
Changes since RFC v2 (20161113) (http://lists.infradead.org/pipermail/barebox/2016-November/028533.html):
* add RV32 support.
Changes since RFC v1 (20161013) (http://lists.infradead.org/pipermail/barebox/2016-October/028309.html):
* drop spike pk support;
* add qemu-sifive board support;
* add Documentation/boards/riscv.rst;
* fix guard macro names.
TODOs:
* add nmon for RISC-V;
* run barebox on a real FPGA board.
Antony Pavlov (2):
serial: add driver for SiFive UART
Add initial RISC-V architecture support
Documentation/boards/riscv.rst | 93 +++++++++++++++++++++ arch/riscv/Kconfig | 76 +++++++++++++++++ arch/riscv/Makefile | 51 ++++++++++++ arch/riscv/boards/qemu-sifive/.gitignore | 1 + arch/riscv/boards/qemu-sifive/Makefile | 1 + arch/riscv/boards/qemu-sifive/board.c | 28 +++++++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 +++++++++ arch/riscv/boot/start.S | 44 ++++++++++ arch/riscv/configs/qemu-sifive-e300_defconfig | 76 +++++++++++++++++ arch/riscv/configs/qemu-sifive-u500_defconfig | 75 +++++++++++++++++ arch/riscv/dts/.gitignore | 1 + arch/riscv/dts/Makefile | 9 ++ arch/riscv/dts/qemu-sifive.dts | 19 +++++ arch/riscv/dts/skeleton.dtsi | 13 +++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 35 ++++++++ arch/riscv/include/asm/bitsperlong.h | 10 +++ arch/riscv/include/asm/byteorder.h | 12 +++ arch/riscv/include/asm/common.h | 6 ++ arch/riscv/include/asm/elf.h | 11 +++ arch/riscv/include/asm/io.h | 8 ++ arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 ++ arch/riscv/include/asm/types.h | 60 ++++++++++++++ arch/riscv/include/asm/unaligned.h | 19 +++++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 7 ++ arch/riscv/lib/ashldi3.c | 28 +++++++ arch/riscv/lib/ashrdi3.c | 30 +++++++ arch/riscv/lib/asm-offsets.c | 12 +++ arch/riscv/lib/barebox.lds.S | 87 ++++++++++++++++++++ arch/riscv/lib/dtb.c | 41 ++++++++++ arch/riscv/lib/libgcc.h | 29 +++++++ arch/riscv/lib/lshrdi3.c | 28 +++++++ arch/riscv/mach-sifive/Kconfig | 16 ++++ arch/riscv/mach-sifive/Makefile | 3 + arch/riscv/mach-sifive/include/mach/debug_ll.h | 38 +++++++++ drivers/of/Kconfig | 2 +- drivers/serial/Kconfig | 3 + drivers/serial/Makefile | 1 + drivers/serial/serial_sifive.c | 109 +++++++++++++++++++++++++ 44 files changed, 1134 insertions(+), 1 deletion(-) create mode 100644 Documentation/boards/riscv.rst create mode 100644 arch/riscv/Kconfig create mode 100644 arch/riscv/Makefile create mode 100644 arch/riscv/boards/qemu-sifive/.gitignore create mode 100644 arch/riscv/boards/qemu-sifive/Makefile create mode 100644 arch/riscv/boards/qemu-sifive/board.c create mode 100644 arch/riscv/boot/Makefile create mode 100644 arch/riscv/boot/main_entry.c create mode 100644 arch/riscv/boot/start.S create mode 100644 arch/riscv/configs/qemu-sifive-e300_defconfig create mode 100644 arch/riscv/configs/qemu-sifive-u500_defconfig create mode 100644 arch/riscv/dts/.gitignore create mode 100644 arch/riscv/dts/Makefile create mode 100644 arch/riscv/dts/qemu-sifive.dts create mode 100644 arch/riscv/dts/skeleton.dtsi create mode 100644 arch/riscv/include/asm/barebox.h create mode 100644 arch/riscv/include/asm/bitops.h create mode 100644 arch/riscv/include/asm/bitsperlong.h create mode 100644 arch/riscv/include/asm/byteorder.h create mode 100644 arch/riscv/include/asm/common.h create mode 100644 arch/riscv/include/asm/elf.h create mode 100644 arch/riscv/include/asm/io.h create mode 100644 arch/riscv/include/asm/posix_types.h create mode 100644 arch/riscv/include/asm/sections.h create mode 100644 arch/riscv/include/asm/string.h create mode 100644 arch/riscv/include/asm/swab.h create mode 100644 arch/riscv/include/asm/types.h create mode 100644 arch/riscv/include/asm/unaligned.h create mode 100644 arch/riscv/lib/.gitignore create mode 100644 arch/riscv/lib/Makefile create mode 100644 arch/riscv/lib/ashldi3.c create mode 100644 arch/riscv/lib/ashrdi3.c create mode 100644 arch/riscv/lib/asm-offsets.c create mode 100644 arch/riscv/lib/barebox.lds.S create mode 100644 arch/riscv/lib/dtb.c create mode 100644 arch/riscv/lib/libgcc.h create mode 100644 arch/riscv/lib/lshrdi3.c create mode 100644 arch/riscv/mach-sifive/Kconfig create mode 100644 arch/riscv/mach-sifive/Makefile create mode 100644 arch/riscv/mach-sifive/include/mach/debug_ll.h create mode 100644 drivers/serial/serial_sifive.c
Signature · 7 lines
2.10.2 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
RFC v3 1/2 serial: add driver for SiFive UART
Signed-off-by Antony Pavlov <[email protected]>
--
TODO:
* add speed setup support;
* add Tx FIFO check.
--- drivers/serial/Kconfig | 3 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_sifive.c | 109 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+)
drivers/serial/Kconfig +3 -0
@@ -117,6 +117,9 @@ config DRIVER_SERIAL_S3C_AUTOSYNC Say Y here if you want to use the auto flow feature of this UART. RTS and CTS will be handled by the hardware when enabled. +config DRIVER_SERIAL_SIFIVE + bool "SiFive serial driver" + config DRIVER_SERIAL_PXA bool "PXA serial driver" depends on ARCH_PXA
drivers/serial/Makefile +1 -0
@@ -20,3 +20,4 @@ obj-$(CONFIG_DRIVER_SERIAL_AUART) += serial_auart.o obj-$(CONFIG_DRIVER_SERIAL_CADENCE) += serial_cadence.o obj-$(CONFIG_DRIVER_SERIAL_EFI_STDIO) += efi-stdio.o obj-$(CONFIG_DRIVER_SERIAL_DIGIC) += serial_digic.o +obj-$(CONFIG_DRIVER_SERIAL_SIFIVE) += serial_sifive.o
drivers/serial/serial_sifive.c new file +109 -0
109 lines not on this page · raw message
Signature · 7 lines
2.10.2 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
RFC v3 2/2 Add initial RISC-V architecture support
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--
TODOs:
* split patch;
* use sifive timer IP-block.
--- Documentation/boards/riscv.rst | 93 ++++++++++++++++++++++++++ arch/riscv/Kconfig | 76 +++++++++++++++++++++ arch/riscv/Makefile | 51 ++++++++++++++ arch/riscv/boards/qemu-sifive/.gitignore | 1 + arch/riscv/boards/qemu-sifive/Makefile | 1 + arch/riscv/boards/qemu-sifive/board.c | 28 ++++++++ arch/riscv/boot/Makefile | 2 + arch/riscv/boot/main_entry.c | 40 +++++++++++ arch/riscv/boot/start.S | 44 ++++++++++++ arch/riscv/configs/qemu-sifive-e300_defconfig | 76 +++++++++++++++++++++ arch/riscv/configs/qemu-sifive-u500_defconfig | 75 +++++++++++++++++++++ arch/riscv/dts/.gitignore | 1 + arch/riscv/dts/Makefile | 9 +++ arch/riscv/dts/qemu-sifive.dts | 19 ++++++ arch/riscv/dts/skeleton.dtsi | 13 ++++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 35 ++++++++++ arch/riscv/include/asm/bitsperlong.h | 10 +++ arch/riscv/include/asm/byteorder.h | 12 ++++ arch/riscv/include/asm/common.h | 6 ++ arch/riscv/include/asm/elf.h | 11 +++ arch/riscv/include/asm/io.h | 8 +++ arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 ++ arch/riscv/include/asm/types.h | 60 +++++++++++++++++ arch/riscv/include/asm/unaligned.h | 19 ++++++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 7 ++ arch/riscv/lib/ashldi3.c | 28 ++++++++ arch/riscv/lib/ashrdi3.c | 30 +++++++++ arch/riscv/lib/asm-offsets.c | 12 ++++ arch/riscv/lib/barebox.lds.S | 87 ++++++++++++++++++++++++ arch/riscv/lib/dtb.c | 41 ++++++++++++ arch/riscv/lib/libgcc.h | 29 ++++++++ arch/riscv/lib/lshrdi3.c | 28 ++++++++ arch/riscv/mach-sifive/Kconfig | 16 +++++ arch/riscv/mach-sifive/Makefile | 3 + arch/riscv/mach-sifive/include/mach/debug_ll.h | 38 +++++++++++ drivers/of/Kconfig | 2 +- 41 files changed, 1021 insertions(+), 1 deletion(-)
Documentation/boards/riscv.rst new file +93 -0
@@ -0,0 +1,93 @@ +RISC-V +====== + +At the moment only qemu emulator is supported (see https://github.com/riscv/riscv-isa-sim +for details). + +Running RISC-V barebox +---------------------- + +Obtain RISC-V GCC/Newlib Toolchain, +see https://github.com/riscv/riscv-tools/blob/master/README.md +for details. The ``build.sh`` script from ``riscv-tools`` should +create toolchain. + +Next compile qemu emulator:: + + $ git clone https://github.com/riscv/riscv-qemu + $ cd riscv-qemu + $ cap="no" ./configure \ + --extra-cflags="-Wno-maybe-uninitialized" \ + --audio-drv-list="" \ + --disable-attr \ + --disable-blobs \ + --disable-bluez \ + --disable-brlapi \ + --disable-curl \ + --disable-curses \ + --disable-docs \ + --disable-kvm \ + --disable-spice \ + --disable-sdl \ + --disable-vde \ + --disable-vnc-sasl \ + --disable-werror \ + --enable-trace-backend=simple \ + --disable-stack-protector \ + --target-list=riscv32-softmmu,riscv64-softmmu + $ make + + +### barebox 32bit ### + +Next compile barebox:: + + $ make qemu-sifive-e300_defconfig ARCH=riscv + ... + $ make ARCH=riscv CROSS_COMPILE=<path to your riscv toolchain>/riscv32-unknown-elf- + +Run barebox:: + + $ <path to riscv-qemu source>/riscv32-softmmu/qemu-system-riscv32 \ + -nographic -M sifive -kernel <path to barebox sources >/barebox \ + -serial stdio -monitor none -trace file=/dev/null + + Switch to console [cs0] + + + barebox 2016.11.0-00006-g3c29f61 #1 Mon Nov 13 22:21:03 MSK 2016 + + + Board: QEMU SiFive + Warning: Using dummy clocksource + malloc space: 0x00800000 -> 0x00bfffff (size 4 MiB) + running /env/bin/init... + /env/bin/init not found + barebox:/ + +### barebox 64bit ### + +Next compile barebox:: + + $ make qemu-sifive-u500_defconfig ARCH=riscv + ... + $ make ARCH=riscv CROSS_COMPILE=<path to your riscv toolchain>/riscv64-unknown-elf- + +Run barebox:: + + $ <path to riscv-qemu source>/riscv64-softmmu/qemu-system-riscv64 \ + -nographic -M sifive -kernel <path to barebox sources >/barebox \ + -serial stdio -monitor none -trace file=/dev/null + + Switch to console [cs0] + + + barebox 2016.11.0-00006-g3c29f61 #1 Mon Nov 13 22:21:03 MSK 2016 + + + Board: QEMU SiFive + Warning: Using dummy clocksource + malloc space: 0x00800000 -> 0x00bfffff (size 4 MiB) + running /env/bin/init... + /env/bin/init not found + barebox:/
arch/riscv/Kconfig new file +76 -0
76 lines not on this page · raw message
arch/riscv/Makefile new file +51 -0
51 lines not on this page · raw message
arch/riscv/boards/qemu-sifive/.gitignore new file +1 -0
@@ -0,0 +1 @@ +barebox.lds
arch/riscv/boards/qemu-sifive/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-y += board.o
arch/riscv/boards/qemu-sifive/board.c new file +28 -0
@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <driver.h> +#include <init.h> + +static int hostname_init (void ) +{ +barebox_set_hostname ("barebox" ); + +return 0 ; +} +postcore_initcall (hostname_init);
arch/riscv/boot/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +obj-y += start.o +obj-y += main_entry.o
arch/riscv/boot/main_entry.c new file +40 -0
@@ -0,0 +1,40 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> +#include <asm/sections.h> + +void main_entry (void ); + +/** +* Called plainly from assembler code +* +* @note The C environment isn't initialized yet +*/ +void main_entry (void ) +{ +/* clear the BSS first */ +memset (__bss_start,0x00 , __bss_stop - __bss_start); + +mem_malloc_init ((void *)MALLOC_BASE , + (void *)(MALLOC_BASE +MALLOC_SIZE -1 )); + +start_barebox (); +}
arch/riscv/boot/start.S new file +44 -0
44 lines not on this page · raw message
arch/riscv/configs/qemu-sifive-e300_defconfig new file +76 -0
76 lines not on this page · raw message
arch/riscv/configs/qemu-sifive-u500_defconfig new file +75 -0
75 lines not on this page · raw message
arch/riscv/dts/.gitignore new file +1 -0
@@ -0,0 +1 @@ +*dtb*
arch/riscv/dts/Makefile new file +9 -0
@@ -0,0 +1,9 @@ +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o + +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
arch/riscv/dts/qemu-sifive.dts new file +19 -0
@@ -0,0 +1,19 @@ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "QEMU SiFive"; + compatible = "sifive,qemu"; + + /* Digilent Arty has 256MB DDR3L */ + memory { + device_type = "memory"; + reg = <0 0x80000000 0x10000000>; + }; + + uart: uart { + compatible = "sifive,uart"; + reg = <0 0x40002000 0x10>; + }; +};
arch/riscv/dts/skeleton.dtsi new file +13 -0
@@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0>; }; +};
arch/riscv/include/asm/barebox.h new file +1 -0
@@ -0,0 +1 @@ +/* dummy */
arch/riscv/include/asm/bitops.h new file +35 -0
@@ -0,0 +1,35 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +*/ + +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit (x, y) __set_bit(x, y) +#define clear_bit (x, y) __clear_bit(x, y) +#define change_bit (x, y) __change_bit(x, y) +#define test_and_set_bit (x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit (x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit (x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_BITOPS_H_ */
arch/riscv/include/asm/bitsperlong.h new file +10 -0
@@ -0,0 +1,10 @@ +#ifndef __ASM_BITSPERLONG_H +#define __ASM_BITSPERLONG_H + +#ifdef __riscv64 +#define BITS_PER_LONG 64 +#else +#define BITS_PER_LONG 32 +#endif + +#endif /* __ASM_BITSPERLONG_H */
arch/riscv/include/asm/byteorder.h new file +12 -0
@@ -0,0 +1,12 @@ +#ifndef _ASM_RISCV_BYTEORDER_H +#define _ASM_RISCV_BYTEORDER_H + +#if defined(__RISCVEL__) +#include <linux/byteorder/little_endian.h> +#elif defined(__RISCVEB__) +#include <linux/byteorder/big_endian.h> +#else +#error "Unknown endianness" +#endif + +#endif /* _ASM_RISCV_BYTEORDER_H */
arch/riscv/include/asm/common.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef ASM_RISCV_COMMON_H +#define ASM_RISCV_COMMON_H + +/* nothing special yet */ + +#endif /* ASM_RISCV_COMMON_H */
arch/riscv/include/asm/elf.h new file +11 -0
@@ -0,0 +1,11 @@ +#ifndef __ASM_RISCV_ELF_H__ +#define __ASM_RISCV_ELF_H__ + +#if __SIZEOF_POINTER__ ==8 +#define ELF_CLASS ELFCLASS64 +#define CONFIG_PHYS_ADDR_T_64BIT +#else +#define ELF_CLASS ELFCLASS32 +#endif + +#endif /* __ASM_RISCV_ELF_H__ */
arch/riscv/include/asm/io.h new file +8 -0
@@ -0,0 +1,8 @@ +#ifndef __ASM_RISCV_IO_H +#define __ASM_RISCV_IO_H + +#include <asm-generic/io.h> + +#define IO_SPACE_LIMIT 0 + +#endif /* __ASM_RISCV_IO_H */
arch/riscv/include/asm/posix_types.h new file +1 -0
@@ -0,0 +1 @@ +#include <asm-generic/posix_types.h>
arch/riscv/include/asm/sections.h new file +1 -0
@@ -0,0 +1 @@ +#include <asm-generic/sections.h>
arch/riscv/include/asm/string.h new file +1 -0
@@ -0,0 +1 @@ +/* dummy */
arch/riscv/include/asm/swab.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef _ASM_SWAB_H +#define _ASM_SWAB_H + +/* nothing. use generic functions */ + +#endif /* _ASM_SWAB_H */
arch/riscv/include/asm/types.h new file +60 -0
60 lines not on this page · raw message
arch/riscv/include/asm/unaligned.h new file +19 -0
@@ -0,0 +1,19 @@ +#ifndef _ASM_RISCV_UNALIGNED_H +#define _ASM_RISCV_UNALIGNED_H + +/* +* FIXME: this file is copy-n-pasted from sandbox's unaligned.h +*/ + +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif + +#endif /* _ASM_RISCV_UNALIGNED_H */
arch/riscv/lib/.gitignore new file +1 -0
@@ -0,0 +1 @@ +barebox.lds
arch/riscv/lib/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds + +obj-$(CONFIG_32BIT) += lshrdi3.o +obj-$(CONFIG_32BIT) += ashldi3.o +obj-$(CONFIG_32BIT) += ashrdi3.o + +obj-$(CONFIG_BUILTIN_DTB) += dtb.o
arch/riscv/lib/ashldi3.c new file +28 -0
@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashldi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.low =0 ; + w.s.high = (unsigned int ) uu.s.low << -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.low >> bm; + + w.s.low = (unsigned int ) uu.s.low << b; + w.s.high = ((unsigned int ) uu.s.high << b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashldi3);
arch/riscv/lib/ashrdi3.c new file +30 -0
@@ -0,0 +1,30 @@ +#include <module.h> + +#include "libgcc.h" + +long long __ashrdi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { +/* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >>31 ; + w.s.low = uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__ashrdi3);
arch/riscv/lib/asm-offsets.c new file +12 -0
@@ -0,0 +1,12 @@ +/* +* Generate definitions needed by assembly language modules. +* This code generates raw asm output which is post-processed to extract +* and format the required data. +*/ + +#include <linux/kbuild.h> + +int main (void ) +{ +return 0 ; +}
arch/riscv/lib/barebox.lds.S new file +87 -0
87 lines not on this page · raw message
arch/riscv/lib/dtb.c new file +41 -0
41 lines not on this page · raw message
arch/riscv/lib/libgcc.h new file +29 -0
@@ -0,0 +1,29 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); + +#ifdef __BIG_ENDIAN +struct DWstruct { +int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { +int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { +struct DWstruct s; +long long ll; +}DWunion ; + +long long __lshrdi3 (long long u,word_type b); +long long __ashldi3 (long long u,word_type b); +long long __ashrdi3 (long long u,word_type b); + +#endif /* __ASM_LIBGCC_H */
arch/riscv/lib/lshrdi3.c new file +28 -0
@@ -0,0 +1,28 @@ +#include <module.h> + +#include "libgcc.h" + +long long __lshrdi3 (long long u,word_type b) +{ +DWunion uu, w; +word_type bm; + +if (b ==0 ) +return u; + + uu.ll = u; + bm =32 - b; + +if (bm <=0 ) { + w.s.high =0 ; + w.s.low = (unsigned int ) uu.s.high >> -bm; + }else { +const unsigned int carries = (unsigned int ) uu.s.high << bm; + + w.s.high = (unsigned int ) uu.s.high >> b; + w.s.low = ((unsigned int ) uu.s.low >> b) | carries; + } + +return w.ll; +} +EXPORT_SYMBOL (__lshrdi3);
arch/riscv/mach-sifive/Kconfig new file +16 -0
@@ -0,0 +1,16 @@ +if MACH_SIFIVE + +config ARCH_TEXT_BASE + hex + default 0x00001000 + +choice + prompt "Board type" + +config BOARD_QEMU_SIFIVE + bool "qemu sifive" + select HAS_DEBUG_LL + +endchoice + +endif
arch/riscv/mach-sifive/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +# just to build a built-in.o. Otherwise compilation fails when no o-files is +# created. +obj- += dummy.o
arch/riscv/mach-sifive/include/mach/debug_ll.h new file +38 -0
@@ -0,0 +1,38 @@ +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* See file CREDITS for list of people who contributed to this project. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 +* as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#ifndef __MACH_SIFIVE_DEBUG_LL__ +#define __MACH_SIFIVE_DEBUG_LL__ + +/** @file +* This File contains declaration for early output support +*/ + +#include <linux/kconfig.h> +#include <asm/io.h> + +#define UART_BASE 0x40002000 +#define R_DATA (0 << 2) +#define R_RXCNT (2 << 2) + +static inline void PUTC_LL (int ch) +{ +if (IS_ENABLED (CONFIG_DEBUG_LL )) +__raw_writeb (ch, (u8 *)UART_BASE +R_DATA ); +} + +#endif /* __MACH_SIFIVE_DEBUG_LL__ */
drivers/of/Kconfig +1 -1
@@ -4,7 +4,7 @@ config OFTREE config OFTREE_MEM_GENERIC depends on OFTREE - depends on PPC || ARM || ARCH_EFI || OPENRISC || SANDBOX + depends on PPC || ARM || ARCH_EFI || OPENRISC || SANDBOX || RISCV def_bool y config DTC
Signature · 7 lines
2.10.2 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v3 2/2] Add initial RISC-V architecture support
arch/riscv/configs/qemu-sifive-e300_defconfig line 9
Quoted 5 lines
arch/riscv/configs/qemu-sifive-e300_defconfig new file +5
-0+CONFIG_TEXT_BASE=0x80000000 +CONFIG_MEMORY_LAYOUT_FIXED=y +CONFIG_STACK_BASE=0x807f0000 +CONFIG_STACK_SIZE=0x10000 +CONFIG_MALLOC_BASE=0x80800000
Due to changed offsets in e300/u500 configurations (as compared to v2- qemu config) linkage fails with binutils-2.25.1 and gcc-5.3.0:
arch/riscv/boot/built-in.o: In function `main_entry':
/build/barebox/arch/riscv/boot/main_entry.c:34:(.text+0x0): relocation truncated to fit: R_RISCV_HI20 against symbol `__bss_start' defined in .bss section in barebox
Makefile:756: recipe for target 'barebox' failed
_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
Re: [RFC v3 2/2] Add initial RISC-V architecture support
Quoted 9 lines · On Tue, 13 Dec 2016 20:02:41 +0300 Andrey Korolyov <[email protected]> wrote:
Review
Quoted 5 lines
(quoted diff) +5
-0+CONFIG_TEXT_BASE=0x80000000 +CONFIG_MEMORY_LAYOUT_FIXED=y +CONFIG_STACK_BASE=0x807f0000 +CONFIG_STACK_SIZE=0x10000 +CONFIG_MALLOC_BASE=0x80800000Due to changed offsets in e300/u500 configurations (as compared to v2- qemu config) linkage fails with binutils-2.25.1 and gcc-5.3.0:
Quoted 5 lines
arch/riscv/boot/built-in.o: In function `main_entry':
/build/barebox/arch/riscv/boot/main_entry.c:34:(.text+0x0): relocation truncated to fit:R_RISCV_HI20against symbol `__bss_start' defined in .bss section in barebox
Makefile:756: recipe for target 'barebox' failed
You can fix the problem by explicitly selecting the 'Medium/Anywhere' gcc code model, e.g.
arch/riscv/Makefile +1 -1
@@ -2,7 +2,7 @@ CPPFLAGS += -fno-strict-aliasing cflags-y += -fno-pic -pipe cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \ - -Wno-uninitialized -Wno-format -Wno-main + -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany LDFLAGS += $(ldflags-y) LDFLAGS_barebox += -nostdlib
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox