FAILED: patch "[PATCH] perf/x86: Fix full width counter, counter overflow" failed to apply to 4.4-stable tree

From 7f612a7f0bc13a2361a152862435b7941156b6af Mon Sep 17 00:00:00 2001

The patch below does not apply to the 4.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From 7f612a7f0bc13a2361a152862435b7941156b6af Mon Sep 17 00:00:00 2001

From: "Peter Zijlstra (Intel)" <[email protected]>
Date: Tue, 29 Nov 2016 20:33:28 +0000
Subject: [PATCH] perf/x86: Fix full width counter, counter overflow

Lukasz reported that perf stat counters overflow handling is broken on KNL/SLM.

Both these parts have full_width_write set, and that does indeed have a problem. In order to deal with counter wrap, we must sample the counter at at least half the counter period (see also the sampling theorem) such that we can unambiguously reconstruct the count.

However commit:

069e0c3c4058 ("perf/x86/intel: Support full width counting")

sets the sampling interval to the full period, not half.

Fixing that exposes another issue, in that we must not sign extend the delta value when we shift it right; the counter cannot have decremented after all.

With both these issues fixed, counter overflow functions correctly again.

Reported-by Lukasz Odzioba <[email protected]>

Tested-by Liang, Kan <[email protected]>

Tested-by Odzioba, Lukasz <[email protected]>

Signed-off-by Peter Zijlstra (Intel) <[email protected]>

Cc Alexander Shishkin <[email protected]>

Cc Arnaldo Carvalho de Melo <[email protected]>

Cc Jiri Olsa <[email protected]>

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Stephane Eranian <[email protected]>

Cc Thomas Gleixner <[email protected]>

Cc Vince Weaver <[email protected]>

Cc [email protected]

Fixes 069e0c3c4058 ("perf/x86/intel: Support full width counting")

Signed-off-by Ingo Molnar <[email protected]>

arch/x86/events/core.c +1 -1

index 9d4bf3ab049e..6e395c996900 100644
@@ -69,7 +69,7 @@ u64 x86_perf_event_update(struct perf_event *event)
 	int shift = 64 - x86_pmu.cntval_bits;
 	u64 prev_raw_count, new_raw_count;
 	int idx = hwc->idx;
-	s64 delta;
+	u64 delta;
 
 	if (idx == INTEL_PMC_IDX_FIXED_BTS)
 		return 0;

arch/x86/events/intel/core.c +1 -2

index a74a2dbc0180..cb8522290e6a 100644
@@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void)
 
 	/* Support full width counters using alternative MSR range */
 	if (x86_pmu.intel_cap.full_width_write) {
-		x86_pmu.max_period = x86_pmu.cntval_mask;
+		x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
 		x86_pmu.perfctr = MSR_IA32_PMC0;
 		pr_cont("full-width counters, ");
 	}
 
--

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Nevermind, I got it to work, sorry for the noise...