clk: sunxi-ng: A31: Fix spdif clock register
Subsystems (2)
PATCH 1/1 clk: sunxi-ng: A31: Fix spdif clock register
From: Marcus Cooper <[email protected]>
As the SPDIF was rarely documented on the earlier Allwinner SoCs it was assumed that it had a similar clock register to the one described in the H3 User Manual.
However this is not the case and it looks to shares the same setup as the I2S clock registers.
Signed-off-by Marcus Cooper <[email protected]>
--- drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/clk/sunxi-ng/ccu-sun6i-a31.c +2 -2
@@ -468,8 +468,8 @@ static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents, static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents, 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); -static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", - 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); +static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents, + 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0x0cc, BIT(8), 0);
Signature · 1 line
2.11.0
Maxime Ripard
AppliedPATCH 1/1 clk: sunxi-ng: A31: Fix spdif clock register
Quoted 10 lines · codekipper at gmail.com
From: Marcus Cooper <[email protected]>
As the SPDIF was rarely documented on the earlier Allwinner SoCs it was assumed that it had a similar clock register to the one described in the H3 User Manual.
However this is not the case and it looks to shares the same setup as the I2S clock registers.
Signed-off-by Marcus Cooper <[email protected]>
Applied, thanks!
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161220/632bbf56/attachment.sig>