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arm64/clk: update Marvell Armada CP110 system controller driver

PATCH New Thomas Petazzoni 3 participants 14 messages Dec 21, 2016 – Mar 1, 2017

Subsystems (3)
Device tree bindings Common clk Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support
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Thomas Petazzoni

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#0 lore raw

v2 cover arm64/clk: update Marvell Armada CP110 system controller driver

Hello,

This small set of commits updates the Marvell Armada CP110 system controller driver, its Device Tree binding, and Device Tree representation, to take into account three new things:

- The clock driver now handles clock n?9 (GOP) as a child of clock n?18 (controls SD/MMC and GOP)

- The DT representation is adjusted to name clock n?18 "sd-mmc-gop" instead of just "sd-mmc".

- The clock driver now handles clock n?5 (MG) as a child of clock n?6 (MG_CORE).

This set of commits is some preparation work to add networking support for Marvell Armada 7K/8K.

I would expect patches 1 and 2 to be taken by the clock maintainers, and patch 3 be taken by the Marvell EBU maintainers.

Changes since v1:

- Addition of the handling of the MG and MG_CORE clocks (n?5 and n?6), also needed for the networking support on Marvell Aramda 7K/8K.

Thanks,

Thomas

Thomas Petazzoni (3):
dt-bindings: arm: update Armada CP110 system controller binding
clk: mvebu: adjust clock handling for the CP110 system controller
arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon

 .../bindings/arm/marvell/cp110-system-controller0.txt       |  6 +++---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi        |  2 +-
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi         |  2 +-
 drivers/clk/mvebu/cp110-system-controller.c                 | 13 +++++++++++--
 4 files changed, 16 insertions(+), 7 deletions(-)
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH v2 1/3 dt-bindings: arm: update Armada CP110 system controller binding

It turns out that in the CP110 HW block present in Marvell Armada 7K/8K SoCs, gatable clock n?18 not only controls SD/MMC, but also the GOP block. This commit updates the Device Tree binding for this piece of hardware accordingly.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 .../devicetree/bindings/arm/marvell/cp110-system-controller0.txt    | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt +3 -3
index 30c5469..07dbb35 100644
@@ -45,7 +45,7 @@ The following clocks are available:
    - 1 15	SATA
    - 1 16	SATA USB
    - 1 17	Main
-   - 1 18	SD/MMC
+   - 1 18	SD/MMC/GOP
    - 1 21	Slow IO (SPI, NOR, BootROM, I2C, UART)
    - 1 22	USB3H0
    - 1 23	USB3H1

@@ -65,7 +65,7 @@ Required properties:
 	"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
 	"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
 	"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
-	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
+	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
 	"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
 
 Example:

@@ -78,6 +78,6 @@ Example:
 		gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
 			"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
 			"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
-			"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
+			"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
 			"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
 	};
Signature · 1 line
2.7.4
Applied
#2 lore raw

PATCH v2 1/3 dt-bindings: arm: update Armada CP110 system controller binding

Quoted 7 lines · Thomas Petazzoni

It turns out that in the CP110 HW block present in Marvell Armada 7K/8K SoCs, gatable clock n?18 not only controls SD/MMC, but also the GOP block. This commit updates the Device Tree binding for this piece of hardware accordingly.

Signed-off-by Thomas Petazzoni <[email protected]>

---

Applied to clk-next

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#3 lore raw

PATCH v2 1/3 dt-bindings: arm: update Armada CP110 system controller binding

Stephen,

Quoted 10 lines · Stephen Boyd
Quoted 7 lines · Thomas Petazzoni

It turns out that in the CP110 HW block present in Marvell Armada 7K/8K SoCs, gatable clock n?18 not only controls SD/MMC, but also the GOP block. This commit updates the Device Tree binding for this piece of hardware accordingly.

Signed-off-by Thomas Petazzoni <[email protected]>

---

Applied to clk-next

Even though you said you applied it, I still don't see this patch in mainline, while PATCH 2/3 of this series is now in mainline.

Was this patch forgotten? Let me know if I should resend it, but I'm pretty sure it still applies, since no other changes on this file have been merged since quite a while.

Thanks,

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
#4 lore raw

PATCH v2 1/3 dt-bindings: arm: update Armada CP110 system controller binding

Quoted 12 lines · Thomas Petazzoni

Stephen,

Quoted 9 lines · Stephen Boyd
Quoted 7 lines · Thomas Petazzoni

It turns out that in the CP110 HW block present in Marvell Armada 7K/8K SoCs, gatable clock n?18 not only controls SD/MMC, but also the GOP block. This commit updates the Device Tree binding for this piece of hardware accordingly.

Signed-off-by Thomas Petazzoni <[email protected]>

---

Quoted 9 lines
Quoted 1 line

Applied to clk-next

Even though you said you applied it, I still don't see this patch in mainline, while PATCH 2/3 of this series is now in mainline.

Was this patch forgotten? Let me know if I should resend it, but I'm pretty sure it still applies, since no other changes on this file have been merged since quite a while.

No worries. I've made a note to put it into the fixes queue to send off after rc1.

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#5 lore raw

PATCH v2 1/3 dt-bindings: arm: update Armada CP110 system controller binding

Hello,

Quoted 10 lines · Stephen Boyd
Quoted 7 lines

Even though you said you applied it, I still don't see this patch in mainline, while PATCH 2/3 of this series is now in mainline.

Was this patch forgotten? Let me know if I should resend it, but I'm pretty sure it still applies, since no other changes on this file have been merged since quite a while.

No worries. I've made a note to put it into the fixes queue to send off after rc1.

Great, thanks a lot. It's not a big thing, but it keeps popping up in my list of "things accepted by the maintainer, but not yet completely merged upstream" :-)

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
author
#6 lore raw

PATCH v2 2/3 clk: mvebu: adjust clock handling for the CP110 system controller

In reply to Thomas Petazzoni

This commit:

- makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP.

- makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6)

Signed-off-by Thomas Petazzoni <[email protected]>
---
 drivers/clk/mvebu/cp110-system-controller.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)
drivers/clk/mvebu/cp110-system-controller.c +11 -2
index f2303da..8038b93 100644
@@ -64,8 +64,11 @@ enum {
 #define CP110_GATE_NAND			2
 #define CP110_GATE_PPV2			3
 #define CP110_GATE_SDIO			4
+#define CP110_GATE_MG			5
+#define CP110_GATE_MG_CORE		6
 #define CP110_GATE_XOR1			7
 #define CP110_GATE_XOR0			8
+#define CP110_GATE_GOP_DP		9
 #define CP110_GATE_PCIE_X1_0		11
 #define CP110_GATE_PCIE_X1_1		12
 #define CP110_GATE_PCIE_X4		13

@@ -73,7 +76,7 @@ enum {
 #define CP110_GATE_SATA			15
 #define CP110_GATE_SATA_USB		16
 #define CP110_GATE_MAIN			17
-#define CP110_GATE_SDMMC		18
+#define CP110_GATE_SDMMC_GOP		18
 #define CP110_GATE_SLOW_IO		21
 #define CP110_GATE_USB3H0		22
 #define CP110_GATE_USB3H1		23

@@ -302,6 +305,11 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
 						      "gate-clock-output-names",
 						      CP110_GATE_MAIN, &parent);
 			break;
+		case CP110_GATE_MG:
+			of_property_read_string_index(np,
+						      "gate-clock-output-names",
+						      CP110_GATE_MG_CORE, &parent);
+			break;
 		case CP110_GATE_NAND:
 			parent = nand_name;
 			break;

@@ -309,9 +317,10 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
 			parent = ppv2_name;
 			break;
 		case CP110_GATE_SDIO:
+		case CP110_GATE_GOP_DP:
 			of_property_read_string_index(np,
 						      "gate-clock-output-names",
-						      CP110_GATE_SDMMC, &parent);
+						      CP110_GATE_SDMMC_GOP, &parent);
 			break;
 		case CP110_GATE_XOR1:
 		case CP110_GATE_XOR0:
Signature · 1 line
2.7.4
Applied
#7 lore raw

PATCH v2 2/3 clk: mvebu: adjust clock handling for the CP110 system controller

Quoted 7 lines · Thomas Petazzoni

This commit:

- makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP.

Quoted 5 lines

- makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6)

Signed-off-by Thomas Petazzoni <[email protected]>

---

Applied to clk-next

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#8 lore raw

PATCH v2 2/3 clk: mvebu: adjust clock handling for the CP110 system controller

Hello Stephen,

Quoted 8 lines · Stephen Boyd
Quoted 7 lines · Thomas Petazzoni

This commit:

- makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP.

Quoted 7 lines
Quoted 5 lines

- makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6)

Signed-off-by Thomas Petazzoni <[email protected]>

---

Applied to clk-next

I don't see my patch in clk-next at
https://git.kernel.org/cgit/linux/kernel/git/clk/linux.git/log/drivers/clk/mvebu/cp110-system-controller.c?h=clk-next,
nor in linux-next. Am I missing something?

Thanks a lot,

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
#9 lore raw

PATCH v2 2/3 clk: mvebu: adjust clock handling for the CP110 system controller

Quoted 14 lines · Thomas Petazzoni

Hello Stephen,

Quoted 11 lines · Stephen Boyd
Quoted 10 lines · Thomas Petazzoni

This commit:

- makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP.

- makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6)

Quoted 9 lines
Quoted 4 lines
Quoted 2 lines
Signed-off-by Thomas Petazzoni <[email protected]>

---

Applied to clk-next

I don't see my patch in clk-next at
https://git.kernel.org/cgit/linux/kernel/git/clk/linux.git/log/drivers/clk/mvebu/cp110-system-controller.c?h=clk-next,
nor in linux-next. Am I missing something?

Odd. I don't know what happened. I've applied it now.

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#10 lore raw

PATCH v2 2/3 clk: mvebu: adjust clock handling for the CP110 system controller

Hello,

Quoted 5 lines · Stephen Boyd
Quoted 3 lines

I don't see my patch in clk-next at
https://git.kernel.org/cgit/linux/kernel/git/clk/linux.git/log/drivers/clk/mvebu/cp110-system-controller.c?h=clk-next,
nor in linux-next. Am I missing something?

Odd. I don't know what happened. I've applied it now.

I think you also forgot to apply:

[PATCHv2 1/3] dt-bindings: arm: update Armada CP110 system controller binding

from the same series. You told me "Applied to clk-next", but I don't see it in linux-next.

Thanks!

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
author
#11 lore raw

PATCH v2 3/3 arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon

In reply to Thomas Petazzoni

This commit adjusts the names of gatable clock #18 of the Marvell Armada CP110 system controller. This clock not only controls SD/MMC, but also the GOP (Group Of Ports) used for networking. So the clock is renamed to {cpm,cps}-sd-mmc-gop instead of {cpm,cps}-sd-mmc.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -1
index 602e2c2..895babc 100644
@@ -74,7 +74,7 @@
 					"cpm-gop-dp", "none", "cpm-pcie_x10",
 					"cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
 					"cpm-sata", "cpm-sata-usb", "cpm-main",
-					"cpm-sd-mmc", "none", "none",
+					"cpm-sd-mmc-gop", "none", "none",
 					"cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
 					"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
 			};
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +1 -1
index 6bf9e24..db99646 100644
@@ -74,7 +74,7 @@
 					"cps-gop-dp", "none", "cps-pcie_x10",
 					"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
 					"cps-sata", "cps-sata-usb", "cps-main",
-					"cps-sd-mmc", "none", "none",
+					"cps-sd-mmc-gop", "none", "none",
 					"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
 					"cps-usb3dev", "cps-eip150", "cps-eip197";
 			};
Signature · 1 line
2.7.4
author
#12 lore raw

PATCH v2 3/3 arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon

Hello,

Quoted 6 lines · Thomas Petazzoni

This commit adjusts the names of gatable clock #18 of the Marvell Armada CP110 system controller. This clock not only controls SD/MMC, but also the GOP (Group Of Ports) used for networking. So the clock is renamed to {cpm,cps}-sd-mmc-gop instead of {cpm,cps}-sd-mmc.

Signed-off-by Thomas Petazzoni <[email protected]>

Gr?gory, since patches 1/3 and 2/3 of this series have been applied, could you take this PATCH 3/3 ?

Thanks!

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
#13 lore raw

PATCH v2 3/3 arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon

Hi Thomas,

Quoted 8 lines · Thomas Petazzoni

Hello,

Quoted 5 lines · Thomas Petazzoni

This commit adjusts the names of gatable clock #18 of the Marvell Armada CP110 system controller. This clock not only controls SD/MMC, but also the GOP (Group Of Ports) used for networking. So the clock is renamed to {cpm,cps}-sd-mmc-gop instead of {cpm,cps}-sd-mmc.

Quoted 4 lines
Quoted 1 line
Signed-off-by Thomas Petazzoni <[email protected]>

Gr?gory, since patches 1/3 and 2/3 of this series have been applied, could you take this PATCH 3/3 ?

I completely missed this patch!

Now, applied on mvebu/dt64

Thanks,

Gregory

Quoted 8 lines

Thanks!

Thomas

Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Signature · 4 lines
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com