arm64: Define Falkor v1 CPU
Subsystems (4)
PATCH v2 1/5 arm64: Define Falkor v1 CPU
From: Shanker Donthineni <[email protected]>
Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner.
--- arch/arm64/include/asm/cputype.h | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm64/include/asm/cputype.h +4 -0
@@ -71,6 +71,7 @@#define ARM_CPU_IMP_APM 0x50#define ARM_CPU_IMP_CAVIUM 0x43#define ARM_CPU_IMP_BRCM 0x42 +#define ARM_CPU_IMP_QCOM 0x51#define ARM_CPU_PART_AEM_V8 0xD0F#define ARM_CPU_PART_FOUNDATION 0xD00
@@ -84,10 +85,13 @@#define BRCM_CPU_PART_VULCAN 0x516 +#define QCOM_CPU_PART_FALKOR_V1 0x800 +#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) +#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)#ifndef __ASSEMBLY__
Signature · 3 lines
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
PATCH v2 2/5 arm64: Work around Falkor erratum 1003
From: Shanker Donthineni <[email protected]>
On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may allocate TLB entries using an incorrect ASID when TTBRx_EL1 is being updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields separately using a reserved ASID will ensure that there are no TLB entries with incorrect ASID after changing the the ASID.
Pseudo code:
write TTBRx_EL1[ASID] to a reserved value
ISB
write TTBRx_EL1[BADDR] to a desired value
ISB
write TTBRx_EL1[ASID] to a desired value
ISB
--- Documentation/arm64/silicon-errata.txt | 43 +++++++++++++++++----------------- arch/arm64/Kconfig | 16 +++++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 7 ++++++ arch/arm64/mm/context.c | 10 ++++++++ arch/arm64/mm/proc.S | 12 ++++++++++ 6 files changed, 69 insertions(+), 22 deletions(-)
Documentation/arm64/silicon-errata.txt +22 -21
@@ -42,24 +42,25 @@ file acts as a registry of software workarounds in the Linux Kernel and will be updated when new workarounds are committed and backported to stable kernels. -| Implementor | Component | Erratum ID | Kconfig | -+----------------+-----------------+-----------------+-------------------------+ -| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | -| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | -| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | -| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | -| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 | -| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | -| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | -| ARM | Cortex-A57 | #852523 | N/A | -| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | -| ARM | Cortex-A72 | #853709 | N/A | -| ARM | MMU-500 | #841119,#826419 | N/A | -| | | | | -| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | -| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | -| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | -| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | -| Cavium | ThunderX SMMUv2 | #27704 | N/A | -| | | | | -| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +| Implementor | Component | Erratum ID | Kconfig | ++---------------+-----------------+-----------------+--------------------------+ +| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | +| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | +| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | +| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | +| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 | +| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | +| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | +| ARM | Cortex-A57 | #852523 | N/A | +| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | +| ARM | Cortex-A72 | #853709 | N/A | +| ARM | MMU-500 | #841119,#826419 | N/A | +| | | | | +| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | +| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | +| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | +| Cavium | ThunderX SMMUv2 | #27704 | N/A | +| | | | | +| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +| Qualcomm | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
arch/arm64/Kconfig +16 -0
@@ -479,6 +479,22 @@ config CAVIUM_ERRATUM_27456 If unsure, say Y. +config QCOM_FALKOR_ERRATUM_1003 + bool "Falkor E1003: Incorrect translation due to ASID change" + default y + help + An incorrect translation TLBI entry may be created while + changing the ASID & translation table address together for + TTBR0_EL1. The workaround for this issue is use a reserved + ASID in cpu_do_switch_mm() before switching to target ASID. + + If unsure, say Y. + +config QCOM_FALKOR_E1003_RESERVED_ASID + int + default 1 + depends on QCOM_FALKOR_ERRATUM_1003 + endmenu
arch/arm64/include/asm/cpucaps.h +2 -1
@@ -35,7 +35,8 @@#define ARM64_HYP_OFFSET_LOW 14#define ARM64_MISMATCHED_CACHE_LINE_SIZE 15#define ARM64_HAS_NO_FPSIMD 16 +#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 17 -#define ARM64_NCAPS 17 +#define ARM64_NCAPS 18#endif /* __ASM_CPUCAPS_H */
arch/arm64/kernel/cpu_errata.c +7 -0
@@ -130,6 +130,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .def_scope = SCOPE_LOCAL_CPU, .enable = cpu_enable_trap_ctr_access, }, +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 + { + .desc = "Qualcomm Falkor erratum 1003", + .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, + MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0x00, 0x00), + }, +#endif { } };
arch/arm64/mm/context.c +10 -0
@@ -87,6 +87,11 @@ static void flush_context(unsigned int cpu)/* Update the list of reserved ASIDs and the ASID bitmap. */ bitmap_clear (asid_map,0 ,NUM_USER_ASIDS ); +/* Reserve ASID for Falkor erratum 1003 */ +if (IS_ENABLED (CONFIG_QCOM_FALKOR_ERRATUM_1003 ) && +cpus_have_cap (ARM64_WORKAROUND_QCOM_FALKOR_E1003 )) +__set_bit (CONFIG_QCOM_FALKOR_E1003_RESERVED_ASID , asid_map); +/* * Ensure the generation bump is observed before we xchg the * active_asids.
@@ -244,6 +249,11 @@ static int asids_init(void)panic ("Failed to allocate bitmap for %lu ASIDs\n" ,NUM_USER_ASIDS ); +/* Reserve ASID for Falkor erratum 1003 */ +if (IS_ENABLED (CONFIG_QCOM_FALKOR_ERRATUM_1003 ) && +cpus_have_cap (ARM64_WORKAROUND_QCOM_FALKOR_E1003 )) +__set_bit (CONFIG_QCOM_FALKOR_E1003_RESERVED_ASID , asid_map); +pr_info ("ASID allocator initialised with %lu entries\n" ,NUM_USER_ASIDS );return 0 ; }
arch/arm64/mm/proc.S +12 -0
@@ -140,6 +140,18 @@ ENDPROC(cpu_do_resume) ENTRY(cpu_do_switch_mm) mmid x1, x1 // get mm->context.id bfi x0, x1, #48, #16 // set the ASID +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 + mrs x2, ttbr0_el1 // get cuurent TTBR0_EL1 + mov x3, #CONFIG_QCOM_FALKOR_ERRATUM_1003 // reserved ASID + bfi x2, x3, #48, #16 // set the reserved ASID + old BADDR + msr ttbr0_el1, x2 // update TTBR0_EL1 + isb + bfi x2, x0, #0, #48 // set the desired BADDR + reserved ASID + msr ttbr0_el1, x2 // update TTBR0_EL1 + isb +alternative_else_nop_endif +#endif msr ttbr0_el1, x0 // set TTBR0 isb post_ttbr0_update_workaround
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Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Quoted 35 lines · Christopher Covington
-| Implementor | Component | Erratum ID |
Kconfig|
-+----------------+-----------------+-----------------+-------------------------+-| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | -| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | -| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | -| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | -| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 | -| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | -| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | -| ARM | Cortex-A57 | #852523 | N/A | -| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | -| ARM | Cortex-A72 | #853709 | N/A | -| ARM | MMU-500 | #841119,#826419 | N/A | -| | | | | -| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | -| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | -| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | -| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | -| Cavium | ThunderX SMMUv2 | #27704 | N/A | -| | | | | -| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +| Implementor | Component | Erratum ID | Kconfig | ++---------------+-----------------+-----------------+--------------------------+ +| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | +| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | +| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | +| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | +| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 | +| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | +| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | +| ARM | Cortex-A57 | #852523 | N/A | +| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | +| ARM | Cortex-A72 | #853709 | N/A | +| ARM | MMU-500 | #841119,#826419 | N/A | +| | | | |
Quoted 8 lines
+| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | +| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | +| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | +| Cavium | ThunderX SMMUv2 | #27704 | N/A | +| | | | | +| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +| Qualcomm | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
Looks like you've made an unrelated whitespace change that affected the entire table, not just the line you're adding.
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Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Quoted 45 lines · Timur Tabi
Quoted 35 lines · Christopher Covington
-| Implementor | Component | Erratum ID |
Kconfig|
-+----------------+-----------------+-----------------+-------------------------+-| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | -| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | -| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | -| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | -| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 | -| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | -| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | -| ARM | Cortex-A57 | #852523 | N/A | -| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | -| ARM | Cortex-A72 | #853709 | N/A | -| ARM | MMU-500 | #841119,#826419 | N/A | -| | | | | -| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | -| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | -| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | -| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | -| Cavium | ThunderX SMMUv2 | #27704 | N/A | -| | | | | -| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +| Implementor | Component | Erratum ID | Kconfig | ++---------------+-----------------+-----------------+--------------------------+ +| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | +| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | +| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | +| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | +| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 | +| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | +| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | +| ARM | Cortex-A57 | #852523 | N/A | +| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | +| ARM | Cortex-A72 | #853709 | N/A | +| ARM | MMU-500 | #841119,#826419 | N/A | +| | | | |Quoted 8 lines
+| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | +| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | +| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | +| Cavium | ThunderX SMMUv2 | #27704 | N/A | +| | | | | +| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +| Qualcomm | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
Quoted 2 lines
Looks like you've made an unrelated whitespace change that affected the entire table, not just the line you're adding.
I'm making space for "QCOM_FALKOR_ERRATUM_1003".
Cov
Signature · 3 lines
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Quoted 3 lines · Christopher Covington
Quoted 2 lines
Quoted 2 lines
Looks like you've made an unrelated whitespace change that affected the entire table, not just the line you're adding.
I'm making space for "
QCOM_FALKOR_ERRATUM_1003".
Ok, but you're also shrinking the other columns. I think a better solution is to make the macro shorter. QCOM_ERRATUM_FLK1003?
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Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
In reply to Christopher Covingtonarch/arm64/Kconfig config CAVIUM_ERRATUM_27456 · line 496
Quoted 4 lines · Christopher Covington
arch/arm64/Kconfig +4
-0+config QCOM_FALKOR_E1003_RESERVED_ASID + int + default 1 + depends on QCOM_FALKOR_ERRATUM_1003
Also, since this can't be changed via the menu, why bother putting it in?
Signature · 3 lines
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Quoted 7 lines · Timur Tabi
arch/arm64/Kconfig config CAVIUM_ERRATUM_27456 · line 496
Quoted 4 lines · Christopher Covington
arch/arm64/Kconfig +4
-0+config QCOM_FALKOR_E1003_RESERVED_ASID + int + default 1 + depends on QCOM_FALKOR_ERRATUM_1003Also, since this can't be changed via the menu, why bother putting it in?
I put it in in response to review comments asking for the magic number to be clarified by a #define or variable. I could not find a suitably shared header between the files in question, so I used the Kconfig machinery to generate the #define.
Cov
Signature · 3 lines
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Quoted 5 lines · Christopher Covington
Quoted 1 line
Quoted 1 line
Also, since this can't be changed via the menu, why bother putting it in?
I put it in in response to review comments asking for the magic number to be clarified by a #define or variable. I could not find a suitably shared header between the files in question, so I used the
Kconfigmachinery to generate the #define.
I don't think that's the right approach. Kconfigs are not an alternative to header files. Is the ASID configurable? If you just put some text after the "int" then it because a menu option that the user can select and change.
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kbuild test robot
build botRe: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
In reply to Christopher Covingtonurl: https://github.com/0day-ci/linux/commits/Christopher-Covington/arm64-Define-Falkor-v1-CPU/20161230-081412 config: arm64-allnoconfig (attached as .config) compiler: aarch64-linux-gnu-gcc (Debian…
Hi Shanker,
[auto build test ERROR on next-20161224]
[also build test ERROR on v4.10-rc1]
[cannot apply to arm64/for-next/core v4.9-rc8 v4.9-rc7 v4.9-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Christopher-Covington/arm64-Define-Falkor-v1-CPU/20161230-081412
config: arm64-allnoconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All errors (new ones prefixed by >>):
arch/arm64/mm/context.c: In function 'flush_context':
>> arch/arm64/mm/context.c:93:13: error: 'CONFIG_QCOM_FALKOR_E1003_RESERVED_ASID' undeclared (first use in this function)
__set_bit(CONFIG_QCOM_FALKOR_E1003_RESERVED_ASID, asid_map);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/mm/context.c:93:13: note: each undeclared identifier is reported only once for each function it appears in
arch/arm64/mm/context.c: In function 'asids_init':
arch/arm64/mm/context.c:255:13: error: 'CONFIG_QCOM_FALKOR_E1003_RESERVED_ASID' undeclared (first use in this function)
__set_bit(CONFIG_QCOM_FALKOR_E1003_RESERVED_ASID, asid_map);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~vim +/CONFIG_QCOM_FALKOR_E1003_RESERVED_ASID +93 arch/arm64/mm/context.c
87 /* Update the list of reserved ASIDs and the ASID bitmap. */
88 bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
89
90 /* Reserve ASID for Falkor erratum 1003 */
91 if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_1003) &&
92 cpus_have_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003))
> 93 __set_bit(CONFIG_QCOM_FALKOR_E1003_RESERVED_ASID, asid_map);
94
95 /*
96 * Ensure the generation bump is observed before we xchg the---
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Mark Rutland
reviewerRe: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
In reply to Christopher CovingtonHi,
arch/arm64/Kconfig config CAVIUM_ERRATUM_27456 · line 497
Quoted 5 lines · Christopher Covington
arch/arm64/Kconfig +5
-0+config QCOM_FALKOR_E1003_RESERVED_ASID + int + default 1 + depends on QCOM_FALKOR_ERRATUM_1003 +
I don't think this needs to be configurable, so let's drop this into a header, e.g. drop:
#define FALKOR_RESERVED_ASID 1
... in <asm/mmu_context.h>, protecting the rest with an ifndef __ASSEMBLY__ guard.
[...]
arch/arm64/mm/proc.S ENDPROC(cpu_do_resume) · line 146
Quoted 4 lines
arch/arm64/mm/proc.S +4
-0+#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 + mrs x2, ttbr0_el1 // get cuurent TTBR0_EL1 + mov x3, #CONFIG_QCOM_FALKOR_ERRATUM_1003 // reserved ASID
Wrong macro? That's not the ASID.
Thanks,
Mark.
Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Quoted 12 lines · Mark Rutland
Hi,
arch/arm64/Kconfig config CAVIUM_ERRATUM_27456 · line 497
Quoted 5 lines · Christopher Covington
arch/arm64/Kconfig +5
-0+config QCOM_FALKOR_E1003_RESERVED_ASID + int + default 1 + depends on QCOM_FALKOR_ERRATUM_1003 +I don't think this needs to be configurable, so let's drop this into a header, e.g. drop:
Quoted 4 lines
#define
FALKOR_RESERVED_ASID1... in <
asm/mmu_context.h>, protecting the rest with an ifndef__ASSEMBLY__guard.
Will do, thanks for the concrete suggestion.
Quoted 8 lines
[...]
arch/arm64/mm/proc.S ENDPROC(cpu_do_resume) · line 146
Quoted 4 lines
arch/arm64/mm/proc.S +4
-0+#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 + mrs x2, ttbr0_el1 // get cuurent TTBR0_EL1 + mov x3, #CONFIG_QCOM_FALKOR_ERRATUM_1003 // reserved ASIDWrong macro? That's not the ASID.
Oops, thanks for spotting.
Cov
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Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
In reply to Christopher CovingtonQuoted 7 lines · Christopher Covington
From: Shanker Donthineni <[email protected]>
On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may allocate TLB entries using an incorrect ASID when
TTBRx_EL1is being updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields separately using a reserved ASID will ensure that there are no TLB entries with incorrect ASID after changing the the ASID.
When we restore guest state in KVM, we completely save and restore TTBRx_EL1 from EL2. Would that be affected by this erratum?
Thanks,
-Christoffer
Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Hi Christoffer,
Quoted 11 lines · Christoffer Dall
Quoted 7 lines · Christopher Covington
From: Shanker Donthineni <[email protected]>
On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may allocate TLB entries using an incorrect ASID when
TTBRx_EL1is being updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields separately using a reserved ASID will ensure that there are no TLB entries with incorrect ASID after changing the the ASID.When we restore guest state in KVM, we completely save and restore
TTBRx_EL1from EL2. Would that be affected by this erratum?
Good question, but apparently not. I'll add the following explanation to the v3 commit message.
"EL2 and EL3 code changing the EL1&0 ASID is not subject to this erratum because hardware is prohibited from performing translations from an out-of-context translation regime."
Thanks,
Cov
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Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
PATCH v2 3/5 arm64: Create and use __tlbi_dsb() macros
In reply to Christopher CovingtonThis refactoring will allow an errata workaround that repeats tlbi dsb sequences to only change one location. This is not intended to change the generated assembly and comparing before and after preprocessor output of arch/arm64/mm/mmu.c and vmlinux objdump show no functional changes.
--- arch/arm64/include/asm/tlbflush.h | 104 +++++++++++++++++++++++++------------- 1 file changed, 69 insertions(+), 35 deletions(-)
arch/arm64/include/asm/tlbflush.h +69 -35
@@ -25,22 +25,69 @@#include <asm/cputype.h> /* -* Raw TLBI operations. +* Raw TLBI, DSB operations * -* Where necessary, use the __tlbi() macro to avoid asm() -* boilerplate. Drivers and most kernel code should use the TLB -* management routines in preference to the macro below. +* Where necessary, use __tlbi_*dsb() macros to avoid asm() boilerplate. +* Drivers and most kernel code should use the TLB management routines in +* preference to the macros below. * -* The macro can be used as __tlbi(op) or __tlbi(op, arg), depending -* on whether a particular TLBI operation takes an argument or -* not. The macros handles invoking the asm with or without the -* register argument as appropriate. +* The __tlbi_dsb() macro handles invoking the asm without any register +* argument, with a single register argument, and with start (included) +* and end (excluded) range of register arguments. For example: +* +* __tlbi_dsb(op, attr) +* +* tlbi op +* dsb attr +* +* __tlbi_dsb(op, attr, addr) +* +* mov %[addr], =addr +* tlbi op, %[addr] +* dsb attr +* +* __tlbi_range_dsb(op, attr, start, end) +* +* mov %[arg], =start +* mov %[end], =end +* for: +* tlbi op, %[addr] +* add %[addr], %[addr], #(1 << (PAGE_SHIFT - 12)) +* cmp %[addr], %[end] +* b.ne for +* dsb attr */ -#define __TLBI_0 (op, arg) asm ("tlbi " #op) -#define __TLBI_1 (op, arg) asm ("tlbi " #op ", %0" : : "r" (arg)) -#define __TLBI_N (op, arg, n, ...) __TLBI_##n(op, arg) -#define __tlbi (op, ...) __TLBI_N(op, ##__VA_ARGS__, 1, 0) +#define __TLBI_FOR_0 (ig0, ig1, ig2) +#define __TLBI_INSTR_0 (op, ig1, ig2) "tlbi " #op +#define __TLBI_IO_0 (ig0, ig1, ig2) : : + +#define __TLBI_FOR_1 (ig0, ig1, ig2) +#define __TLBI_INSTR_1 (op, ig0, ig1) "tlbi " #op ", %0" +#define __TLBI_IO_1 (ig0, arg, ig1) : : "r" (arg) + +#define __TLBI_FOR_2 (ig0, start, ig1) unsigned long addr; \ + for (addr = start; addr < end; \ + addr += 1 << (PAGE_SHIFT - 12)) +#define __TLBI_INSTR_2 (op, ig0, ig1) "tlbi " #op ", %0" +#define __TLBI_IO_2 (ig0, ig1, ig2) : : "r" (addr) + +#define __TLBI_FOR_N (op, a1, a2, n, ...) __TLBI_FOR_##n(op, a1, a2) +#define __TLBI_INSTR_N (op, a1, a2, n, ...) __TLBI_INSTR_##n(op, a1, a2) +#define __TLBI_IO_N (op, a1, a2, n, ...) __TLBI_IO_##n(op, a1, a2) + +#define __TLBI_FOR (op, ...) __TLBI_FOR_N(op, ##__VA_ARGS__, 2, 1, 0) +#define __TLBI_INSTR (op, ...) __TLBI_INSTR_N(op, ##__VA_ARGS__, 2, 1, 0) +#define __TLBI_IO (op, ...) __TLBI_IO_N(op, ##__VA_ARGS__, 2, 1, 0) + +#define __tlbi_asm_dsb (as, op, attr, ...) do { \ + __TLBI_FOR(op, ##__VA_ARGS__) \ + asm (__TLBI_INSTR(op, ##__VA_ARGS__) \ + __TLBI_IO(op, ##__VA_ARGS__)); \ + asm volatile ( as "\ndsb " #attr "\n" \ + : : : "memory"); } while (0) + +#define __tlbi_dsb (...) __tlbi_asm_dsb("", ##__VA_ARGS__)/* * TLB Management
@@ -84,16 +131,14 @@static inline void local_flush_tlb_all (void ) {dsb (nshst); -__tlbi (vmalle1); -dsb (nsh); +__tlbi_dsb (vmalle1, nsh);isb (); }static inline void flush_tlb_all (void ) {dsb (ishst); -__tlbi (vmalle1is); -dsb (ish); +__tlbi_dsb (vmalle1is, ish);isb (); }
@@ -102,8 +147,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)unsigned long asid =ASID (mm) <<48 ;dsb (ishst); -__tlbi (aside1is, asid); -dsb (ish); +__tlbi_dsb (aside1is, ish, asid); } static inline void flush_tlb_page(struct vm_area_struct *vma,
@@ -112,8 +156,7 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,unsigned long addr = uaddr >>12 | (ASID (vma->vm_mm) <<48 );dsb (ishst); -__tlbi (vale1is, addr); -dsb (ish); +__tlbi_dsb (vale1is, ish, addr); }/*
@@ -127,7 +170,6 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, bool last_level) {unsigned long asid =ASID (vma->vm_mm) <<48 ; -unsigned long addr;if ((end - start) >MAX_TLB_RANGE ) {flush_tlb_mm (vma->vm_mm);
@@ -138,13 +180,10 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, end = asid | (end >>12 );dsb (ishst); -for (addr = start; addr < end; addr +=1 << (PAGE_SHIFT -12 )) { -if (last_level) -__tlbi (vale1is, addr); -else -__tlbi (vae1is, addr); - } -dsb (ish); +if (last_level) +__tlbi_dsb (vale1is, ish, start, end); +else +__tlbi_dsb (vae1is, ish, start, end); } static inline void flush_tlb_range(struct vm_area_struct *vma,
@@ -155,8 +194,6 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,static inline void flush_tlb_kernel_range (unsigned long start,unsigned long end) { -unsigned long addr; -if ((end - start) >MAX_TLB_RANGE ) {flush_tlb_all ();return ;
@@ -166,9 +203,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end end >>=12 ;dsb (ishst); -for (addr = start; addr < end; addr +=1 << (PAGE_SHIFT -12 )) -__tlbi (vaae1is, addr); -dsb (ish); +__tlbi_dsb (vaae1is, ish, start, end);isb (); }
@@ -181,8 +216,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, {unsigned long addr = uaddr >>12 | (ASID (mm) <<48 ); -__tlbi (vae1is, addr); -dsb (ish); +__tlbi_dsb (vae1is, ish, addr); }#endif
Signature · 3 lines
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
PATCH v2 4/5 arm64: Use __tlbi_dsb() macros in KVM code
In reply to Christopher CovingtonRefactor the KVM code to use the newly introduced __tlbi_dsb macros, which will allow an errata workaround that repeats tlbi dsb sequences to only change one location. This is not intended to change the generated assembly and comparing before and after vmlinux objdump shows no functional changes.
--- arch/arm64/kvm/hyp/tlb.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-)
arch/arm64/kvm/hyp/tlb.c +6 -11
@@ -16,6 +16,7 @@*/ #include <asm/kvm_hyp.h> +#include <asm/tlbflush.h> void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) {
@@ -32,7 +33,7 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)* whole of Stage-1. Weep... */ ipa >>=12 ; - asmvolatile ("tlbi ipas2e1is, %0" : :"r" (ipa)); +__tlbi_dsb (ipas2e1is, ish, ipa);/* * We have to ensure completion of the invalidation at Stage-2,
@@ -40,9 +41,7 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)* complete (S1 + S2) walk based on the old Stage-2 mapping if * the Stage-1 invalidation happened first. */ -dsb (ish); - asmvolatile ("tlbi vmalle1is" : : ); -dsb (ish); +__tlbi_dsb (vmalle1is, ish);isb ();write_sysreg (0 , vttbr_el2);
@@ -57,8 +56,7 @@ void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)write_sysreg (kvm->arch.vttbr, vttbr_el2);isb (); - asmvolatile ("tlbi vmalls12e1is" : : ); -dsb (ish); +__tlbi_dsb (vmalls12e1is, ish);isb ();write_sysreg (0 , vttbr_el2);
@@ -72,8 +70,7 @@ void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu)write_sysreg (kvm->arch.vttbr, vttbr_el2);isb (); - asmvolatile ("tlbi vmalle1" : : ); -dsb (nsh); +__tlbi_dsb (vmalle1, nsh);isb ();write_sysreg (0 , vttbr_el2);
@@ -82,7 +79,5 @@ void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu) void __hyp_text __kvm_flush_vm_context(void) {dsb (ishst); - asmvolatile ("tlbi alle1is \n" -"ic ialluis " : : ); -dsb (ish); +__tlbi_asm_dsb ("ic ialluis" , alle1is, ish); }
Signature · 3 lines
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Mark Rutland
reviewerRe: [PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code
arch/arm64/kvm/hyp/tlb.c void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) · line 43
Quoted 10 lines · Christopher Covington
Refactor the KVM code to use the newly introduced
__tlbi_dsbmacros, which will allow an errata workaround that repeats tlbi dsb sequences to only change one location. This is not intended to change the generated assembly and comparing before and after vmlinux objdump shows no functional changes.arch/arm64/kvm/hyp/tlb.c +0
-1@@ -40,9 +41,7 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)* complete (S1 + S2) walk based on the old Stage-2 mapping if * the Stage-1 invalidation happened first. */ -dsb (ish);
Looks like this got accidentally removed. AFAICT it is still necessary.
arch/arm64/kvm/hyp/tlb.c void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) · line 45
Quoted 4 lines
arch/arm64/kvm/hyp/tlb.c +1
-2- asmvolatile ("tlbi vmalle1is" : : ); -dsb (ish); +__tlbi_dsb (vmalle1is, ish);isb ();
Thanks,
Mark.
Re: [PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code
Quoted 5 lines · Mark Rutland
Quoted 4 lines · Christopher Covington
Refactor the KVM code to use the newly introduced
__tlbi_dsbmacros, which will allow an errata workaround that repeats tlbi dsb sequences to only change one location. This is not intended to change the generated assembly and comparing before and after vmlinux objdump shows no functional changes.
@@ -32,7 +33,7 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
* whole of Stage-1. Weep...
*/
ipa >>= 12;
- asm volatile("tlbi ipas2e1is, %0" : : "r" (ipa));
+ __tlbi_dsb(ipas2e1is, ish, ipa);
/*
* We have to ensure completion of the invalidation at Stage-2,
Quoted 7 lines
arch/arm64/kvm/hyp/tlb.c void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) · line 43
Quoted 5 lines
arch/arm64/kvm/hyp/tlb.c +0
-1@@ -40,9 +41,7 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)* complete (S1 + S2) walk based on the old Stage-2 mapping if * the Stage-1 invalidation happened first. */ -dsb (ish);Looks like this got accidentally removed. AFAICT it is still necessary.
Not removed, just hoisted above the comment block to the previous patch hunk.
Quoted 4 lines
arch/arm64/kvm/hyp/tlb.c void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) · line 45
Quoted 4 lines
arch/arm64/kvm/hyp/tlb.c +1
-2- asmvolatile ("tlbi vmalle1is" : : ); -dsb (ish); +__tlbi_dsb (vmalle1is, ish);isb ();
Thanks,
Cov
Signature · 3 lines
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Mark Rutland
reviewerRe: [PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code
Quoted 25 lines · Christopher Covington
Quoted 5 lines · Mark Rutland
Quoted 4 lines · Christopher Covington
Refactor the KVM code to use the newly introduced
__tlbi_dsbmacros, which will allow an errata workaround that repeats tlbi dsb sequences to only change one location. This is not intended to change the generated assembly and comparing before and after vmlinux objdump shows no functional changes.arch/arm64/kvm/hyp/tlb.c +1
-1@@ -32,7 +33,7 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)* whole of Stage-1. Weep... */ ipa >>=12 ; - asmvolatile ("tlbi ipas2e1is, %0" : :"r" (ipa)); +__tlbi_dsb (ipas2e1is, ish, ipa);/* * We have to ensure completion of the invalidation at Stage-2, Quoted 8 lines
arch/arm64/kvm/hyp/tlb.c void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) · line 43
Quoted 6 lines
arch/arm64/kvm/hyp/tlb.c +0
-1@@ -40,9 +41,7 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)* complete (S1 + S2) walk based on the old Stage-2 mapping if * the Stage-1 invalidation happened first. */ -dsb (ish);Looks like this got accidentally removed. AFAICT it is still necessary.
Quoted 1 line
Not removed, just hoisted above the comment block to the previous patch hunk.
Ah, sorry. I hadn't spotted that it got folded into the __tlbi_dsb() above.
Given the comment was previously attached to the DSB, it might make more sense to fold it into the prior comment block, so that it remains attached to the __tlbi_dsb(), which guarantees the completion that the comment describes.
Thanks,
Mark.
PATCH v2 5/5 arm64: Work around Falkor erratum 1009
In reply to Christopher CovingtonDuring a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed; instruction fetches are not subject to the conditions of this erratum.
Change-Id: I25e86b068addd68cdfba5a11142b9fc37312b1ee
--- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 10 ++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/tlbflush.h | 5 ++++- arch/arm64/kernel/cpu_errata.c | 7 +++++++ 5 files changed, 24 insertions(+), 2 deletions(-)
Documentation/arm64/silicon-errata.txt +1 -0
@@ -64,3 +64,4 @@ stable kernels. | | | | | | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | | Qualcomm | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | +| Qualcomm | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
arch/arm64/Kconfig +10 -0
@@ -495,6 +495,16 @@ config QCOM_FALKOR_E1003_RESERVED_ASID default 1 depends on QCOM_FALKOR_ERRATUM_1003 +config QCOM_FALKOR_ERRATUM_1009 + bool "Falkor E1009: Prematurely complete a DSB after a TLBI" + default y + help + Falkor CPU may prematurely complete a DSB following a TLBI xxIS + invalidate maintenance operations. Repeat the TLBI operation one + more time to fix the issue. + + If unsure, say Y. + endmenu
arch/arm64/include/asm/cpucaps.h +2 -1
@@ -36,7 +36,8 @@#define ARM64_MISMATCHED_CACHE_LINE_SIZE 15#define ARM64_HAS_NO_FPSIMD 16#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 17 +#define ARM64_WORKAROUND_REPEAT_TLBI 18 -#define ARM64_NCAPS 18 +#define ARM64_NCAPS 19#endif /* __ASM_CPUCAPS_H */
arch/arm64/include/asm/tlbflush.h +4 -1
@@ -85,7 +85,10 @@ asm (__TLBI_INSTR(op, ##__VA_ARGS__) \ __TLBI_IO(op, ##__VA_ARGS__)); \ asm volatile ( as "\ndsb " #attr "\n" \ - : : : "memory"); } while (0) + ALTERNATIVE("nop" "\nnop" "\n", \ + __TLBI_INSTR(op, ##__VA_ARGS__) "\ndsb " #attr "\n", \ + ARM64_WORKAROUND_REPEAT_TLBI) \ + __TLBI_IO(op, ##__VA_ARGS__) : "memory"); } while (0)#define __tlbi_dsb (...) __tlbi_asm_dsb("", ##__VA_ARGS__)
arch/arm64/kernel/cpu_errata.c +7 -0
@@ -137,6 +137,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0x00, 0x00), },#endif +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 + { + .desc = "Qualcomm Falkor erratum 1009", + .capability = ARM64_WORKAROUND_REPEAT_TLBI, + MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0x00, 0x00), + }, +#endif { } };
Signature · 3 lines
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.