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arm64: Add DTS support for FSL's LS1012A SoC

PATCH Superseded Harninder Rai 2 participants 2 messages Dec 6, 2016 – Dec 30, 2016

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Device tree bindings Arm i.MX and Layerscape

v3 of 4 Superseded Latest is v4 →

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Harninder Rai

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PATCH v3 1/1 arm64: Add DTS support for FSL's LS1012A SoC

LS1012A features an advanced 64-bit ARM v8 CortexA53 processor with 32 KB of parity protected L1-I cache, 32 KB of ECC protected L1-D cache, as well as 256 KB of ECC protected L2 cache.

Features summary
One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
- Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC protection
- Speed up to 800 MHz
- Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
- Neon SIMD engine
- ARM v8 cryptography extensions
One 16-bit DDR3L SDRAM memory controller
ARM core-link CCI-400 cache coherent interconnect
Cryptography acceleration (SEC)
One Configurable x3 SerDes
One PCI Express Gen2 controller, supporting x1 operation
One serial ATA (SATA Gen 3.0) controller
One USB 3.0/2.0 controller with integrated PHY

Following levels of DTSI/DTS files have been created for the LS1012A
SoC family:

- fsl-ls1012a.dtsi:
DTS-Include file for FSL LS1012A SoC.

- fsl-ls1012a-frdm.dts:
DTS file for FSL LS1012A FRDM board.

- fsl-ls1012a-qds.dts:
DTS file for FSL LS1012A QDS board.

- fsl-ls1012a-rdb.dts:
DTS file for FSL LS1012A RDB board.

Signed-off-by Harninder Rai <[email protected]>
Signed-off-by Bhaskar Upadhaya <[email protected]>

---
Changes in v3: Incorporated Shawn's comments
- Change PPI interrupts to IRQ_TYPE_LEVEL_LOW and
- SPI interrupts to IRQ_TYPE_LEVEL_HIGH

Changes in v2: Incorporated Shawn's comments
- Brief introduction of the SoC in commit message
- Alphabetic ordering of labeled nodes
- Better naming to be used for regulator node
- Make timer node's comments more readable
- Sort nodes with unit-address in order of the address

 arch/arm64/boot/dts/freescale/Makefile             |   3 +
 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 115 ++++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  | 128 +++++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts  |  59 +++++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi     | 245 +++++++++++++++++++++
 5 files changed, 550 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
arch/arm64/boot/dts/freescale/Makefile +3 -0
index 6602718..39db645 100644
@@ -1,3 +1,6 @@
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts new file +115 -0

115 lines not on this page · raw message

arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts new file +128 -0

128 lines not on this page · raw message

arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts new file +59 -0

59 lines not on this page · raw message

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi new file +245 -0

245 lines not on this page · raw message

Signature · 1 line
1.9.1
#1 lore raw

PATCH v3 1/1 arm64: Add DTS support for FSL's LS1012A SoC

Quoted 29 lines · Harninder Rai

LS1012A features an advanced 64-bit ARM v8 CortexA53 processor with 32 KB of parity protected L1-I cache, 32 KB of ECC protected L1-D cache, as well as 256 KB of ECC protected L2 cache.

Features summary
One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
- Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC protection
- Speed up to 800 MHz
- Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
- Neon SIMD engine
- ARM v8 cryptography extensions
One 16-bit DDR3L SDRAM memory controller
ARM core-link CCI-400 cache coherent interconnect
Cryptography acceleration (SEC)
One Configurable x3 SerDes
One PCI Express Gen2 controller, supporting x1 operation
One serial ATA (SATA Gen 3.0) controller
One USB 3.0/2.0 controller with integrated PHY

Following levels of DTSI/DTS files have been created for the LS1012A
SoC family:

- fsl-ls1012a.dtsi:
DTS-Include file for FSL LS1012A SoC.

- fsl-ls1012a-frdm.dts:
DTS file for FSL LS1012A FRDM board.

Quoted 8 lines

- fsl-ls1012a-qds.dts:
DTS file for FSL LS1012A QDS board.

- fsl-ls1012a-rdb.dts:
DTS file for FSL LS1012A RDB board.

Signed-off-by Harninder Rai <[email protected]>
Signed-off-by Bhaskar Upadhaya <[email protected]>

It looks good now, except a few minor things below.

<snip>

arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts line 58

Quoted 11 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts new file +11 -0
+/ {
+	model = "LS1012A Freedom Board";
+	compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
+	sys_mclk: clock-mclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	regulator_1p8v: regulator {

The node name is too generic. We generally suggest the following naming scheme for fixed regulator.

	reg_xxx: regulator-xxx {
		...
	};
Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts new file +6 -0
+		compatible = "regulator-fixed";
+		regulator-name = "1P8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};

<snip>

arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts line 58

Quoted 12 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts new file +12 -0
+
+/ {
+	model = "LS1012A QDS Board";
+	compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+
+	sys_mclk: clock-mclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24576000>;
+	};
+
+	regulator_3p3v: regulator {

Ditto

Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts new file +6 -0
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};

<snip>

Quoted 19 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi new file +19 -0
+/ {
+	compatible = "fsl,ls1012a";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			clocks = <&clockgen 1 0>;
+			#cooling-cells = <2>;
+		};
+	};
+

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi line 75

Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi new file +10 -0
+	sysclk: sysclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "sysclk";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+

This newline is unnecessary.

Quoted 5 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi new file +5 -0
+		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
+			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
+			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
+			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
+	};

<snip>

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi line 156

Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi new file +6 -0
+		duart0: serial at 21c0500 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x00 0x21c0500 0x0 0x100>;
+			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen 4 0>;
+		};

status = "disabled";

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi line 163

Quoted 7 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi new file +7 -0
+
+		duart1: serial at 21c0600 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x00 0x21c0600 0x0 0x100>;
+			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen 4 0>;
+		};

Ditto

<snip>

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi line 242

Quoted 5 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi new file +5 -0
+		sata: sata at 3200000 {
+			compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
+			reg = <0x0 0x3200000 0x0 0x10000>;
+			interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clockgen 4 0>;

Ditto

Shawn

Quoted 11 lines
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts new file +3 -0
+		};
+	};
+};
Signature · 7 lines
1.9.1


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