nvmem: imx-ocotp: Add support for i.MX6UL

PATCH New Daniel Schultz 4 participants 6 messages Dec 2, 2016 – Jan 4, 2017

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Device tree bindings Arm i.MX and Layerscape NVMEM framework

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Daniel Schultz

author

2016-12-02 14:45 UTC #0 lore raw

PATCH 1/3 nvmem: imx-ocotp: Add support for i.MX6UL

This patch adds OCOTP support for the i.MX6UL SoC.

Signed-off-by Daniel Schultz <[email protected]>

---
 Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 5 +++--
 drivers/nvmem/imx-ocotp.c                             | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt +3 -2

index 383d588..fcb1a48 100644
@@ -1,13 +1,14 @@
 Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
 
 This binding represents the on-chip eFuse OTP controller found on
-i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
 
 Required properties:
 - compatible: should be one of
 	"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
 	"fsl,imx6sl-ocotp" (i.MX6SL), or
-	"fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
+	"fsl,imx6sx-ocotp" (i.MX6SX), or
+	"fsl,imx6ul-ocotp" (i.MX6UL), followed by "syscon".
 - reg: Should contain the register base and length.
 - clocks: Should contain a phandle pointing to the gated peripheral clock.

drivers/nvmem/imx-ocotp.c +1 -0

index ac27b9b..d2f78d3 100644
@@ -71,6 +71,7 @@ static int imx_ocotp_read(void *context, unsigned int offset,
 
 static const struct of_device_id imx_ocotp_dt_ids[] = {
 	{ .compatible = "fsl,imx6q-ocotp",  (void *)128 },
+	{ .compatible = "fsl,imx6ul-ocotp", (void *)128 },
 	{ .compatible = "fsl,imx6sl-ocotp", (void *)32 },
 	{ .compatible = "fsl,imx6sx-ocotp", (void *)128 },
 	{ },

Signature · 1 line

1.9.1

Daniel Schultz

author

2016-12-02 14:45 UTC #1 lore raw

PATCH 2/3 ARM: dts: imx6ul: Add OCOTP node

This device node adds OCOTP for the i.MX6UL SoC.

Signed-off-by Daniel Schultz <[email protected]>

---
 arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/boot/dts/imx6ul.dtsi +6 -0

index c5c05fd..ee53795 100644
@@ -849,6 +849,12 @@
 				reg = <0x021b0000 0x4000>;
 			};
 
+			ocotp: ocotp at 021bc000 {
+				compatible = "fsl,imx6ul-ocotp";
+				reg = <0x021bc000 0x4000>;
+				clocks = <&clks IMX6UL_CLK_OCOTP>;
+			};
+
 			lcdif: lcdif at 021c8000 {
 				compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 				reg = <0x021c8000 0x4000>;

Signature · 1 line

1.9.1

Shawn Guo

2016-12-30 13:01 UTC #2 lore raw

PATCH 2/3 ARM: dts: imx6ul: Add OCOTP node

Quoted 3 lines · Daniel Schultz

This device node adds OCOTP for the i.MX6UL SoC.
Signed-off-by Daniel Schultz <[email protected]>

Bai Ping (Cc'ed here) from NXP is sending similar patches [1]. DTS change looks good to me, but I will not apply it until the driver and bindings get accepted.

Shawn

[1] https://www.spinics.net/lists/arm-kernel/msg540900.html

Quoted 29 lines

---
 arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/boot/dts/imx6ul.dtsi +6 -0

index c5c05fd..ee53795 100644
@@ -849,6 +849,12 @@
 				reg = <0x021b0000 0x4000>;
 			};
 
+			ocotp: ocotp at 021bc000 {
+				compatible = "fsl,imx6ul-ocotp";
+				reg = <0x021bc000 0x4000>;
+				clocks = <&clks IMX6UL_CLK_OCOTP>;
+			};
+
 			lcdif: lcdif at 021c8000 {
 				compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 				reg = <0x021c8000 0x4000>;

Signature · 7 lines

1.9.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Daniel Schultz

author

2016-12-02 14:45 UTC #3 lore raw

PATCH 3/3 nvmem: imx-ocotp: Fix wrong register size

In reply to Daniel Schultz

All i.MX6 SoCs have an OCOTP Controller with 4kbit fuses. The i.MX6SL is an exception and has only 2kbit fuses.

In the TRM for the i.MX6DQ (IMX6QDRM - Rev 2, 06/2014) the fuses size is described in chapter 46.1.1 with:
"32-bit word restricted program and read to 4Kbits of eFuse OTP(512x8)."

In the TRM for the i.MX6SL (IMX6SLRM - Rev 2, 06/2015) the fuses size is described in chapter 34.1.1 with:
"32-bit word restricted program and read to 2 kbit of eFuse OTP(128x8)."

Since the Freescale Linux kernel OCOTP driver works with a fuses size of 2 kbit for the i.MX6SL, it looks like the TRM is wrong and the formula to calculate the correct fuses size has to be 256x8.

Signed-off-by Daniel Schultz <[email protected]>

---
 drivers/nvmem/imx-ocotp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/nvmem/imx-ocotp.c +1 -1

index d2f78d3..8482c53 100644
@@ -72,7 +72,7 @@ static int imx_ocotp_read(void *context, unsigned int offset,
 static const struct of_device_id imx_ocotp_dt_ids[] = {
 	{ .compatible = "fsl,imx6q-ocotp",  (void *)128 },
 	{ .compatible = "fsl,imx6ul-ocotp", (void *)128 },
-	{ .compatible = "fsl,imx6sl-ocotp", (void *)32 },
+	{ .compatible = "fsl,imx6sl-ocotp", (void *)64 },
 	{ .compatible = "fsl,imx6sx-ocotp", (void *)128 },
 	{ },
 };

Signature · 1 line

1.9.1

Rob Herring

maintainer

2016-12-09 21:02 UTC #4 lore raw

PATCH 1/3 nvmem: imx-ocotp: Add support for i.MX6UL

In reply to Daniel Schultz

Quoted 7 lines · Daniel Schultz

This patch adds OCOTP support for the i.MX6UL SoC.
Signed-off-by Daniel Schultz <[email protected]>
---
 Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 5 +++--
 drivers/nvmem/imx-ocotp.c                             | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

Acked-by Rob Herring <[email protected]>

Srinivas Kandagatla

2017-01-04 14:14 UTC #5 lore raw

PATCH 1/3 nvmem: imx-ocotp: Add support for i.MX6UL

In reply to Daniel Schultz

Quoted 3 lines · Daniel Schultz

This patch adds OCOTP support for the i.MX6UL SoC.
Signed-off-by Daniel Schultz <[email protected]>

As Shawn said, there is already a similar patch in the mailing list
http://www.spinics.net/lists/arm-kernel/msg543203.html
http://www.spinics.net/lists/arm-kernel/msg543204.html

I will pick that patch + I will queue up fix from you "[PATCH 3/3]
nvmem: imx-ocotp: Fix wrong register size"

thanks,
srini

Quoted 39 lines

---
 Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 5 +++--
 drivers/nvmem/imx-ocotp.c                             | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt +3 -2

index 383d588..fcb1a48 100644
@@ -1,13 +1,14 @@
 Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
 
 This binding represents the on-chip eFuse OTP controller found on
-i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
 
 Required properties:
 - compatible: should be one of
 	"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
 	"fsl,imx6sl-ocotp" (i.MX6SL), or
-	"fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
+	"fsl,imx6sx-ocotp" (i.MX6SX), or
+	"fsl,imx6ul-ocotp" (i.MX6UL), followed by "syscon".
 - reg: Should contain the register base and length.
 - clocks: Should contain a phandle pointing to the gated peripheral clock.

drivers/nvmem/imx-ocotp.c +1 -0

index ac27b9b..d2f78d3 100644
@@ -71,6 +71,7 @@ static int imx_ocotp_read(void *context, unsigned int offset,
 
 static const struct of_device_id imx_ocotp_dt_ids[] = {
 	{ .compatible = "fsl,imx6q-ocotp",  (void *)128 },
+	{ .compatible = "fsl,imx6ul-ocotp", (void *)128 },
 	{ .compatible = "fsl,imx6sl-ocotp", (void *)32 },
 	{ .compatible = "fsl,imx6sx-ocotp", (void *)128 },
 	{ },