MIPS: Loongson: Merge load addresses

PATCH New 谢致邦 (XIE Zhibang) 1 participant 1 message Jan 4, 2017

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MIPS MIPS/LOONGSON1 architecture

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谢致邦 (XIE Zhibang)

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2017-01-04 13:31 UTC #0 lore raw

PATCH 1/1 MIPS: Loongson: Merge load addresses

Loongson 1 is a 32-bit MIPS CPU family with PRID 0x4220.

Signed-off-by 谢致邦 (XIE Zhibang) <[email protected]>

---
 arch/mips/loongson32/Platform | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

arch/mips/loongson32/Platform +1 -2

index ffe01c6d..29795d56 100644
@@ -4,5 +4,4 @@ cflags-$(CONFIG_CPU_LOONGSON1)	+= \
 
 platform-$(CONFIG_MACH_LOONGSON32)	+= loongson32/
 cflags-$(CONFIG_MACH_LOONGSON32)	+= -I$(srctree)/arch/mips/include/asm/mach-loongson32
-load-$(CONFIG_LOONGSON1_LS1B)		+= 0xffffffff80100000
-load-$(CONFIG_LOONGSON1_LS1C)		+= 0xffffffff80100000
+load-$(CONFIG_CPU_LOONGSON1)		+= 0xffffffff80100000

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