usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)
Subsystems (4)
PATCH v2 1/3 usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)
This patch introduces a new parameter to activate USB OTG HS/FS core embedded phy transciver. The STM32F4x9 SoC uses the GGPIO register to enable the transciver.
--- drivers/usb/dwc2/core.h | 4 ++++ drivers/usb/dwc2/hcd.c | 21 ++++++++++++++----- drivers/usb/dwc2/hw.h | 2 ++ drivers/usb/dwc2/params.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+), 5 deletions(-)
drivers/usb/dwc2/core.h +4 -0
@@ -430,6 +430,9 @@ enum dwc2_ep0_state {* needed. * 0 - No (default) * 1 - Yes +* @activate_transceiver: Activate internal transceiver using GGPIO register. +* 0 - Deactivate the transceiver (default) +* 1 - Activate the transceiver * @g_dma: Enables gadget dma usage (default: autodetect). * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). * @g_rx_fifo_size: The periodic rx fifo size for the device, in
@@ -501,6 +504,7 @@ struct dwc2_core_params {int uframe_sched;int external_id_pin_ctl;int hibernation; +int activate_transceiver;/* * The following parameters are *only* set via device
drivers/usb/dwc2/hcd.c +16 -5
@@ -118,7 +118,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)static int dwc2_fs_phy_init (struct dwc2_hsotg *hsotg,bool select_phy) { -u32 usbcfg, i2cctl; +u32 usbcfg, ggpio, i2cctl;int retval =0 ;/*
@@ -142,6 +142,17 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)return retval; } } + + ggpio =dwc2_readl (hsotg->regs +GGPIO ); +if (!(ggpio &GGPIO_STM32_OTG_GCCFG_PWRDWN ) && + (hsotg->params.activate_transceiver >0 )) { +dev_dbg (hsotg->dev,"Activating transceiver\n" ); +/* STM32F4xx uses the GGPIO register as general core +* configuration register. +*/ + ggpio |=GGPIO_STM32_OTG_GCCFG_PWRDWN ; +dwc2_writel (ggpio, hsotg->regs +GGPIO ); + } }/*
@@ -941,7 +952,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)* * In slave mode, checks for a free request queue entry, then sets the Channel * Enable and Channel Disable bits of the Host Channel Characteristics -* register of the specified channel to intiate the halt. If there is no free +* register of the specified channel to initiate the halt. If there is no free * request queue entry, sets only the Channel Disable bit of the HCCHARn * register to flush requests for this channel. In the latter case, sets a * flag to indicate that the host channel needs to be halted when a request
@@ -2359,9 +2370,9 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)dwc2_flush_rx_fifo (hsotg);/* Clear Host Set HNP Enable in the OTG Control Register */ - otgctl =dwc2_readl (hsotg->regs +GOTGCTL ); - otgctl &= ~GOTGCTL_HSTSETHNPEN ; -dwc2_writel (otgctl, hsotg->regs +GOTGCTL ); +//otgctl = dwc2_readl(hsotg->regs + GOTGCTL); +//otgctl &= ~GOTGCTL_HSTSETHNPEN; +//dwc2_writel(otgctl, hsotg->regs + GOTGCTL); if (hsotg->params.dma_desc_enable <=0 ) {int num_channels, i;
drivers/usb/dwc2/hw.h +2 -0
@@ -225,6 +225,8 @@#define GPVNDCTL HSOTG_REG(0x0034)#define GGPIO HSOTG_REG(0x0038) +#define GGPIO_STM32_OTG_GCCFG_PWRDWN (1 << 16) +#define GUID HSOTG_REG(0x003c)#define GSNPSID HSOTG_REG(0x0040)#define GHWCFG1 HSOTG_REG(0x0044)
drivers/usb/dwc2/params.c +51 -0
75 lines not on this page · raw message
Signature · 1 line
2.10.1 (Apple Git-78)
PATCH v2 2/3 ARM: dts: STM32 Add USB FS host mode support
This patch adds the USB pins and nodes for USB HS/FS cores working at FS speed, using embedded PHY.
--- arch/arm/boot/dts/stm32f429-disco.dts | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32f429.dtsi | 35 ++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/stm32f469-disco.dts | 30 ++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 1 deletion(-)
arch/arm/boot/dts/stm32f429-disco.dts +30 -0
@@ -88,6 +88,16 @@ gpios = <&gpioa 0 0>; }; }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpioc 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &clk_hse {
@@ -99,3 +109,23 @@ pinctrl-names = "default"; status = "okay"; }; + +&usbotg_hs { + compatible = "st,stm32-fsotg", "snps,dwc2"; + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + usb-host { + usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PC4_FUNC_GPIO>; + bias-disable; + drive-push-pull; + }; + }; + }; +};
arch/arm/boot/dts/stm32f429.dtsi +34 -1
@@ -206,7 +206,7 @@ reg = <0x40007000 0x400>; }; - pin-controller { + pinctrl: pin-controller { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f429-pinctrl";
@@ -316,6 +316,30 @@ }; }; + usbotg_fs_pins_a: usbotg_fs at 0 { + pins { + pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>, + <STM32F429_PA11_FUNC_OTG_FS_DM>, + <STM32F429_PA12_FUNC_OTG_FS_DP>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_b: usbotg_fs at 1 { + pins { + pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>, + <STM32F429_PB14_FUNC_OTG_HS_DM>, + <STM32F429_PB15_FUNC_OTG_HS_DP>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + + usbotg_hs_pins_a: usbotg_hs at 0 { pins { pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
@@ -420,6 +444,15 @@ status = "disabled"; }; + usbotg_fs: usb at 50000000 { + compatible = "st,stm32f4xx-fsotg", "snps,dwc2"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 39>; + clock-names = "otg"; + status = "disabled"; + }; + rng: rng at 50060800 { compatible = "st,stm32-rng"; reg = <0x50060800 0x400>;
arch/arm/boot/dts/stm32f469-disco.dts +30 -0
@@ -68,6 +68,17 @@ soc { dma-ranges = <0xc0000000 0x0 0x10000000>; }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpiob 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &rcc {
@@ -81,3 +92,22 @@ &usart3 { status = "okay"; }; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + usb-host { + usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PB2_FUNC_GPIO>; + bias-disable; + drive-push-pull; + }; + }; + }; +};
Signature · 1 line
2.10.1 (Apple Git-78)
Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support
Hi Bruno,
Quoted 4 lines · Bruno Herrera
This patch adds the USB pins and nodes for USB HS/FS cores working at FS speed, using embedded PHY.
Signed-off-by Bruno Herrera <[email protected]>
Sorry, but what is patch 1 & pacth 3 status ?
For this one, can split it in 3 patches (one patch for SOC and one for each board) please.
Quoted 41 lines
--- arch/arm/boot/dts/stm32f429-disco.dts | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32f429.dtsi | 35 ++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/stm32f469-disco.dts | 30 ++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 1 deletion(-)arch/arm/boot/dts/stm32f429-disco.dts +20
-0@@ -88,6 +88,16 @@ gpios = <&gpioa 0 0>; }; }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpioc 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &clk_hse {@@ -99,3 +109,23 @@ pinctrl-names = "default"; status = "okay"; }; + +&usbotg_hs { + compatible = "st,stm32-fsotg", "snps,dwc2"; + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl {
arch/arm/boot/dts/stm32f429-disco.dts line 131
Quoted 10 lines
arch/arm/boot/dts/stm32f429-disco.dts +10
-0+ usb-host { + usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PC4_FUNC_GPIO>; + bias-disable; + drive-push-pull; + }; + }; + }; +};
Pinctrl muxing has to be defined/declared in stm32f429.dtsi
Quoted 95 lines
arch/arm/boot/dts/stm32f429.dtsi +34
-1@@ -206,7 +206,7 @@ reg = <0x40007000 0x400>; }; - pin-controller { + pinctrl: pin-controller { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f429-pinctrl";@@ -316,6 +316,30 @@ }; }; + usbotg_fs_pins_a: usbotg_fs at 0 { + pins { + pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>, + <STM32F429_PA11_FUNC_OTG_FS_DM>, + <STM32F429_PA12_FUNC_OTG_FS_DP>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_b: usbotg_fs at 1 { + pins { + pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>, + <STM32F429_PB14_FUNC_OTG_HS_DM>, + <STM32F429_PB15_FUNC_OTG_HS_DP>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + + usbotg_hs_pins_a: usbotg_hs at 0 { pins { pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,@@ -420,6 +444,15 @@ status = "disabled"; }; + usbotg_fs: usb at 50000000 { + compatible = "st,stm32f4xx-fsotg", "snps,dwc2"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 39>; + clock-names = "otg"; + status = "disabled"; + }; + rng: rng at 50060800 { compatible = "st,stm32-rng"; reg = <0x50060800 0x400>;arch/arm/boot/dts/stm32f469-disco.dts +20
-0@@ -68,6 +68,17 @@ soc { dma-ranges = <0xc0000000 0x0 0x10000000>; }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpiob 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &rcc {@@ -81,3 +92,22 @@ &usart3 { status = "okay"; }; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl {
arch/arm/boot/dts/stm32f469-disco.dts line 113
Quoted 10 lines
arch/arm/boot/dts/stm32f469-disco.dts +10
-0+ usb-host { + usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PB2_FUNC_GPIO>; + bias-disable; + drive-push-pull; + }; + }; + }; +};
Same. Note that if you have 2 configuration for one feature (like it is here for "usbotg_pwren_h"), you could index it. Not that I'm adding a dedidacted pinctroller for stm32f469.
Br
Alex
Quoted 1 line
Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support
Hi Alex,
Quoted 4 lines · Alexandre Torgue
Hi Bruno,
Quoted 1 line · Bruno Herrera
Quoted 8 lines
Quoted 5 lines
This patch adds the USB pins and nodes for USB HS/FS cores working at FS speed,
using embedded PHY.Signed-off-by Bruno Herrera <[email protected]>Sorry, but what is patch 1 & pacth 3 status ?
My bad, I'll add the status of the patch series version 3.
Quoted 4 lines
For this one, can split it in 3 patches (one patch for SOC and one for each board) please.
No problem.
Quoted 50 lines
Quoted 50 lines
--- arch/arm/boot/dts/stm32f429-disco.dts | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32f429.dtsi | 35 ++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/stm32f469-disco.dts | 30 ++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 1 deletion(-)arch/arm/boot/dts/stm32f429-disco.dts +25
-0@@ -88,6 +88,16 @@ gpios = <&gpioa 0 0>; }; }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpioc 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &clk_hse {@@ -99,3 +109,23 @@ pinctrl-names = "default"; status = "okay"; }; + +&usbotg_hs { + compatible = "st,stm32-fsotg", "snps,dwc2"; + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + usb-host { + usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PC4_FUNC_GPIO>; + bias-disable;
Quoted 9 lines
arch/arm/boot/dts/stm32f429-disco.dts line 131
Quoted 5 lines
arch/arm/boot/dts/stm32f429-disco.dts +5
-0+ drive-push-pull; + }; + }; + }; +};Pinctrl muxing has to be defined/declared in
stm32f429.dtsi
This is board specific logic and it vary from board to board, should it be defined here?
Quoted 112 lines
Quoted 112 lines
arch/arm/boot/dts/stm32f429.dtsi +15
-1@@ -206,7 +206,7 @@ reg = <0x40007000 0x400>; }; - pin-controller { + pinctrl: pin-controller { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f429-pinctrl";@@ -316,6 +316,30 @@ }; }; + usbotg_fs_pins_a: usbotg_fs at 0 { + pins { + pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>, + <STM32F429_PA11_FUNC_OTG_FS_DM>, + <STM32F429_PA12_FUNC_OTG_FS_DP>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_b: usbotg_fs at 1 { + pins { + pinmux =<
STM32F429_PB12_FUNC_OTG_HS_ID>,
+
<STM32F429_PB14_FUNC_OTG_HS_DM>,
+
<STM32F429_PB15_FUNC_OTG_HS_DP>;arch/arm/boot/dts/stm32f429.dtsi +8
-0+ bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + + usbotg_hs_pins_a: usbotg_hs at 0 { pins { pinmux =<
STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,arch/arm/boot/dts/stm32f429.dtsi +9
-0@@ -420,6 +444,15 @@ status = "disabled"; }; + usbotg_fs: usb at 50000000 { + compatible = "st,stm32f4xx-fsotg", "snps,dwc2"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 39>; + clock-names = "otg"; + status = "disabled"; + }; + rng: rng at 50060800 { compatible = "st,stm32-rng"; reg = <0x50060800 0x400>;arch/arm/boot/dts/stm32f469-disco.dts +26
-0@@ -68,6 +68,17 @@ soc { dma-ranges = <0xc0000000 0x0 0x10000000>; }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpiob 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &rcc {@@ -81,3 +92,22 @@ &usart3 { status = "okay"; }; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + usb-host { + usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PB2_FUNC_GPIO>; + bias-disable; + drive-push-pull;
Quoted 9 lines
arch/arm/boot/dts/stm32f469-disco.dts line 113
Quoted 4 lines
arch/arm/boot/dts/stm32f469-disco.dts +4
-0+ }; + }; + }; +};Same. Note that if you have 2 configuration for one feature (like it is here for "
usbotg_pwren_h"), you could index it. Not that I'm adding a dedidacted pinctroller for stm32f469.
Sorry, but I dont know what you mean by index here.
The usbotg_pwren_h (VBUS ENABLE) is attached in different port/pins for each board.
Br.,
Quoted 6 lines
Br
AlexQuoted 2 lines
Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support
Quoted 83 lines · Bruno Herrera
Hi Alex,
Quoted 4 lines · Alexandre Torgue
Hi Bruno,
Quoted 1 line · Bruno Herrera
Quoted 8 lines
Quoted 5 lines
This patch adds the USB pins and nodes for USB HS/FS cores working at FS speed,
using embedded PHY.Signed-off-by Bruno Herrera <[email protected]>Sorry, but what is patch 1 & pacth 3 status ?
My bad, I'll add the status of the patch series version 3.
Quoted 4 lines
For this one, can split it in 3 patches (one patch for SOC and one for each board) please.
No problem.
Quoted 50 lines
Quoted 50 lines
--- arch/arm/boot/dts/stm32f429-disco.dts | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32f429.dtsi | 35 ++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/stm32f469-disco.dts | 30 ++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 1 deletion(-)arch/arm/boot/dts/stm32f429-disco.dts +25
-0@@ -88,6 +88,16 @@ gpios = <&gpioa 0 0>; }; }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpioc 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &clk_hse {@@ -99,3 +109,23 @@ pinctrl-names = "default"; status = "okay"; }; + +&usbotg_hs { + compatible = "st,stm32-fsotg", "snps,dwc2"; + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + usb-host { + usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PC4_FUNC_GPIO>; + bias-disable;Quoted 9 lines
arch/arm/boot/dts/stm32f429-disco.dts line 131
Quoted 5 lines
arch/arm/boot/dts/stm32f429-disco.dts +5
-0+ drive-push-pull; + }; + }; + }; +};Pinctrl muxing has to be defined/declared in
stm32f429.dtsi
Quoted 2 lines
This is board specific logic and it vary from board to board, should it be defined here?
Pinmuxing definition is a SOC part (as it is a possibility offered by SOC). Pinmuxing choice is board specific.
Regarding your code, it should not boot. Ex for disco:
+ gpio = <&gpiob 2 0>;
Quoted 2 lines
Quoted 2 lines
arch/arm/boot/dts/stm32f429-disco.dts
Quoted 2 lines
arch/arm/boot/dts/stm32f429-disco.dts +2
-0+ pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>;
+
usb-host {
Quoted 3 lines
Quoted 3 lines
arch/arm/boot/dts/stm32f429-disco.dts
Quoted 3 lines
arch/arm/boot/dts/stm32f429-disco.dts +3
-0+ usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PB2_FUNC_GPIO>;
Indeed, you are declaring two time the pin PB2 (one time through pinctrl and one other time through gpiolib). in strict mode you can't request 2 times the same Pin.
I assume that your driver want controls this GPIO (request/set direction / set, get value ...). in this case you only need to declare this part:
gpio = <&gpiob 2 0>;
The GPIO lib will deal with pinctrl framework for you.
And in this case, yes gpio declaration is board specific so this part will be in board file.
Let me know, if I'm not enough clear.
Regards
Alex
Quoted 134 lines
Quoted 112 lines
Quoted 112 lines
arch/arm/boot/dts/stm32f429.dtsi +15
-1@@ -206,7 +206,7 @@ reg = <0x40007000 0x400>; }; - pin-controller { + pinctrl: pin-controller { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f429-pinctrl";@@ -316,6 +316,30 @@ }; }; + usbotg_fs_pins_a: usbotg_fs at 0 { + pins { + pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>, + <STM32F429_PA11_FUNC_OTG_FS_DM>, + <STM32F429_PA12_FUNC_OTG_FS_DP>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_b: usbotg_fs at 1 { + pins { + pinmux =<
STM32F429_PB12_FUNC_OTG_HS_ID>,
+
<STM32F429_PB14_FUNC_OTG_HS_DM>,
+
<STM32F429_PB15_FUNC_OTG_HS_DP>;arch/arm/boot/dts/stm32f429.dtsi +8
-0+ bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + + usbotg_hs_pins_a: usbotg_hs at 0 { pins { pinmux =<
STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,arch/arm/boot/dts/stm32f429.dtsi +9
-0@@ -420,6 +444,15 @@ status = "disabled"; }; + usbotg_fs: usb at 50000000 { + compatible = "st,stm32f4xx-fsotg", "snps,dwc2"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 39>; + clock-names = "otg"; + status = "disabled"; + }; + rng: rng at 50060800 { compatible = "st,stm32-rng"; reg = <0x50060800 0x400>;arch/arm/boot/dts/stm32f469-disco.dts +26
-0@@ -68,6 +68,17 @@ soc { dma-ranges = <0xc0000000 0x0 0x10000000>; }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpiob 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &rcc {@@ -81,3 +92,22 @@ &usart3 { status = "okay"; }; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + usb-host { + usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PB2_FUNC_GPIO>; + bias-disable; + drive-push-pull;Quoted 9 lines
arch/arm/boot/dts/stm32f469-disco.dts line 113
Quoted 4 lines
arch/arm/boot/dts/stm32f469-disco.dts +4
-0+ }; + }; + }; +};Same. Note that if you have 2 configuration for one feature (like it is here for "
usbotg_pwren_h"), you could index it. Not that I'm adding a dedidacted pinctroller for stm32f469.Sorry, but I dont know what you mean by index here.
Theusbotg_pwren_h(VBUS ENABLE) is attached in different port/pins for each board.Br.,
Quoted 6 lines
Br
AlexQuoted 2 lines
Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support
Quoted 123 lines · Alexandre Torgue
Quoted 94 lines · Bruno Herrera
Hi Alex,
Quoted 10 lines · Alexandre Torgue
Hi Bruno,
Quoted 6 lines · Bruno Herrera
This patch adds the USB pins and nodes for USB HS/FS cores working at FS speed,
using embedded PHY.Quoted 5 lines
Quoted 1 line
Signed-off-by Bruno Herrera <[email protected]>Sorry, but what is patch 1 & pacth 3 status ?
My bad, I'll add the status of the patch series version 3.
Quoted 6 lines
For this one, can split it in 3 patches (one patch for SOC and one for each
board) please.No problem.
Quoted 54 lines
Quoted 54 lines
--- arch/arm/boot/dts/stm32f429-disco.dts | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32f429.dtsi | 35 ++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/stm32f469-disco.dts | 30 ++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 1 deletion(-)arch/arm/boot/dts/stm32f429-disco.dts +26
-0@@ -88,6 +88,16 @@ gpios = <&gpioa 0 0>; }; }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpioc 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &clk_hse {@@ -99,3 +109,23 @@ pinctrl-names = "default"; status = "okay"; }; + +&usbotg_hs { + compatible = "st,stm32-fsotg", "snps,dwc2"; + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + usb-host { + usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PC4_FUNC_GPIO>; + bias-disable; + drive-push-pull;Quoted 9 lines
arch/arm/boot/dts/stm32f429-disco.dts line 130
Quoted 4 lines
arch/arm/boot/dts/stm32f429-disco.dts +4
-0+ }; + }; + }; +};Pinctrl muxing has to be defined/declared in
stm32f429.dtsiQuoted 2 lines
This is board specific logic and it vary from board to board, should it be defined here?
Pinmuxing definition is a SOC part (as it is a possibility offered by SOC). Pinmuxing choice is board specific.
Regarding your code, it should not boot. Ex for disco:
+ gpio = <&gpiob 2 0>;
Quoted 2 lines
Quoted 2 lines
arch/arm/boot/dts/stm32f429-disco.dts
Quoted 2 lines
arch/arm/boot/dts/stm32f429-disco.dts +2
-0+ pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>;+
usb-host {
Quoted 3 lines
Quoted 3 lines
arch/arm/boot/dts/stm32f429-disco.dts
Quoted 3 lines
arch/arm/boot/dts/stm32f429-disco.dts +3
-0+ usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PB2_FUNC_GPIO>;Indeed, you are declaring two time the pin PB2 (one time through pinctrl and one other time through gpiolib). in strict mode you can't request 2 times the same Pin.
I assume that your driver want controls this GPIO (request/set direction / set, get value ...). in this case you only need to declare this part:
Quoted 7 lines
gpio = <&gpiob 2 0>;
The GPIO lib will deal with pinctrl framework for you.
And in this case, yes gpio declaration is board specific so this part will be in board file.Let me know, if I'm not enough clear.
Thats very clear! Thanks for bringing.
I'll retest without the pinctrl.
br,
Bruno
Quoted 147 lines
Regards
AlexQuoted 138 lines
Quoted 115 lines
Quoted 115 lines
arch/arm/boot/dts/stm32f429.dtsi +15
-1@@ -206,7 +206,7 @@ reg = <0x40007000 0x400>; }; - pin-controller { + pinctrl: pin-controller { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f429-pinctrl";@@ -316,6 +316,30 @@ }; }; + usbotg_fs_pins_a: usbotg_fs at 0 { + pins { + pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>, + <STM32F429_PA11_FUNC_OTG_FS_DM>, + <STM32F429_PA12_FUNC_OTG_FS_DP>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_b: usbotg_fs at 1 { + pins { + pinmux =<
STM32F429_PB12_FUNC_OTG_HS_ID>,
+
<STM32F429_PB14_FUNC_OTG_HS_DM>,
+
<STM32F429_PB15_FUNC_OTG_HS_DP>;arch/arm/boot/dts/stm32f429.dtsi +8
-0+ bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + + usbotg_hs_pins_a: usbotg_hs at 0 { pins { pinmux =<
STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,arch/arm/boot/dts/stm32f429.dtsi +9
-0@@ -420,6 +444,15 @@ status = "disabled"; }; + usbotg_fs: usb at 50000000 { + compatible = "st,stm32f4xx-fsotg", "snps,dwc2"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 39>; + clock-names = "otg"; + status = "disabled"; + }; + rng: rng at 50060800 { compatible = "st,stm32-rng"; reg = <0x50060800 0x400>;arch/arm/boot/dts/stm32f469-disco.dts +29
-0@@ -68,6 +68,17 @@ soc { dma-ranges = <0xc0000000 0x0 0x10000000>; }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpiob 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; }; &rcc {@@ -81,3 +92,22 @@ &usart3 { status = "okay"; }; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + usb-host { + usbotg_pwren_h: usbotg-pwren-h { + pins { + pinmux = <STM32F429_PB2_FUNC_GPIO>; + bias-disable; + drive-push-pull; + }; + }; + };Quoted 9 lines
arch/arm/boot/dts/stm32f469-disco.dts line 113
Quoted 1 line
arch/arm/boot/dts/stm32f469-disco.dts +1
-0+};Same. Note that if you have 2 configuration for one feature (like it is here
for "usbotg_pwren_h"), you could index it. Not that I'm adding a dedidacted
pinctroller for stm32f469.Sorry, but I dont know what you mean by index here.
Theusbotg_pwren_h(VBUS ENABLE) is attached in different port/pins for each board.Br.,
Quoted 7 lines
Br
AlexQuoted 3 lines
PATCH v2 3/3 dt-bindings: Document the STM32 USB OTG DWC2 core binding
In reply to Bruno HerreraThis patch adds the documentation for STM32F4x9 USB OTG FS/HS compatible strings.
--- Documentation/devicetree/bindings/usb/dwc2.txt | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/usb/dwc2.txt +4 -0
@@ -14,6 +14,10 @@ Required properties: - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs; - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs; - snps,dwc2: A generic DWC2 USB controller with default parameters. + - "st,stm32f4xx-fsotg": The DWC2 USB FS/HS controller instance in STM32F4xx SoCs + configured in FS mode; + - "st,stm32f4xx-hsotg": The DWC2 USB HS controller instance in STM32F4xx SoCs + configured in HS mode; - reg : Should contain 1 register range (address and length) - interrupts : Should contain 1 interrupt - clocks: clock provider specifier
Signature · 1 line
2.10.1 (Apple Git-78)