clk: vc5: Add bindings for IDT VersaClock 5P49V5923 and 5P49V5933
Subsystems (3)
PATCH v2 1/2 clk: vc5: Add bindings for IDT VersaClock 5P49V5923 and 5P49V5933
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs.
---
V2: Add mapping between the clock specifier and physical pins of the chip
--- .../devicetree/bindings/clock/idt,versaclock5.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.txt
Documentation/devicetree/bindings/clock/idt,versaclock5.txt new file +65 -0
@@ -0,0 +1,65 @@ +Binding for IDT VersaClock5 programmable i2c clock generator. + +The IDT VersaClock5 are programmable i2c clock generators providing +from 3 to 12 output clocks. + +==I2C device node== + +Required properties: +- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933". +- reg: i2c device address, shall be 0x68 or 0x6a. +- #clock-cells: from common clock binding; shall be set to 1. +- clocks: from common clock binding; list of parent clock handles, + - 5p49v5923: (required) either or both of XTAL or CLKIN + reference clock. + - 5p49v5933: (optional) property not present (internal + Xtal used) or CLKIN reference + clock. +- clock-names: from common clock binding; clock input names, can be + - 5p49v5923: (required) either or both of "xin", "clkin". + - 5p49v5933: (optional) property not present or "clkin". + +==Mapping between clock specifier and physical pins== + +When referencing the provided clock in the DT using phandle and +clock specifier, the following mapping applies: + +5P49V5923: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT2 + +5P49V5933: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT4 + +==Example== + +/* 25MHz reference crystal */ +ref25: ref25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; +}; + +i2c-master-node { + + /* IDT 5P49V5923 i2c clock generator */ + vc5: clock-generator@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + + /* Connect XIN input to 25MHz reference */ + clocks = <&ref25m>; + clock-names = "xin"; + }; +}; + +/* Consumer referencing the 5P49V5923 pin OUT1 */ +consumer { + ... + clocks = <&vc5 1>; + ... +}
Signature · 1 line
2.11.0
PATCH v6 2/2 clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL.
The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL.
The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar.
---
V2: - Drop address-cells and size-cells from the binding
- Add clock-names to the binding
- Drop vc5_input_names
- Fix assortment of spelling mistakes
- Switch div_frc and div_int datatype to uXX
- Switch f_in to u32
- Add missing remove
- Define macros for handling XIN and CLKIN
- Rework the FOD fractional divider calculation, this was wrong and made the output clock be off considerably under certain circumstances (when the fractional part was large).
V3: - Rework the MUX frequency recalculation and divider configration
so that it fits into the clock framework
- Add support for 5P49V5933 chip to lay groundwork for adding more chips easily.
- Export the OUT0_SEL_I2CB output into the clock framework, so it can be accessed from DT as well. WARNING: This does change the bindings, clock0 is now the OUT0_SEL_I2CB, clock1 is OUT1 and clock2 is OUT2 (or OUT4 on the 5P49V5933).
- Drop unnecessary caching of pin_*_name clock name and clk_hw structures in driver data.
- Add missing MAINTAINERS entry
V4: - Support also 5P49V5923A by dropping the B from the bindings and
code. According to the update notice, the chips are identical except for disabling the VCO monitoring, which is internal factory-defined bit and has no impact on silicon performance.
V5: - Make the CCF handle upstream clock enabling and disabling
- Drop test for unsigned value reg being less than zero
- Streamline vc5_map_index_to_output
V6: - Drop the error message from vc5_of_clk_get(), this will be
reported by the core
--- MAINTAINERS | 5 + drivers/clk/Kconfig | 10 + drivers/clk/Makefile | 1 + drivers/clk/clk-versaclock5.c | 793 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 809 insertions(+) create mode 100644 drivers/clk/clk-versaclock5.c
MAINTAINERS +5 -0
@@ -6113,6 +6113,11 @@ S: Maintained F: drivers/mfd/lpc_ich.c F: drivers/gpio/gpio-ich.c +IDT VersaClock 5 CLOCK DRIVER +M: Marek Vasut <[email protected]> +S: Maintained +F: drivers/clk/clk-versaclock5.c + IDE SUBSYSTEM M: "David S. Miller" <[email protected]> L: [email protected]
drivers/clk/Kconfig +10 -0
@@ -198,6 +198,16 @@ config COMMON_CLK_OXNAS ---help--- Support for the OXNAS SoC Family clocks. +config COMMON_CLK_VC5 + tristate "Clock driver for IDT VersaClock5 devices" + depends on I2C + depends on OF + select REGMAP_I2C + help + ---help--- + This driver supports the IDT VersaClock5 programmable clock + generator. + source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/mediatek/Kconfig"
drivers/clk/Makefile +1 -0
@@ -46,6 +46,7 @@ obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o +obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
drivers/clk/clk-versaclock5.c new file +793 -0
793 lines not on this page · raw message
Signature · 1 line
2.11.0
Re: [PATCH V6 2/2] clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933
Hi Marek,
Thank you for the patch.
Quoted 15 lines · On Thursday 12 Jan 2017 02:03:24 Marek Vasut wrote:
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL.
The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL.
The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar.
Quoted 6 lines
Signed-off-by Marek Vasut <[email protected]>Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Laurent Pinchart <[email protected]>Tested-by Laurent Pinchart <[email protected]>
Quoted 39 lines
---
V2: - Drop address-cells and size-cells from the binding
- Add clock-names to the binding
- Dropvc5_input_names
- Fix assortment of spelling mistakes
- Switchdiv_frcanddiv_intdatatype to uXX
- Switchf_into u32
- Add missing remove
- Define macros for handling XIN and CLKIN
- Rework the FOD fractional divider calculation, this was wrong and made the output clock be off considerably under certain circumstances (when the fractional part was large).
V3: - Rework the MUX frequency recalculation and divider configration
so that it fits into the clock framework
- Add support for 5P49V5933 chip to lay groundwork for adding more chips easily.
- Export theOUT0_SEL_I2CBoutput into the clock framework, so it can be accessed from DT as well. WARNING: This does change the bindings, clock0 is now theOUT0_SEL_I2CB, clock1 is OUT1 and clock2 is OUT2 (or OUT4 on the 5P49V5933).
- Drop unnecessary caching of pin_*_name clock name andclk_hw
structures in driver data.
- Add missingMAINTAINERSentry
V4: - Support also 5P49V5923A by dropping the B from the bindings and
code. According to the update notice, the chips are identical except for disabling the VCO monitoring, which is internal factory-defined bit and has no impact on silicon performance.
V5: - Make the CCF handle upstream clock enabling and disabling
- Drop test for unsigned value reg being less than zero
- Streamlinevc5_map_index_to_output
V6: - Drop the error message fromvc5_of_clk_get(), this will be
reported by the core--- MAINTAINERS | 5 + drivers/clk/Kconfig | 10 + drivers/clk/Makefile | 1 + drivers/clk/clk-versaclock5.c | 793 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 809 insertions(+) create mode 100644 drivers/clk/clk-versaclock5.c
Signature · 3 lines
Regards, Laurent Pinchart
Stephen Boyd
AppliedRe: [PATCH V6 2/2] clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933
In reply to Marek VasutQuoted 15 lines · Marek Vasut
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL.
The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL.
The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar.
Quoted 7 lines
Signed-off-by Marek Vasut <[email protected]>Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Laurent Pinchart <[email protected]>Tested-by Laurent Pinchart <[email protected]>---
Applied to clk-next
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH V6 2/2] clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933
Quoted 24 lines · Stephen Boyd
Quoted 15 lines · Marek Vasut
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL.
The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL.
The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar.
Quoted 7 lines
Signed-off-by Marek Vasut <[email protected]>Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Laurent Pinchart <[email protected]>Tested-by Laurent Pinchart <[email protected]>---
Quoted 2 lines
Applied to clk-next
Thank you :)
Signature · 2 lines
Best regards, Marek Vasut
Hi Marek,
Thank you for the patch.
Quoted 5 lines · On Thursday 12 Jan 2017 02:03:23 Marek Vasut wrote:
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs.
Quoted 7 lines
Signed-off-by Marek Vasut <[email protected]>Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Laurent Pinchart <[email protected]>Cc Rob Herring <[email protected]>
Please add this tag if you submit a v3.
Quoted 80 lines
---
V2: Add mapping between the clock specifier and physical pins of the chip--- .../devicetree/bindings/clock/idt,versaclock5.txt | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644
Documentation/devicetree/bindings/clock/idt,versaclock5.txt(quoted diff) +0
-0
b/Documentation/devicetree/bindings/clock/idt,versaclock5.txtnew file mode 100644
index 000000000000..87e9c47a89a3Documentation/devicetree/bindings/clock/idt,versaclock5.txt new file +65
-0@@ -0,0 +1,65 @@ +Binding for IDT VersaClock5 programmable i2c clock generator. + +The IDT VersaClock5 are programmable i2c clock generators providing +from 3 to 12 output clocks. + +==I2C device node== + +Required properties: +- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933". +- reg: i2c device address, shall be 0x68 or 0x6a. +- #clock-cells: from common clock binding; shall be set to 1. +- clocks: from common clock binding; list of parent clock handles, + - 5p49v5923: (required) either or both of XTAL or CLKIN + reference clock. + - 5p49v5933: (optional) property not present (internal + Xtal used) or CLKIN reference + clock. +- clock-names: from common clock binding; clock input names, can be + - 5p49v5923: (required) either or both of "xin", "clkin". + - 5p49v5933: (optional) property not present or "clkin". + +==Mapping between clock specifier and physical pins== + +When referencing the provided clock in the DT using phandle and +clock specifier, the following mapping applies: + +5P49V5923: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT2 + +5P49V5933: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT4 + +==Example== + +/* 25MHz reference crystal */ +ref25: ref25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; +}; + +i2c-master-node { + + /* IDT 5P49V5923 i2c clock generator */ + vc5: clock-generator@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + + /* Connect XIN input to 25MHz reference */ + clocks = <&ref25m>; + clock-names = "xin"; + }; +}; + +/* Consumer referencing the 5P49V5923 pin OUT1 */ +consumer { + ... + clocks = <&vc5 1>; + ... +}
Signature · 3 lines
Regards, Laurent Pinchart
Hi Marek,
Quoted 30 lines · Marek Vasut
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs.
Signed-off-by Marek Vasut <[email protected]>Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Laurent Pinchart <[email protected]>Cc Rob Herring <[email protected]>---
V2: Add mapping between the clock specifier and physical pins of the chip--- .../devicetree/bindings/clock/idt,versaclock5.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.txtDocumentation/devicetree/bindings/clock/idt,versaclock5.txt new file +4
-0@@ -0,0 +1,65 @@ +==Mapping between clock specifier and physical pins== + +When referencing the provided clock in the DT using phandle and +clock specifier, the following mapping applies:
Documentation/devicetree/bindings/clock/idt,versaclock5.txt line 35
Quoted 10 lines
Documentation/devicetree/bindings/clock/idt,versaclock5.txt new file +10
-0+ +5P49V5923: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT2 + +5P49V5933: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT4
I'm a bit puzzled by the use of "OUT4".
According to the datasheets, both '5923 and '5933 have OUT1 and OUT2. The '5933 datasheet has a single reference to OUT4 ("The OUT1 to OUT4 clock outputs"), but that may be a copy and paste error from a datasheet for a part with 4 outputs.
Apart from that:
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Quoted 1 line · Geert Uytterhoeven
Hi Marek,
Hi!
Quoted 27 lines · Marek Vasut
Quoted 25 lines
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs.
Signed-off-by Marek Vasut <[email protected]>Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Laurent Pinchart <[email protected]>Cc Rob Herring <[email protected]>---
V2: Add mapping between the clock specifier and physical pins of the chip--- .../devicetree/bindings/clock/idt,versaclock5.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.txtDocumentation/devicetree/bindings/clock/idt,versaclock5.txt new file +0
-0@@ -0,0 +1,65 @@
Quoted 16 lines
Quoted 4 lines
Documentation/devicetree/bindings/clock/idt,versaclock5.txt new file +4
-0+==Mapping between clock specifier and physical pins== + +When referencing the provided clock in the DT using phandle and +clock specifier, the following mapping applies:Documentation/devicetree/bindings/clock/idt,versaclock5.txt line 35
Quoted 10 lines
Documentation/devicetree/bindings/clock/idt,versaclock5.txt new file +10
-0+ +5P49V5923: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT2 + +5P49V5933: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT4I'm a bit puzzled by the use of "OUT4".
You're not the only one, but at least you're not the one banging your head against the desk while glaring into the scope and seeing nonsense on one of the channels :-)
Quoted 4 lines
According to the datasheets, both '5923 and '5933 have OUT1 and OUT2. The '5933 datasheet has a single reference to OUT4 ("The OUT1 to OUT4 clock outputs"), but that may be a copy and paste error from a datasheet for a part with 4 outputs.
The physical VC5 5P49V5933 devkit has OUT0 , OUT1 and OUT4 . At first, I thought it was laziness in the PCB design -- because there are VC5s with up to 4 outputs and the devkit PCB is identical for all of them, except some components are not populated -- but that is not correct.
They actually use (inside of the chip) output1 with fod1 and output4 with fod4 for the 5933 and they use output1 with fod1 and output2 with fod2 on the 5923 . This became obvious after I took a look into the IDT clock commander software, which has a visualization of the chip and there are two "unpopulated" positions between out1 and out4 in case of the 5933 while on 5923 the unpopulated positions are below out2 .
I have no explanation as for why they did this, it's just unsystematic.
Quoted 14 lines
Apart from that:
Reviewed-by Geert Uytterhoeven <[email protected]>Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Signature · 2 lines
Best regards, Marek Vasut
Quoted 12 lines · Marek Vasut
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs.
Signed-off-by Marek Vasut <[email protected]>Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Laurent Pinchart <[email protected]>Cc Rob Herring <[email protected]>
Quoted 6 lines
---
V2: Add mapping between the clock specifier and physical pins of the chip--- .../devicetree/bindings/clock/idt,versaclock5.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.txt
Stephen Boyd
AppliedQuoted 5 lines · Marek Vasut
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs.
Quoted 8 lines
Signed-off-by Marek Vasut <[email protected]>Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Laurent Pinchart <[email protected]>Cc Rob Herring <[email protected]>---
Applied to clk-next
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project