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clk: sunxi-ng: Call divider_round_rate if we only have a single parent

PATCH New Maxime Ripard 3 participants 7 messages Jan 24, 2017 – Jan 27, 2017

Subsystems (2)
Common clk Arm/Allwinner sunXi SoC support
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Maxime Ripard

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#0 lore raw

PATCH 1/2 clk: sunxi-ng: Call divider_round_rate if we only have a single parent

The divider_get_val function that is used in our determine_rate callback doesn't try to change the parent rate at all, while clk_divider_bestdiv, used in divider_round_rate, does.

If we have a single parent, call divider_round_rate.

Signed-off-by Maxime Ripard <[email protected]>
---
 drivers/clk/sunxi-ng/ccu_div.c | 12 ++++++++++++
 1 file changed, 12 insertions(+), 0 deletions(-)
drivers/clk/sunxi-ng/ccu_div.c +12 -0
index 8659b4cb6c20..4057e6021aa9 100644
@@ -77,6 +77,18 @@ static int ccu_div_determine_rate(struct clk_hw *hw,
 {
 	struct ccu_div *cd = hw_to_ccu_div(hw);
 
+	if (clk_hw_get_num_parents(hw) == 1) {
+		req->rate = divider_round_rate(hw, req->rate,
+					       &req->best_parent_rate,
+					       cd->div.table,
+					       cd->div.width,
+					       cd->div.flags);
+
+		req->best_parent_hw = clk_hw_get_parent(hw);
+
+		return 0;
+	}
+
 	return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
 					     req, ccu_div_round_rate, cd);
 }

base-commit: 9181f40cede22bff9bc7f26830a4562373f30d73

Signature · 1 line
git-series 0.8.11
author
#1 lore raw

PATCH 2/2 clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU

In order to achieve all the rates asked by the GPU, we might need to change the parent frequency.

Signed-off-by Maxime Ripard <[email protected]>
---
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/sunxi-ng/ccu-sun8i-a33.c +1 -1
index 0d513d2674cb..a7b3c08ed0e2 100644
@@ -468,7 +468,7 @@ static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
 				       0x180, 0, 4, 24, 3, BIT(31), 0);
 
 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
-			     0x1a0, 0, 3, BIT(31), 0);
+			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
 
 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
Signature · 1 line
git-series 0.8.11
#2 lore raw

PATCH 2/2 clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU

Quoted 5 lines · Maxime Ripard

In order to achieve all the rates asked by the GPU, we might need to change the parent frequency.

Signed-off-by Maxime Ripard <[email protected]>

---

Acked-by Stephen Boyd <[email protected]>
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
#3 lore raw

PATCH 2/2 clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU

Quoted 8 lines · Stephen Boyd
Quoted 5 lines · Maxime Ripard

In order to achieve all the rates asked by the GPU, we might need to change the parent frequency.

Signed-off-by Maxime Ripard <[email protected]>

---

Acked-by Stephen Boyd <[email protected]>
Acked-by Chen-Yu Tsai <[email protected]>
Quoted 3 lines

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

#4 lore raw

PATCH 1/2 clk: sunxi-ng: Call divider_round_rate if we only have a single parent

In reply to Maxime Ripard
Quoted 8 lines · Maxime Ripard

The divider_get_val function that is used in our determine_rate callback doesn't try to change the parent rate at all, while clk_divider_bestdiv, used in divider_round_rate, does.

If we have a single parent, call divider_round_rate.

Signed-off-by Maxime Ripard <[email protected]>

---

Acked-by Stephen Boyd <[email protected]>
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
#5 lore raw

PATCH 1/2 clk: sunxi-ng: Call divider_round_rate if we only have a single parent

Quoted 6 lines · Stephen Boyd
Quoted 5 lines · Maxime Ripard

The divider_get_val function that is used in our determine_rate callback doesn't try to change the parent rate at all, while clk_divider_bestdiv, used in divider_round_rate, does.

If we have a single parent, call divider_round_rate.

I guess my "clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT" patch somewhat takes care of the multi-parent case? Still, the underlying clock type doesn't get to specify what is considers to be the best parent rate.

Quoted 4 lines
Quoted 2 lines
Signed-off-by Maxime Ripard <[email protected]>

---

Acked-by Stephen Boyd <[email protected]>
Acked-by Chen-Yu Tsai <[email protected]>
author
#6 lore raw

PATCH 1/2 clk: sunxi-ng: Call divider_round_rate if we only have a single parent

Quoted 11 lines · Chen-Yu Tsai
Quoted 6 lines · Stephen Boyd
Quoted 5 lines · Maxime Ripard

The divider_get_val function that is used in our determine_rate callback doesn't try to change the parent rate at all, while clk_divider_bestdiv, used in divider_round_rate, does.

If we have a single parent, call divider_round_rate.

I guess my "clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT" patch somewhat takes care of the multi-parent case?

It looks like it does yes :)

Quoted 9 lines

Still, the underlying clock type doesn't get to specify what is considers to be the best parent rate.

Quoted 4 lines
Quoted 2 lines
Signed-off-by Maxime Ripard <[email protected]>

---

Acked-by Stephen Boyd <[email protected]>
Acked-by Chen-Yu Tsai <[email protected]>

Merged the two patches with Stephen and your Acked-bY.

Thanks!
Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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