clk: renesas: cpg-mssr: r8a7796: add IMR clocks
Subsystems (2)
PATCH 1/1 clk: renesas: cpg-mssr: r8a7796: add IMR clocks
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.
---
This patch is against the 'clk-next' branch of CLK group's 'linux.git' repo.
drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/clk/renesas/r8a7796-cpg-mssr.c +2 -0
@@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796DEF_MOD ("vin1" ,810 ,R8A7796_CLK_S0D2 ),DEF_MOD ("vin0" ,811 ,R8A7796_CLK_S0D2 ),DEF_MOD ("etheravb" ,812 ,R8A7796_CLK_S0D6 ), +DEF_MOD ("imr1" ,822 ,R8A7796_CLK_S2D1 ), +DEF_MOD ("imr0" ,823 ,R8A7796_CLK_S2D1 ),DEF_MOD ("gpio7" ,905 ,R8A7796_CLK_S3D4 ),DEF_MOD ("gpio6" ,906 ,R8A7796_CLK_S3D4 ), DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4),
Hi Sergei,
Quoted 3 lines · Sergei Shtylyov
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.
Signed-off-by Sergei Shtylyov <[email protected]>
drivers/clk/renesas/r8a7796-cpg-mssr.c static const struct mssr_mod_clk r8a7796 · line 183
Quoted 8 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c +2
-0@@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796DEF_MOD ("vin1" ,810 ,R8A7796_CLK_S0D2 ),DEF_MOD ("vin0" ,811 ,R8A7796_CLK_S0D2 ),DEF_MOD ("etheravb" ,812 ,R8A7796_CLK_S0D6 ), +DEF_MOD ("imr1" ,822 ,R8A7796_CLK_S2D1 ), + DEF_MOD("imr0", 823, R8A7796_CLK_S2D1),
According to R-Car Gen3 Hardware Users Manual Rev.0.53E, the parent clock is S0D2, like on H3 ES2.0.
Will queue in clk-renesas-for-v4.12 with corrected parent clock.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Quoted 6 lines · Geert Uytterhoeven
Quoted 3 lines
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>
Quoted 11 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c static const struct mssr_mod_clk r8a7796 · line 183
Quoted 8 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c +2
-0@@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796DEF_MOD ("vin1" ,810 ,R8A7796_CLK_S0D2 ),DEF_MOD ("vin0" ,811 ,R8A7796_CLK_S0D2 ),DEF_MOD ("etheravb" ,812 ,R8A7796_CLK_S0D6 ), +DEF_MOD ("imr1" ,822 ,R8A7796_CLK_S2D1 ), + DEF_MOD("imr0", 823, R8A7796_CLK_S2D1),According to R-Car Gen3 Hardware Users Manual Rev.0.53E, the parent clock is S0D2, like on H3 ES2.0.
I only have 0.51E here, doesn't seem to contain much of the clock info...
Quoted 1 line
Will queue in clk-renesas-for-v4.12 with corrected parent clock.
Thank you!
Quoted 3 lines
Gr{oetje,eeting}s,
Geert
MBR, Sergei
Quoted 6 lines · Geert Uytterhoeven
Quoted 3 lines
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>
Quoted 11 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c static const struct mssr_mod_clk r8a7796 · line 183
Quoted 8 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c +2
-0@@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796DEF_MOD ("vin1" ,810 ,R8A7796_CLK_S0D2 ),DEF_MOD ("vin0" ,811 ,R8A7796_CLK_S0D2 ),DEF_MOD ("etheravb" ,812 ,R8A7796_CLK_S0D6 ), +DEF_MOD ("imr1" ,822 ,R8A7796_CLK_S2D1 ), + DEF_MOD("imr0", 823, R8A7796_CLK_S2D1),According to R-Car Gen3 Hardware Users Manual Rev.0.53E, the parent clock is S0D2, like on H3 ES2.0.
Not S0D4? I'd expect that what they call "register access" to be
controlled by the MSSR bits...
Quoted 1 line
Will queue in clk-renesas-for-v4.12 with corrected parent clock.
So, what have you used for 7795 and 7796?
Quoted 3 lines
Gr{oetje,eeting}s,
Geert
MBR, Sergei
Hi Sergei,
Quoted 20 lines · Sergei Shtylyov
Quoted 6 lines · Geert Uytterhoeven
Quoted 3 lines
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>Quoted 12 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c static const struct mssr_mod_clk r8a7796 · line 183
Quoted 8 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c +2
-0@@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796DEF_MOD ("vin1" ,810 ,R8A7796_CLK_S0D2 ),DEF_MOD ("vin0" ,811 ,R8A7796_CLK_S0D2 ),DEF_MOD ("etheravb" ,812 ,R8A7796_CLK_S0D6 ), +DEF_MOD ("imr1" ,822 ,R8A7796_CLK_S2D1 ), + DEF_MOD("imr0", 823, R8A7796_CLK_S2D1),According to R-Car Gen3 Hardware Users Manual Rev.0.53E, the parent clock is S0D2, like on H3 ES2.0.
Quoted 2 lines
Not S0D4? I'd expect that what they call "register access" to be
controlled by the MSSR bits...
Good question...
Quoted 3 lines
Quoted 1 line
Will queue in clk-renesas-for-v4.12 with corrected parent clock.
So, what have you used for 7795 and 7796?
S2D1 for r8a7795 (H3 ES1.0)
S0D2 for r8a7796 (M3-W)
And I planned to use S0D2 for H3 ES2.0, too.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Quoted 25 lines · Geert Uytterhoeven
Quoted 20 lines · Geert Uytterhoeven
Quoted 6 lines
Quoted 3 lines
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>Quoted 12 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c static const struct mssr_mod_clk r8a7796 · line 183
Quoted 8 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c +2
-0@@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796DEF_MOD ("vin1" ,810 ,R8A7796_CLK_S0D2 ),DEF_MOD ("vin0" ,811 ,R8A7796_CLK_S0D2 ),DEF_MOD ("etheravb" ,812 ,R8A7796_CLK_S0D6 ), +DEF_MOD ("imr1" ,822 ,R8A7796_CLK_S2D1 ), + DEF_MOD("imr0", 823, R8A7796_CLK_S2D1),According to R-Car Gen3 Hardware Users Manual Rev.0.53E, the parent clock is S0D2, like on H3 ES2.0.
Quoted 2 lines
Not S0D4? I'd expect that what they call "register access" to be
controlled by the MSSR bits...Good question...
Quoted 8 lines
Quoted 3 lines
Quoted 1 line
Will queue in clk-renesas-for-v4.12 with corrected parent clock.
So, what have you used for 7795 and 7796?
S2D1 for r8a7795 (H3 ES1.0)
S0D2 for r8a7796 (M3-W)And I planned to use S0D2 for H3 ES2.0, too.
Looks to me we should be using S0D4 for both. And perhaps the 2nd
specifier for S0D2.
Quoted 3 lines
Gr{oetje,eeting}s,
Geert
MBR, Sergei
Hi Sergei,
Quoted 19 lines · Sergei Shtylyov
Quoted 18 lines · Geert Uytterhoeven
Quoted 18 lines · Geert Uytterhoeven
Quoted 16 lines
Quoted 3 lines
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>drivers/clk/renesas/r8a7796-cpg-mssr.c static const struct mssr_mod_clk r8a7796 · line 183
Quoted 8 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c +2
-0@@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796DEF_MOD ("vin1" ,810 ,R8A7796_CLK_S0D2 ),DEF_MOD ("vin0" ,811 ,R8A7796_CLK_S0D2 ),DEF_MOD ("etheravb" ,812 ,R8A7796_CLK_S0D6 ), +DEF_MOD ("imr1" ,822 ,R8A7796_CLK_S2D1 ), + DEF_MOD("imr0", 823, R8A7796_CLK_S2D1),According to R-Car Gen3 Hardware Users Manual Rev.0.53E, the parent clock is S0D2, like on H3 ES2.0.
Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
Not S0D4? I'd expect that what they call "register access" to be
controlled by the MSSR bits...
I think in reality, both are gated by the same MSSR bit ;-)
However, if the driver needs to know the frequency of the clock, or control it (e.g. it's driving some external interface), it's always interested in the module's internal clock, not the clock used for register access. The latter is just an artifact of synchronous hardware.
Quoted 1 line
Quoted 1 line
Good question...
I've just finished going over all modules and their (known) parents on R-Car H3 (ES1.x and ES2.0), and M3-W.
If multiple clock inputs are known, we always use the internal clock, which is consistent with my comment above.
Quoted 11 lines
Quoted 8 lines
Quoted 3 lines
Quoted 1 line
Will queue in clk-renesas-for-v4.12 with corrected parent clock.
So, what have you used for 7795 and 7796?
S2D1 for r8a7795 (H3 ES1.0)
S0D2 for r8a7796 (M3-W)And I planned to use S0D2 for H3 ES2.0, too.
Looks to me we should be using S0D4 for both. And perhaps the 2nd
specifier for S0D2.
We typically don't list all other parents clocks, unless we need to query/control them (especially if they can't be gated from Linux, like the internal SxDy clocks).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds