Introduce DCU support for Vybrid

index 52fb6f8d51..b84a1a686a 100644
@@ -91,7 +91,7 @@ int arch_soc_init(void)
 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
 
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 #endif
 

index 5c9b41f2e7..675bf08e5f 100644
@@ -434,9 +434,7 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Video
  */
-#define CONFIG_FSL_DCU_FB
-
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
 #define CONFIG_CMD_BMP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO

index 25e3f92cf5..c7bc312752 100644
@@ -313,9 +313,7 @@
 /*
  * Video
  */
-#define CONFIG_FSL_DCU_FB
-
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
 #define CONFIG_CMD_BMP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO

73 lines not on this page · raw message

index 42632984d3..67e29e74e6 100644
@@ -9,6 +9,7 @@
 
 int fsl_dcu_init(unsigned int xres, unsigned int yres,
 		 unsigned int pixel_format);
+int fsl_dcu_fixedfb_setup(void *blob);
 
 /* Prototypes for external board-specific functions */
 int platform_dcu_init(unsigned int xres, unsigned int yres,

index a456bd17da..c6fdedb5cf 100644
@@ -41,7 +41,7 @@
 #define DCU_VSYN_PARA_BP(x)		((x) << 22)
 #define DCU_VSYN_PARA_PW(x)		((x) << 11)
 #define DCU_VSYN_PARA_FP(x)		(x)
-#define DCU_SYN_POL_INV_PXCK_FALL	(0 << 6)
+#define DCU_SYN_POL_INV_PXCK_FALL	(1 << 6)
 #define DCU_SYN_POL_NEG_REMAIN		(0 << 5)
 #define DCU_SYN_POL_INV_VS_LOW		(1 << 1)
 #define DCU_SYN_POL_INV_HS_LOW		(1)

@@ -191,8 +191,6 @@ static void reset_total_layers(void)
 		dcu_write32(&regs->ctrldescl[i][9], 0);
 		dcu_write32(&regs->ctrldescl[i][10], 0);
 	}
-
-	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
 }
 
 static int layer_ctrldesc_init(int index, u32 pixel_format)

@@ -246,8 +244,6 @@ static int layer_ctrldesc_init(int index, u32 pixel_format)
 	dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
 	dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
 
-	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
-
 	return 0;
 }
 

@@ -270,8 +266,6 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
 	memset(info.screen_base, 0, info.screen_size);
 
 	reset_total_layers();
-	div = dcu_set_pixel_clock(info.var.pixclock);
-	dcu_write32(&regs->div_ratio, (div - 1));
 
 	dcu_write32(&regs->disp_size,
 		    DCU_DISP_SIZE_DELTA_Y(info.var.yres) |

@@ -310,6 +304,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
 
 	layer_ctrldesc_init(0, pixel_format);
 
+	div = dcu_set_pixel_clock(info.var.pixclock);
+	dcu_write32(&regs->div_ratio, (div - 1));
+
+	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
+
 	return 0;
 }
 

index 2f7233f2fe..7a909c88af 100644
@@ -107,6 +107,7 @@
 #define CONFIG_SYS_FSL_SRK_LE
 
 #define DCU_LAYER_MAX_NUM			16
+#define DCU_TOTAL_LAYER_NUM			16
 
 #ifdef CONFIG_LS102XA
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1

index c6fdedb5cf..22aba7ef48 100644
@@ -178,7 +178,7 @@ static void reset_total_layers(void)
 	struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
 	int i;
 
-	for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
+	for (i = 0; i < DCU_TOTAL_LAYER_NUM; i++) {
 		dcu_write32(&regs->ctrldescl[i][0], 0);
 		dcu_write32(&regs->ctrldescl[i][1], 0);
 		dcu_write32(&regs->ctrldescl[i][2], 0);

@@ -188,8 +188,10 @@ static void reset_total_layers(void)
 		dcu_write32(&regs->ctrldescl[i][6], 0);
 		dcu_write32(&regs->ctrldescl[i][7], 0);
 		dcu_write32(&regs->ctrldescl[i][8], 0);
+#ifdef CONFIG_LS102XA
 		dcu_write32(&regs->ctrldescl[i][9], 0);
 		dcu_write32(&regs->ctrldescl[i][10], 0);
+#endif
 	}
 }
 

index 22aba7ef48..6a66e788e0 100644
@@ -104,7 +104,7 @@ static struct fb_videomode fsl_dcu_mode_480_272 = {
 /*
  * This setting is used for Siliconimage SiI9022A HDMI
  */
-static struct fb_videomode fsl_dcu_mode_640_480 = {
+static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
 	.name		= "640x480-60",
 	.refresh	= 60,
 	.xres		= 640,

@@ -120,6 +120,54 @@ static struct fb_videomode fsl_dcu_mode_640_480 = {
 	.vmode		= FB_VMODE_NONINTERLACED,
 };
 
+static struct fb_videomode fsl_dcu_mode_640_480 = {
+	.name		= "640x480-60",
+	.refresh	= 60,
+	.xres		= 640,
+	.yres		= 480,
+	.pixclock	= 25175,
+	.left_margin	= 40,
+	.right_margin	= 24,
+	.upper_margin	= 32,
+	.lower_margin	= 11,
+	.hsync_len	= 96,
+	.vsync_len	= 2,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_800_480 = {
+	.name		= "800x480-60",
+	.refresh	= 60,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= 33260,
+	.left_margin	= 216,
+	.right_margin	= 40,
+	.upper_margin	= 35,
+	.lower_margin	= 10,
+	.hsync_len	= 128,
+	.vsync_len	= 2,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_1024_600 = {
+	.name		= "1024x600-60",
+	.refresh	= 60,
+	.xres		= 1024,
+	.yres		= 600,
+	.pixclock	= 48000,
+	.left_margin	= 104,
+	.right_margin	= 43,
+	.upper_margin	= 24,
+	.lower_margin	= 20,
+	.hsync_len	= 5,
+	.vsync_len	= 5,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED,
+};
+
 /*
  * DCU register map
  */

@@ -341,7 +389,16 @@ void *video_hw_init(void)
 		fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
 		break;
 	case RESOLUTION(640, 480):
-		fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
+		if (!strncmp(options, "monitor=hdmi", 12))
+			fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
+		else
+			fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
+		break;
+	case RESOLUTION(800, 480):
+		fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
+		break;
+	case RESOLUTION(1024, 600):
+		fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
 		break;
 	default:
 		printf("unsupported resolution %ux%u\n",

index a46e396f1d..73b1dd2f14 100644
@@ -9,6 +9,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/types.h>
+
 /* Clock Controller Module (CCM) */
 struct ccm_reg {
 	u32 ccr;

@@ -150,6 +152,9 @@ struct anadig_reg {
 #define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
 #define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)
 
+#define CCM_CSCMR1_DCU1_CLK_SEL			(1 << 29)
+#define CCM_CSCMR1_DCU0_CLK_SEL			(1 << 28)
+
 #define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET		22
 #define CCM_CSCMR1_QSPI0_CLK_SEL_MASK		(0x3 << 22)
 #define CCM_CSCMR1_QSPI0_CLK_SEL(v)		(((v) & 0x3) << 22)

@@ -174,6 +179,13 @@ struct anadig_reg {
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_DCU1_EN			(1 << 23)
+#define CCM_CSCDR3_DCU1_DIV_MASK		(0x7 << 20)
+#define CCM_CSCDR3_DCU1_DIV(v)			(((v) & 0x7) << 20)
+#define CCM_CSCDR3_DCU0_EN			(1 << 19)
+#define CCM_CSCDR3_DCU0_DIV_MASK		(0x7 << 16)
+#define CCM_CSCDR3_DCU0_DIV(v)			(((v) & 0x7) << 16)
+
 #define CCM_CSCDR3_NFC_PRE_DIV_OFFSET		13
 #define CCM_CSCDR3_NFC_PRE_DIV_MASK		(0x7 << 13)
 #define CCM_CSCDR3_NFC_PRE_DIV(v)		(((v) & 0x7) << 13)

@@ -193,6 +205,7 @@ struct anadig_reg {
 #define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
+#define CCM_CCGR1_TCON0_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
 #define CCM_CCGR2_IOMUXC_CTRL_MASK		(0x3 << 16)

@@ -203,6 +216,7 @@ struct anadig_reg {
 #define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
 #define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
+#define CCM_CCGR3_DCU0_CTRL_MASK		(0x3 << 16)
 #define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)

index 9758323433..c080b2f76b 100644
@@ -69,6 +69,7 @@
 #define USB_PHY0_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050800)
 #define USB_PHY1_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050C00)
 #define SCSC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00058000)
 #define ASRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00060000)
 #define SPDIF_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00061000)
 #define ESAI_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00062000)

@@ -98,6 +99,7 @@
 #define USBC1_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00034000)
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00058000)
 #define NFC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00060000)
 
 #define QSPI0_AMBA_BASE		0x20000000

index a140be05f1..5af071a4db 100644
@@ -40,6 +40,8 @@
 				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
 #define VF610_DSPI_SIN_PAD_CTRL	(PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \
 				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
+#define VF610_DCU_PAD_CTRL     (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_DSE_37ohm | PAD_CTL_OBE_ENABLE)
 
 enum {
 	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),

@@ -166,6 +168,35 @@ enum {
 
 	VF610_PAD_PTC28__NF_CLE  		= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
+	VF610_PAD_PTE0__DCU0_HSYNC		= IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE1__DCU0_VSYNC		= IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE2__DCU0_PCLK		= IOMUX_PAD(0x01ac, 0x01ac, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE4__DCU0_DE			= IOMUX_PAD(0x01b4, 0x01b4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE5__DCU0_R0			= IOMUX_PAD(0x01b8, 0x01b8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE6__DCU0_R1			= IOMUX_PAD(0x01bc, 0x01bc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE7__DCU0_R2			= IOMUX_PAD(0x01c0, 0x01c0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE8__DCU0_R3			= IOMUX_PAD(0x01c4, 0x01c4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE9__DCU0_R4			= IOMUX_PAD(0x01c8, 0x01c8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE10__DCU0_R5		= IOMUX_PAD(0x01cc, 0x01cc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE11__DCU0_R6		= IOMUX_PAD(0x01d0, 0x01d0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE12__DCU0_R7		= IOMUX_PAD(0x01d4, 0x01d4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE13__DCU0_G0		= IOMUX_PAD(0x01d8, 0x01d8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE14__DCU0_G1		= IOMUX_PAD(0x01dc, 0x01dc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE15__DCU0_G2		= IOMUX_PAD(0x01e0, 0x01e0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE16__DCU0_G3		= IOMUX_PAD(0x01e4, 0x01e4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE17__DCU0_G4		= IOMUX_PAD(0x01e8, 0x01e8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE18__DCU0_G5		= IOMUX_PAD(0x01ec, 0x01ec, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE19__DCU0_G6		= IOMUX_PAD(0x01f0, 0x01f0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE20__DCU0_G7		= IOMUX_PAD(0x01f4, 0x01f4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE21__DCU0_B0		= IOMUX_PAD(0x01f8, 0x01f8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE22__DCU0_B1		= IOMUX_PAD(0x01fc, 0x01fc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE23__DCU0_B2		= IOMUX_PAD(0x0200, 0x0200, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE24__DCU0_B3		= IOMUX_PAD(0x0204, 0x0204, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE25__DCU0_B4		= IOMUX_PAD(0x0208, 0x0208, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE26__DCU0_B5		= IOMUX_PAD(0x020c, 0x020c, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE27__DCU0_B6		= IOMUX_PAD(0x0210, 0x0210, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE28__DCU0_B7		= IOMUX_PAD(0x0214, 0x0214, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+
 	VF610_PAD_DDR_RESETB			= IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),

index 7587cbbf95..ba0ed43811 100644
@@ -165,7 +165,10 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_ODE		(1 << 10)
 
 #define PAD_CTL_DSE_150ohm	(1 << 6)
+#define PAD_CTL_DSE_75ohm	(2 << 6)
 #define PAD_CTL_DSE_50ohm	(3 << 6)
+#define PAD_CTL_DSE_37ohm	(4 << 6)
+#define PAD_CTL_DSE_30ohm	(5 << 6)
 #define PAD_CTL_DSE_25ohm	(6 << 6)
 #define PAD_CTL_DSE_20ohm	(7 << 6)
 

118 lines not on this page · raw message

new file mode 100644
index 0000000000..3fa6a763d8
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * FSL DCU platform driver
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	unsigned long long div;
+
+	clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
+	clrsetbits_le32(&ccm->cscdr3,
+			CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
+			CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
+	div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
+	do_div(div, pixclock);
+
+	return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+		      const char *port,
+		      struct fb_videomode *dcu_fb_videomode)
+{
+	fsl_dcu_init(xres, yres, 32);
+
+	return 0;
+}

index e0feb0a152..413695aab7 100644
@@ -27,8 +27,20 @@
 #define CONFIG_MXC_OCOTP
 #endif
 
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SYS_FSL_DCU_LE
+
+#define CONFIG_SYS_DCU_ADDR		DCU0_BASE_ADDR
+#define DCU_TOTAL_LAYER_NUM		64
+#define DCU_LAYER_MAX_NUM		6
+#endif
+
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 4 * 1024 * 1024)
 
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE

@@ -133,6 +145,8 @@
 	"setupdate=run setsdupdate || run setusbupdate\0" \
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+	"video-mode=dcufb:640x480-16 at 60,monitor=lcd\0" \
+	"splashpos=m,m\0" \
 	SD_BOOTCMD \
 	NFS_BOOTCMD \
 	UBI_BOOTCMD

@@ -157,7 +171,7 @@
  * Stack sizes
  * The stack sizes are set up in start.S using the settings below
  */
-#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
+#define CONFIG_STACKSIZE		SZ_256K
 
 /* Physical memory map */
 #define CONFIG_NR_DRAM_BANKS		1