arm64: dts: renesas: Remove unit-addresses and regs from integrated caches

Hi Simon, Magnus,

This patch series removes the bogus unit-addresses and reg properties from the device nodes representing Cortex-A57/A53 cache controllers.

Note that the latter were added to remove warnings from dtc when using W=1:

Warning (unit_address_vs_reg): Node /cache-controller at 0 has a unit name, but no reg property

In hindsight, adding the reg properties turned out to be the wrong fix. Indeed, the Cortex-A57/A53 cache controllers are integrated controllers, and thus the device nodes representing them should not have unit-addresses or reg properties.

This series does not have a runtime effect, as Linux doesn't rely much on the properties of the cache-controller nodes.

After this patch has been accepted, I'll submit a similar series to fix the DTS files for the Renesas arm32 SoCs.

Thanks for applying!

Geert Uytterhoeven (2):
arm64: dts: r8a7795: Remove unit-addresses and regs from integrated
caches
arm64: dts: r8a7796: Remove unit-address and reg from integrated cache

 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++----
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 3 +--
 2 files changed, 3 insertions(+), 6 deletions(-)

2.7.4

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

The Cortex-A57/A53 cache controllers are integrated controllers, and thus the device nodes representing them should not have unit-addresses or reg properties.

---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

index 13833aa8e035be04..67a8d2a4c9b568cc 100644
@@ -110,17 +110,15 @@
 			enable-method = "psci";
 		};
 
-		L2_CA57: cache-controller at 0 {
+		L2_CA57: cache-controller-0 {
 			compatible = "cache";
-			reg = <0>;
 			power-domains = <&sysc R8A7795_PD_CA57_SCU>;
 			cache-unified;
 			cache-level = <2>;
 		};
 
-		L2_CA53: cache-controller at 100 {
+		L2_CA53: cache-controller-1 {
 			compatible = "cache";
-			reg = <0x100>;
 			power-domains = <&sysc R8A7795_PD_CA53_SCU>;
 			cache-unified;
 			cache-level = <2>;

2.7.4

The Cortex-A57 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or reg property.

---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

index f02dfdce92406f67..b950dcec9ace96a1 100644
@@ -48,9 +48,8 @@
 			enable-method = "psci";
 		};
 
-		L2_CA57: cache-controller at 0 {
+		L2_CA57: cache-controller-0 {
 			compatible = "cache";
-			reg = <0>;
 			power-domains = <&sysc R8A7796_PD_CA57_SCU>;
 			cache-unified;
 			cache-level = <2>;

2.7.4

Thanks, applied.