Meson GXL USB2 PHY driver
Martin Blumenstingl
reviewercover Meson GXL USB2 PHY driver
This series adds a driver for the USB2 PHYs found in Amlogic Meson GXL (and GXM) SoCs.
Devicetree changes are intentionally missing in this series because of various other problems that need to be resolved before we get USB host support working.
As usual we unfortunately don't have any documentation available. The register definitions were taken from the vendor's GPL kernel sources (see [5] if you are really interested). Translation to human readable names is done using the "best effort" algorithm.
The USB situation on GXL and GXM is a bit special:
the SoCs include both, a dwc3 and a dwc2 controller. The dwc3 controller IP only supports host-mode, while the dwc2 controller IP only supports device mode.
The dwc3 controller has all USB3 ports disabled. GXL has two USB2 ports enabled on dwc3's internal hub, while GXM has three USB2 ports enabled. This makes the initialization a bit special: to enable any of the dwc3 controller's USB2 ports *ALL* PHYs have to be initialized (probably due to the hub's routing logic).
The first USB2 PHY (hardware-wise) also supports OTG mode. The vendor kernel implements this through the USB3 PHY by re-routing the first USB2 PHY from the dwc3 controller to the dwc2 controller (which is disabled by default, but if the USB3 PHY detects that the port should enter device mode it enables the dwc2 controller).
To get USB host mode working the following steps are needed:
- xhci-plat must be able to manage more than one PHY for a controller, this is work-in-progress, see [0]
- there are some DMA handling issues in dwc3 and the rest of the USB stack, this is solved by the "sysdev" patches from [1]
- adding all USB related bits to meson-gxl.dtsi - this is work in progress but depends on the previous TODOs, see [2] and [3]
This supersedes my previous series "Meson GXL and GXM USB support" [4].
[0] https://www.spinics.net/lists/linux-usb/msg151837.html
[1] http://www.mail-archive.com/linux-usb at vger.kernel.org/msg87077.html
[2] https://github.com/xdarklight/linux/commit/e2b83785687fe859ae4bba8da8bb2fb2d7e32bfb
[3] https://github.com/xdarklight/linux/commit/203ab9ea5d1bea0bf066b6738010c8072b821d87
[4] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/001721.html
[5] https://github.com/khadas/linux/blob/76fd19ac41bb774e396ce8009ff665f29c26c535/include/linux/amlogic/usb-gxl.h
Martin Blumenstingl (2):
Documentation: dt-bindings: Add documentation for the Meson GXL USB2
PHY
phy: meson: add USB2 PHY support for Meson GXL and GXM
.../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 ++ drivers/phy/Kconfig | 13 + drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 263 +++++++++++++++++++++ 4 files changed, 294 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt create mode 100644 drivers/phy/phy-meson-gxl-usb2.c
Signature · 1 line
2.12.0
Martin Blumenstingl
reviewerPATCH 1/2 Documentation: dt-bindings: Add documentation for the Meson GXL USB2 PHY
This adds the DT binding documentation for the USB2 PHY(s) found in the Meson GXL and GXM SoCs.
--- .../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt new file +17 -0
@@ -0,0 +1,17 @@ +* Amlogic Meson GXL and GXM USB2 PHY binding + +Required properties: +- compatible: Should be "amlogic,meson-gxl-usb2-phy" +- reg: The base address and length of the registers +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) + +Optional properties: +- phy-supply: see phy-bindings.txt in this directory + + +Example: + usb2_phy0: phy at 78000 { + compatible = "amlogic,meson-gxl-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0x78000 0x0 0x20>; + };
Signature · 1 line
2.12.0
Rob Herring
maintainerPATCH 1/2 Documentation: dt-bindings: Add documentation for the Meson GXL USB2 PHY
Quoted 8 lines · Martin Blumenstingl
This adds the DT binding documentation for the USB2 PHY(s) found in the Meson GXL and GXM SoCs.
Signed-off-by Martin Blumenstingl <[email protected]>--- .../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
Martin Blumenstingl
reviewerPATCH 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
In reply to Martin BlumenstinglThis adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for any of these PHYs. Both drivers were written by reading the reference drivers provided by Amlogic and analyzing the registers on the kernel that was shipped on the boards I have.
--- drivers/phy/Kconfig | 13 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 263 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.c
drivers/phy/Kconfig +13 -0
@@ -486,4 +486,17 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + endmenu
drivers/phy/Makefile +1 -0
@@ -59,3 +59,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.o
drivers/phy/phy-meson-gxl-usb2.c new file +263 -0
263 lines not on this page · raw message
Signature · 1 line
2.12.0
PATCH 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Currently just trying to learn by reading, but a minor comment inline.
Quoted 227 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for any of these PHYs. Both drivers were written by reading the reference drivers provided by Amlogic and analyzing the registers on the kernel that was shipped on the boards I have.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 13 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 263 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +13
-0@@ -486,4 +486,17 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + endmenudrivers/phy/Makefile +1
-0@@ -59,3 +59,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.odrivers/phy/phy-meson-gxl-usb2.c new file +171
-0@@ -0,0 +1,263 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/usb/of.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +if (priv->is_enabled) { +/* reset the PHY and wait until settings are stabilized */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); +udelay (RESET_COMPLETE_TIME ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +0 ); +udelay (RESET_COMPLETE_TIME ); + } + + priv->mode = mode; + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_off (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + + priv->is_enabled =0 ; + +/* power off the PHY by putting it into reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_on (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); +int ret; + + priv->is_enabled =1 ;
drivers/phy/phy-meson-gxl-usb2.c line 181
Quoted 10 lines
drivers/phy/phy-meson-gxl-usb2.c new file +10
-0+ +/* power on the PHY by taking it out of reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); + + ret =phy_meson_gxl_usb2_set_mode (phy, priv->mode); +if (ret) { +phy_meson_gxl_usb2_power_off (phy); + +dev_err (&phy->dev,"Failed to initialize PHY with mode %d\n" , + priv->mode);
Shouldn't priv->is_enabled be reseted to 0 in this case?
drivers/phy/phy-meson-gxl-usb2.c line 185
Quoted 4 lines
drivers/phy/phy-meson-gxl-usb2.c new file +4
-0+return ret; + } + +return 0 ;
This can be merged with return ret from the error case.
Quoted 86 lines
drivers/phy/phy-meson-gxl-usb2.c new file +78
-0+} + +static const struct phy_ops phy_meson_gxl_usb2_ops = { + .power_on = phy_meson_gxl_usb2_power_on, + .power_off = phy_meson_gxl_usb2_power_off, + .set_mode = phy_meson_gxl_usb2_set_mode, + .owner =THIS_MODULE , +}; + +static int phy_meson_gxl_usb2_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +struct phy_provider *phy_provider; +struct resource *res; +struct phy_meson_gxl_usb2_priv *priv; +struct phy *phy; +void __iomem *base; + + priv =devm_kzalloc (dev,sizeof (*priv),GFP_KERNEL ); +if (!priv) +return -ENOMEM ; + +platform_set_drvdata (pdev, priv); + + res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); + base =devm_ioremap_resource (dev, res); +if (IS_ERR (base)) +return PTR_ERR (base); + +switch (of_usb_get_dr_mode_by_phy (dev->of_node,-1 )) { +case USB_DR_MODE_PERIPHERAL : + priv->mode =PHY_MODE_USB_DEVICE ; +break ; +case USB_DR_MODE_OTG : + priv->mode =PHY_MODE_USB_OTG ; +break ; +case USB_DR_MODE_HOST : +default : + priv->mode =PHY_MODE_USB_HOST ; +break ; + } + + priv->regmap =devm_regmap_init_mmio (dev, base, + &phy_meson_gxl_usb2_regmap_conf); +if (IS_ERR (priv->regmap)) +return PTR_ERR (priv->regmap); + + phy =devm_phy_create (dev,NULL , &phy_meson_gxl_usb2_ops); +if (IS_ERR (phy)) { +dev_err (dev,"failed to create PHY\n" ); +return PTR_ERR (phy); + } + +phy_set_drvdata (phy, priv); + + phy_provider =devm_of_phy_provider_register (dev, of_phy_simple_xlate); + +return PTR_ERR_OR_ZERO (phy_provider); +} + +static const struct of_device_id phy_meson_gxl_usb2_of_match[] = { + { .compatible ="amlogic,meson-gxl-usb2-phy" , }, + { }, +}; +MODULE_DEVICE_TABLE (of, phy_meson_gxl_usb2_of_match); + +static struct platform_driver phy_meson_gxl_usb2_driver = { + .probe = phy_meson_gxl_usb2_probe, + .driver = { + .name ="phy-meson-gxl-usb2" , + .of_match_table = phy_meson_gxl_usb2_of_match, + }, +}; +module_platform_driver (phy_meson_gxl_usb2_driver); + +MODULE_AUTHOR ("Martin Blumenstingl <[email protected]>" ); +MODULE_DESCRIPTION ("Meson GXL and GXM USB2 PHY driver" ); +MODULE_LICENSE ("GPL v2" );Signature · 7 lines
2.12.0 _______________________________________________ linux-amlogic mailing list linux-amlogic at lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic
PATCH 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
In reply to Martin BlumenstinglHi,
Quoted 184 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for any of these PHYs. Both drivers were written by reading the reference drivers provided by Amlogic and analyzing the registers on the kernel that was shipped on the boards I have.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 13 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 263 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +13
-0@@ -486,4 +486,17 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + endmenudrivers/phy/Makefile +1
-0@@ -59,3 +59,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.odrivers/phy/phy-meson-gxl-usb2.c new file +128
-0@@ -0,0 +1,263 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/usb/of.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,
drivers/phy/phy-meson-gxl-usb2.c line 138
Quoted 10 lines
drivers/phy/phy-meson-gxl-usb2.c new file +10
-0+ 0); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +if (priv->is_enabled) {
Should set_mode be always called after power_on? or reset of phy should be done if set_mode is called after power_on?
Either case I think it's better to move this reset in phy reset ops and invoke it from this phys users.
Thanks
Kishon
Martin Blumenstingl
reviewerPATCH 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Hi Kishon,
Quoted 201 lines · Kishon Vijay Abraham I
Hi,
Quoted 184 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for any of these PHYs. Both drivers were written by reading the reference drivers provided by Amlogic and analyzing the registers on the kernel that was shipped on the boards I have.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 13 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 263 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +13
-0@@ -486,4 +486,17 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + endmenudrivers/phy/Makefile +1
-0@@ -59,3 +59,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.odrivers/phy/phy-meson-gxl-usb2.c new file +128
-0@@ -0,0 +1,263 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/usb/of.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,drivers/phy/phy-meson-gxl-usb2.c line 138
Quoted 10 lines
drivers/phy/phy-meson-gxl-usb2.c new file +10
-0+ 0); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +if (priv->is_enabled) {Should
set_modebe always called afterpower_on? or reset of phy should be done ifset_modeis called afterpower_on?
Quoted 2 lines
Either case I think it's better to move this reset in phy reset ops and invoke it from this phys users.
unfortunately I can only guess (change code -> boot kernel with changed code -> human testing) here as there's no public datasheet. however, the "consumer" of this PHY will be quite generic: it'll be powered on by the xhci-plat driver (or some utility around that). that might be a bit of a problem: it would mean that we have to decide when to call phy_reset (before or after phy_power_on/phy_set_mode) and define this once for all PHYs that are passed to xhci-plat. what do you think Kishon?
apart from that Hendrik is right, but I think I should call phy_meson_gxl_usb2_power_off instead of stetting is_enabled to false. thanks for spotting this though!
Regards,
Martin
PATCH 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Hi,
Quoted 206 lines · Martin Blumenstingl
Hi Kishon,
Quoted 201 lines · Kishon Vijay Abraham I
Hi,
Quoted 184 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for any of these PHYs. Both drivers were written by reading the reference drivers provided by Amlogic and analyzing the registers on the kernel that was shipped on the boards I have.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 13 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 263 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +13
-0@@ -486,4 +486,17 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + endmenudrivers/phy/Makefile +1
-0@@ -59,3 +59,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.odrivers/phy/phy-meson-gxl-usb2.c new file +128
-0@@ -0,0 +1,263 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/usb/of.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); + regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,drivers/phy/phy-meson-gxl-usb2.c line 138
Quoted 10 lines
drivers/phy/phy-meson-gxl-usb2.c new file +10
-0+ 0); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +if (priv->is_enabled) {Should
set_modebe always called afterpower_on? or reset of phy should be done ifset_modeis called afterpower_on?Quoted 2 lines
Either case I think it's better to move this reset in phy reset ops and invoke it from this phys users.
Quoted 8 lines
unfortunately I can only guess (change code -> boot kernel with changed code -> human testing) here as there's no public datasheet. however, the "consumer" of this PHY will be quite generic: it'll be powered on by the xhci-plat driver (or some utility around that). that might be a bit of a problem: it would mean that we have to decide when to call
phy_reset(before or after phy_power_on/phy_set_mode) and define this once for all PHYs that are passed to xhci-plat. what do you think Kishon?
I would have preferred to call phy_reset. But since it has to be called from xhci-plat which might affect other platforms too, I would prefer not to cause any regressions. So that's fine.
Thanks
Kishon
Martin Blumenstingl
reviewerv2 cover Meson GXL USB2 PHY driver
In reply to Martin BlumenstinglThis series adds a driver for the USB2 PHYs found in Amlogic Meson GXL (and GXM) SoCs.
Devicetree changes are intentionally missing in this series because of various other problems that need to be resolved before we get USB host support working.
As usual we unfortunately don't have any documentation available. The register definitions were taken from the vendor's GPL kernel sources (see [5] if you are really interested). Translation to human readable names is done using the "best effort" algorithm.
The USB situation on GXL and GXM is a bit special:
the SoCs include both, a dwc3 and a dwc2 controller. The dwc3 controller IP only supports host-mode, while the dwc2 controller IP only supports device mode.
The dwc3 controller has all USB3 ports disabled. GXL has two USB2 ports enabled on dwc3's internal hub, while GXM has three USB2 ports enabled. This makes the initialization a bit special: to enable any of the dwc3 controller's USB2 ports *ALL* PHYs have to be initialized (probably due to the hub's routing logic).
The first USB2 PHY (hardware-wise) also supports OTG mode. The vendor kernel implements this through the USB3 PHY by re-routing the first USB2 PHY from the dwc3 controller to the dwc2 controller (which is disabled by default, but if the USB3 PHY detects that the port should enter device mode it enables the dwc2 controller).
To get USB host mode working the following steps are needed:
- xhci-plat must be able to manage more than one PHY for a controller, this is work-in-progress, see [0]
- there are some DMA handling issues in dwc3 and the rest of the USB stack, this is solved by the "sysdev" patches from [1]
- adding all USB related bits to meson-gxl.dtsi - this is work in progress but depends on the previous TODOs, see [2] and [3]
This supersedes my previous series "Meson GXL and GXM USB support" [4].
Changes since v1:
- rebased to the next branch of Kishon's linux-phy tree (currently at fe0134d071 "phy: phy-exynos-pcie: make it explicitly non-modular")
- added a missing call to phy_meson_gxl_usb2_power_off in the error case in phy_meson_gxl_usb2_power_on - thanks to Hendrik v. Raven for spotting this!
- moved the reset logic into a separate function and expose it through phy_ops.reset so it can be used by consumers of this PHY. phy_meson_gxl_usb2_set_mode still resets the PHY directly because this PHY will be configured by xhci-plat (from which we cannot call phy_reset() - see the discussion based on v1 of this patch: [6])
- added Rob Herring's ACK to patch #1 (the dt-binding documentation)
[0] https://www.spinics.net/lists/linux-usb/msg151837.html
[1] http://www.mail-archive.com/linux-usb at vger.kernel.org/msg87077.html
[2] https://github.com/xdarklight/linux/commit/e2b83785687fe859ae4bba8da8bb2fb2d7e32bfb
[3] https://github.com/xdarklight/linux/commit/203ab9ea5d1bea0bf066b6738010c8072b821d87
[4] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/001721.html
[5] https://github.com/khadas/linux/blob/76fd19ac41bb774e396ce8009ff665f29c26c535/include/linux/amlogic/usb-gxl.h
[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-March/002777.html
Martin Blumenstingl (2):
Documentation: dt-bindings: Add documentation for the Meson GXL USB2
PHY
phy: meson: add USB2 PHY support for Meson GXL and GXM
.../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 ++ drivers/phy/Kconfig | 14 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 273 +++++++++++++++++++++ 4 files changed, 305 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt create mode 100644 drivers/phy/phy-meson-gxl-usb2.c
Signature · 1 line
2.12.0
Martin Blumenstingl
reviewerPATCH v2 1/2 Documentation: dt-bindings: Add documentation for the Meson GXL USB2 PHY
This adds the DT binding documentation for the USB2 PHY(s) found in the Meson GXL and GXM SoCs.
--- .../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt new file +17 -0
@@ -0,0 +1,17 @@ +* Amlogic Meson GXL and GXM USB2 PHY binding + +Required properties: +- compatible: Should be "amlogic,meson-gxl-usb2-phy" +- reg: The base address and length of the registers +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) + +Optional properties: +- phy-supply: see phy-bindings.txt in this directory + + +Example: + usb2_phy0: phy at 78000 { + compatible = "amlogic,meson-gxl-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0x78000 0x0 0x20>; + };
Signature · 1 line
2.12.0
Martin Blumenstingl
reviewerPATCH v2 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
In reply to Martin BlumenstinglThis adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
--- drivers/phy/Kconfig | 14 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 273 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.c
drivers/phy/Kconfig +14 -0
@@ -510,6 +510,19 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + config PHY_NSP_USB3 tristate "Broadcom NorthStar plus USB3 PHY driver" depends on OF && (ARCH_BCM_NSP || COMPILE_TEST)
@@ -518,4 +531,5 @@ config PHY_NSP_USB3 help Enable this to support the Broadcom Northstar plus USB3 PHY. If unsure, say N. + endmenu
drivers/phy/Makefile +1 -0
@@ -62,4 +62,5 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.o obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.o
drivers/phy/phy-meson-gxl-usb2.c new file +273 -0
273 lines not on this page · raw message
Signature · 1 line
2.12.0
Martin Blumenstingl
reviewerPATCH v2 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Hi Kishon,
Quoted 10 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
gentle ping - did you have time to review this patch in v2 yet?
Quoted 330 lines
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 14 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 273 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +14
-0@@ -510,6 +510,19 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + config PHY_NSP_USB3 tristate "Broadcom NorthStar plus USB3 PHY driver" depends on OF && (ARCH_BCM_NSP || COMPILE_TEST)@@ -518,4 +531,5 @@ config PHY_NSP_USB3 help Enable this to support the Broadcom Northstar plus USB3 PHY. If unsure, say N. + endmenudrivers/phy/Makefile +1
-0@@ -62,4 +62,5 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.o obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.odrivers/phy/phy-meson-gxl-usb2.c new file +273
-1@@ -0,0 +1,273 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/usb/of.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_reset (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +if (priv->is_enabled) { +/* reset the PHY and wait until settings are stabilized */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); +udelay (RESET_COMPLETE_TIME ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +0 ); +udelay (RESET_COMPLETE_TIME ); + } + +return 0 ; +} + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +phy_meson_gxl_usb2_reset (phy); + + priv->mode = mode; + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_off (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + + priv->is_enabled =0 ; + +/* power off the PHY by putting it into reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_on (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); +int ret; + + priv->is_enabled =1 ; + +/* power on the PHY by taking it out of reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); + + ret =phy_meson_gxl_usb2_set_mode (phy, priv->mode); +if (ret) { +phy_meson_gxl_usb2_power_off (phy); + +dev_err (&phy->dev,"Failed to initialize PHY with mode %d\n" , + priv->mode); +return ret; + } + +return 0 ; +} + +static const struct phy_ops phy_meson_gxl_usb2_ops = { + .power_on = phy_meson_gxl_usb2_power_on, + .power_off = phy_meson_gxl_usb2_power_off, + .set_mode = phy_meson_gxl_usb2_set_mode, + .reset = phy_meson_gxl_usb2_reset, + .owner =THIS_MODULE , +}; + +static int phy_meson_gxl_usb2_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +struct phy_provider *phy_provider; +struct resource *res; +struct phy_meson_gxl_usb2_priv *priv; +struct phy *phy; +void __iomem *base; + + priv =devm_kzalloc (dev,sizeof (*priv),GFP_KERNEL ); +if (!priv) +return -ENOMEM ; + +platform_set_drvdata (pdev, priv); + + res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); + base =devm_ioremap_resource (dev, res); +if (IS_ERR (base)) +return PTR_ERR (base); + +switch (of_usb_get_dr_mode_by_phy (dev->of_node,-1 )) { +case USB_DR_MODE_PERIPHERAL : + priv->mode =PHY_MODE_USB_DEVICE ; +break ; +case USB_DR_MODE_OTG : + priv->mode =PHY_MODE_USB_OTG ; +break ; +case USB_DR_MODE_HOST : +default : + priv->mode =PHY_MODE_USB_HOST ; +break ; + } + + priv->regmap =devm_regmap_init_mmio (dev, base, + &phy_meson_gxl_usb2_regmap_conf); +if (IS_ERR (priv->regmap)) +return PTR_ERR (priv->regmap); + + phy =devm_phy_create (dev,NULL , &phy_meson_gxl_usb2_ops); +if (IS_ERR (phy)) { +dev_err (dev,"failed to create PHY\n" ); +return PTR_ERR (phy); + } + +phy_set_drvdata (phy, priv); + + phy_provider =devm_of_phy_provider_register (dev, of_phy_simple_xlate); + +return PTR_ERR_OR_ZERO (phy_provider); +} + +static const struct of_device_id phy_meson_gxl_usb2_of_match[] = { + { .compatible ="amlogic,meson-gxl-usb2-phy" , }, + { }, +}; +MODULE_DEVICE_TABLE (of, phy_meson_gxl_usb2_of_match); + +static struct platform_driver phy_meson_gxl_usb2_driver = { + .probe = phy_meson_gxl_usb2_probe, + .driver = { + .name ="phy-meson-gxl-usb2" , + .of_match_table = phy_meson_gxl_usb2_of_match, + }, +}; +module_platform_driver (phy_meson_gxl_usb2_driver); + +MODULE_AUTHOR ("Martin Blumenstingl <[email protected]>" ); +MODULE_DESCRIPTION ("Meson GXL and GXM USB2 PHY driver" ); +MODULE_LICENSE ("GPL v2" ); --2.12.0
PATCH v2 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Hi,
Quoted 7 lines · Martin Blumenstingl
Hi Kishon,
Quoted 3 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
Quoted 8 lines
Quoted 7 lines
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
gentle ping - did you have time to review this patch in v2 yet?
Have a few comments, see below..
Quoted 30 lines
Quoted 30 lines
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 14 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 273 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +13
-0@@ -510,6 +510,19 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. +
Quoted 8 lines
drivers/phy/Kconfig config PHY_NSP_USB3 · line 534
Quoted 8 lines
drivers/phy/Kconfig +1
-0config PHY_NSP_USB3 tristate "Broadcom NorthStar plus USB3 PHY driver" depends on OF && (ARCH_BCM_NSP || COMPILE_TEST)@@ -518,4 +531,5 @@ config PHY_NSP_USB3 help Enable this to support the Broadcom Northstar plus USB3 PHY. If unsure, say N. +
spurious space..
Quoted 132 lines
Quoted 132 lines
drivers/phy/Kconfig +0
-0endmenudrivers/phy/Makefile +1
-0@@ -62,4 +62,5 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.o obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.odrivers/phy/phy-meson-gxl-usb2.c new file +115
-0@@ -0,0 +1,273 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/usb/of.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_reset (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +if (priv->is_enabled) {
Quoted 8 lines
drivers/phy/phy-meson-gxl-usb2.c line 123
Quoted 8 lines
drivers/phy/phy-meson-gxl-usb2.c new file +8
-0+/* reset the PHY and wait until settings are stabilized */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); +udelay (RESET_COMPLETE_TIME ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +0 ); +udelay (RESET_COMPLETE_TIME ); + }
Instead of having big if condition blocks, it could be
if (!priv->is_enabled) return 0 the configuration when priv->is_enabled is true should go here.
Quoted 54 lines
Quoted 54 lines
drivers/phy/phy-meson-gxl-usb2.c new file +54
-0+ +return 0 ; +} + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +phy_meson_gxl_usb2_reset (phy); + + priv->mode = mode; + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_off (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + + priv->is_enabled =0 ; + +/* power off the PHY by putting it into reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_on (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy);
Quoted 8 lines
drivers/phy/phy-meson-gxl-usb2.c line 185
Quoted 8 lines
drivers/phy/phy-meson-gxl-usb2.c new file +8
-0+int ret; + + priv->is_enabled =1 ; + +/* power on the PHY by taking it out of reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); + + ret =phy_meson_gxl_usb2_set_mode (phy, priv->mode);
Since this is already part of phy_ops, the consumer of this phy will take care of setting the mode right?
Quoted 2 lines
drivers/phy/phy-meson-gxl-usb2.c line 187
Quoted 2 lines
drivers/phy/phy-meson-gxl-usb2.c new file +2
-0+if (ret) { +phy_meson_gxl_usb2_power_off (phy);
This would mess up the reference count in phy_core, since this function is also part of the phy_ops. The consumer should be responsible for powering off the phy.
Thanks
Kishon
Martin Blumenstingl
reviewerPATCH v2 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Hi Kishon,
Quoted 13 lines · Kishon Vijay Abraham I
Hi,
Quoted 10 lines · Martin Blumenstingl
Hi Kishon,
Quoted 6 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Quoted 7 lines
Quoted 5 lines
Quoted 4 lines
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
gentle ping - did you have time to review this patch in v2 yet?
Have a few comments, see below..
thanks for taking the time to review this!
Quoted 32 lines
Quoted 32 lines
Quoted 32 lines
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 14 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 273 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +13
-0@@ -510,6 +510,19 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + config PHY_NSP_USB3 tristate "Broadcom NorthStar plus USB3 PHY driver"
Quoted 8 lines
Quoted 6 lines
drivers/phy/Kconfig config PHY_NSP_USB3 · line 534
Quoted 6 lines
drivers/phy/Kconfig +1
-0depends on OF && (ARCH_BCM_NSP || COMPILE_TEST)@@ -518,4 +531,5 @@ config PHY_NSP_USB3 help Enable this to support the Broadcom Northstar plus USB3 PHY. If unsure, say N. +spurious space..
you're right, this shouldn't be here. I'll fix this in the next version
Quoted 142 lines
Quoted 132 lines
Quoted 132 lines
drivers/phy/Kconfig +0
-0endmenudrivers/phy/Makefile +1
-0@@ -62,4 +62,5 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.o obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.odrivers/phy/phy-meson-gxl-usb2.c new file +115
-0@@ -0,0 +1,273 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/usb/of.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_reset (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +if (priv->is_enabled) {Quoted 8 lines
drivers/phy/phy-meson-gxl-usb2.c line 123
Quoted 8 lines
drivers/phy/phy-meson-gxl-usb2.c new file +8
-0+/* reset the PHY and wait until settings are stabilized */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); +udelay (RESET_COMPLETE_TIME ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +0 ); +udelay (RESET_COMPLETE_TIME ); + }Instead of having big if condition blocks, it could be
Quoted 4 lines
if (!priv->is_enabled)
return 0
the configuration when priv->is_enabled is true should go here.makes sense (and the code easier to read) in this case - I'll fix it in the next version
Quoted 57 lines
Quoted 57 lines
Quoted 57 lines
drivers/phy/phy-meson-gxl-usb2.c new file +57
-0+ +return 0 ; +} + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +phy_meson_gxl_usb2_reset (phy); + + priv->mode = mode; + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_off (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + + priv->is_enabled =0 ; + +/* power off the PHY by putting it into reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_on (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); +int ret; + + priv->is_enabled =1 ;
Quoted 8 lines
Quoted 5 lines
drivers/phy/phy-meson-gxl-usb2.c line 185
Quoted 5 lines
drivers/phy/phy-meson-gxl-usb2.c new file +5
-0+ +/* power on the PHY by taking it out of reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); + + ret =phy_meson_gxl_usb2_set_mode (phy, priv->mode);Since this is already part of
phy_ops, the consumer of this phy will take care of setting the mode right?
many USB PHYs are configured through of_usb_get_dr_mode_by_phy() (which fetches the USB controller DT node and looks up the dr_mode property). this means that the driver will even work for controller which did not call phy_set_mode() (currently dwc2 and dwc3 are an example where phy_set_mode() is not called, and this driver is probably going to be used by both). are you fine with keeping this or should we instead investigate why dwc2 and dwc3 are not calling phy_set_mode yet?
Quoted 5 lines
Quoted 2 lines
drivers/phy/phy-meson-gxl-usb2.c line 187
Quoted 2 lines
drivers/phy/phy-meson-gxl-usb2.c new file +2
-0+if (ret) { +phy_meson_gxl_usb2_power_off (phy);This would mess up the reference count in
phy_core, since this function is also part of thephy_ops. The consumer should be responsible for powering off the phy.
actually it shouldn't. it would cause issues if I used phy_power_off(phy) here, but I'm using the driver-internal callback here.
if phy_meson_gxl_usb2_power_on() fails then phy_power_on() (from phy-core) prints a warnings and does not increment the internal ref-counter (++phy->power_count).
so in my opinion there shouldn't be a problem
could you please have a look at my replies for issue #3 and #4 (both affecting phy_meson_gxl_usb2_power_on) and let me know what you think?
Regards,
Martin
PATCH v2 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Hi,
Quoted 281 lines · Martin Blumenstingl
Hi Kishon,
Quoted 13 lines · Kishon Vijay Abraham I
Hi,
Quoted 10 lines · Martin Blumenstingl
Hi Kishon,
Quoted 6 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Quoted 7 lines
Quoted 5 lines
Quoted 4 lines
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
gentle ping - did you have time to review this patch in v2 yet?
Have a few comments, see below..
thanks for taking the time to review this!
Quoted 32 lines
Quoted 32 lines
Quoted 32 lines
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 14 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 273 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +13
-0@@ -510,6 +510,19 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + config PHY_NSP_USB3 tristate "Broadcom NorthStar plus USB3 PHY driver"Quoted 8 lines
Quoted 6 lines
drivers/phy/Kconfig config PHY_NSP_USB3 · line 534
Quoted 6 lines
drivers/phy/Kconfig +1
-0depends on OF && (ARCH_BCM_NSP || COMPILE_TEST)@@ -518,4 +531,5 @@ config PHY_NSP_USB3 help Enable this to support the Broadcom Northstar plus USB3 PHY. If unsure, say N. +spurious space..
you're right, this shouldn't be here. I'll fix this in the next version
Quoted 142 lines
Quoted 132 lines
Quoted 132 lines
drivers/phy/Kconfig +0
-0endmenudrivers/phy/Makefile +1
-0@@ -62,4 +62,5 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.o obj-$(CONFIG_PHY_NSP_USB3) += phy-bcm-nsp-usb3.odrivers/phy/phy-meson-gxl-usb2.c new file +115
-0@@ -0,0 +1,273 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/usb/of.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_reset (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +if (priv->is_enabled) {Quoted 8 lines
drivers/phy/phy-meson-gxl-usb2.c line 123
Quoted 8 lines
drivers/phy/phy-meson-gxl-usb2.c new file +8
-0+/* reset the PHY and wait until settings are stabilized */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); +udelay (RESET_COMPLETE_TIME ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +0 ); +udelay (RESET_COMPLETE_TIME ); + }Instead of having big if condition blocks, it could be
Quoted 4 lines
if (!priv->is_enabled) return 0 the configuration when priv->is_enabled is true should go here.makes sense (and the code easier to read) in this case - I'll fix it in the next version
Quoted 57 lines
Quoted 57 lines
Quoted 57 lines
drivers/phy/phy-meson-gxl-usb2.c new file +57
-0+ +return 0 ; +} + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +phy_meson_gxl_usb2_reset (phy); + + priv->mode = mode; + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_off (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + + priv->is_enabled =0 ; + +/* power off the PHY by putting it into reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_on (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); +int ret; + + priv->is_enabled =1 ;Quoted 8 lines
Quoted 5 lines
drivers/phy/phy-meson-gxl-usb2.c line 185
Quoted 5 lines
drivers/phy/phy-meson-gxl-usb2.c new file +5
-0+ +/* power on the PHY by taking it out of reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); + + ret =phy_meson_gxl_usb2_set_mode (phy, priv->mode);Since this is already part of
phy_ops, the consumer of this phy will take care of setting the mode right?
Quoted 8 lines
many USB PHYs are configured through
of_usb_get_dr_mode_by_phy()(which fetches the USB controller DT node and looks up thedr_modeproperty). this means that the driver will even work for controller which did not callphy_set_mode()(currently dwc2 and dwc3 are an example wherephy_set_mode()is not called, and this driver is probably going to be used by both). are you fine with keeping this or should we instead investigate why dwc2 and dwc3 are not callingphy_set_modeyet?
If the driver want to set_mode of the phy, then it should be fine. But let's remove .set_mode from phy_ops. Either the driver should set the mode by itself or allow the consumers to set the mode but not both.
Quoted 9 lines
Quoted 6 lines
Quoted 3 lines
drivers/phy/phy-meson-gxl-usb2.c line 187
Quoted 3 lines
drivers/phy/phy-meson-gxl-usb2.c new file +2
-0+if (ret) { +phy_meson_gxl_usb2_power_off (phy);This would mess up the reference count in
phy_core, since this function is also part of thephy_ops. The consumer should be responsible for powering off the phy.actually it shouldn't. it would cause issues if I used
phy_power_off(phy)here, but I'm using the driver-internal callback here.
I didn't mean you should use phy_power_off(). I meant powering on the phy or powering off the phy should be controlled by the consumer.
Quoted 4 lines
if
phy_meson_gxl_usb2_power_on()fails thenphy_power_on()(from phy-core) prints a warnings and does not increment the internal ref-counter (++phy->power_count).
so in my opinion there shouldn't be a problem
That makes sense.
Thanks
Kishon
Martin Blumenstingl
reviewerv3 cover Meson GXL USB2 PHY driver
In reply to Martin BlumenstinglThis series adds a driver for the USB2 PHYs found in Amlogic Meson GXL (and GXM) SoCs.
Devicetree changes are intentionally missing in this series because of various other problems that need to be resolved before we get USB host support working.
As usual we unfortunately don't have any documentation available. The register definitions were taken from the vendor's GPL kernel sources (see [5] if you are really interested). Translation to human readable names is done using the "best effort" algorithm.
The USB situation on GXL and GXM is a bit special:
the SoCs include both, a dwc3 and a dwc2 controller. The dwc3 controller IP only supports host-mode, while the dwc2 controller IP only supports device mode.
The dwc3 controller has all USB3 ports disabled. GXL has two USB2 ports enabled on dwc3's internal hub, while GXM has three USB2 ports enabled. This makes the initialization a bit special: to enable any of the dwc3 controller's USB2 ports *ALL* PHYs have to be initialized (probably due to the hub's routing logic).
The first USB2 PHY (hardware-wise) also supports OTG mode. The vendor kernel implements this through the USB3 PHY by re-routing the first USB2 PHY from the dwc3 controller to the dwc2 controller (which is disabled by default, but if the USB3 PHY detects that the port should enter device mode it enables the dwc2 controller).
To get USB host mode working the following steps are needed:
- xhci-plat must be able to manage more than one PHY for a controller, this is work-in-progress, see [0]
- there are some DMA handling issues in dwc3 and the rest of the USB stack, this is solved by the "sysdev" patches from [1]
- adding all USB related bits to meson-gxl.dtsi - this is work in progress but depends on the previous TODOs, see [2] and [3]
This supersedes my previous series "Meson GXL and GXM USB support" [4].
Changes since v2:
- removed PHY mode parsing from phy_meson_gxl_usb2_probe (based on of_usb_get_dr_mode_by_phy()) because this will not work with the xhci-plat changes anyways. The driver now simply defaults to host mode until a consumer uses phy_set_mode().
- fixed a stray newline in drivers/phy/Kconfig b/drivers/phy/Kconfig (thanks for spotting this Kishon)
- simplified phy_meson_gxl_usb2_reset() by returning early (thanks Kishon for suggesting this improvement)
Changes since v1:
- rebased to the next branch of Kishon's linux-phy tree (currently at fe0134d071 "phy: phy-exynos-pcie: make it explicitly non-modular")
- added a missing call to phy_meson_gxl_usb2_power_off in the error case in phy_meson_gxl_usb2_power_on - thanks to Hendrik v. Raven for spotting this!
- moved the reset logic into a separate function and expose it through phy_ops.reset so it can be used by consumers of this PHY. phy_meson_gxl_usb2_set_mode still resets the PHY directly because this PHY will be configured by xhci-plat (from which we cannot call phy_reset() - see the discussion based on v1 of this patch: [6])
- added Rob Herring's ACK to patch #1 (the dt-binding documentation)
[0] https://www.spinics.net/lists/linux-usb/msg151837.html
[1] http://www.mail-archive.com/linux-usb at vger.kernel.org/msg87077.html
[2] https://github.com/xdarklight/linux/commit/e2b83785687fe859ae4bba8da8bb2fb2d7e32bfb
[3] https://github.com/xdarklight/linux/commit/203ab9ea5d1bea0bf066b6738010c8072b821d87
[4] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/001721.html
[5] https://github.com/khadas/linux/blob/76fd19ac41bb774e396ce8009ff665f29c26c535/include/linux/amlogic/usb-gxl.h
[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-March/002777.html
Martin Blumenstingl (2):
Documentation: dt-bindings: Add documentation for the Meson GXL USB2
PHY
phy: meson: add USB2 PHY support for Meson GXL and GXM
.../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 ++ drivers/phy/Kconfig | 12 + drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 261 +++++++++++++++++++++ 4 files changed, 291 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt create mode 100644 drivers/phy/phy-meson-gxl-usb2.c
Signature · 1 line
2.12.2
Martin Blumenstingl
reviewerPATCH v3 1/2 Documentation: dt-bindings: Add documentation for the Meson GXL USB2 PHY
This adds the DT binding documentation for the USB2 PHY(s) found in the Meson GXL and GXM SoCs.
--- .../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt new file +17 -0
@@ -0,0 +1,17 @@ +* Amlogic Meson GXL and GXM USB2 PHY binding + +Required properties: +- compatible: Should be "amlogic,meson-gxl-usb2-phy" +- reg: The base address and length of the registers +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) + +Optional properties: +- phy-supply: see phy-bindings.txt in this directory + + +Example: + usb2_phy0: phy at 78000 { + compatible = "amlogic,meson-gxl-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0x78000 0x0 0x20>; + };
Signature · 1 line
2.12.2
Martin Blumenstingl
reviewerPATCH v3 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
In reply to Martin BlumenstinglThis adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
--- drivers/phy/Kconfig | 12 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 261 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 274 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.c
drivers/phy/Kconfig +12 -0
@@ -511,4 +511,16 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + endmenu
drivers/phy/Makefile +1 -0
@@ -62,3 +62,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.o
drivers/phy/phy-meson-gxl-usb2.c new file +261 -0
261 lines not on this page · raw message
Signature · 1 line
2.12.2
Martin Blumenstingl
reviewerPATCH v3 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Hi Kishon,
Quoted 317 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 12 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 261 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 274 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +12
-0@@ -511,4 +511,16 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + endmenudrivers/phy/Makefile +1
-0@@ -62,3 +62,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.odrivers/phy/phy-meson-gxl-usb2.c new file +261
-1@@ -0,0 +1,261 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_reset (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +if (!priv->is_enabled) +return 0 ; + +/* reset the PHY and wait until settings are stabilized */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); +udelay (RESET_COMPLETE_TIME ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); +udelay (RESET_COMPLETE_TIME ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +phy_meson_gxl_usb2_reset (phy); + + priv->mode = mode; + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_off (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + + priv->is_enabled =0 ; + +/* power off the PHY by putting it into reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_on (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); +int ret; + + priv->is_enabled =1 ; + +/* power on the PHY by taking it out of reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); + + ret =phy_meson_gxl_usb2_set_mode (phy, priv->mode); +if (ret) { +phy_meson_gxl_usb2_power_off (phy); + +dev_err (&phy->dev,"Failed to initialize PHY with mode %d\n" , + priv->mode); +return ret; + } + +return 0 ; +} + +static const struct phy_ops phy_meson_gxl_usb2_ops = { + .power_on = phy_meson_gxl_usb2_power_on, + .power_off = phy_meson_gxl_usb2_power_off, + .set_mode = phy_meson_gxl_usb2_set_mode, + .reset = phy_meson_gxl_usb2_reset, + .owner =THIS_MODULE , +}; + +static int phy_meson_gxl_usb2_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +struct phy_provider *phy_provider; +struct resource *res; +struct phy_meson_gxl_usb2_priv *priv; +struct phy *phy; +void __iomem *base; + + priv =devm_kzalloc (dev,sizeof (*priv),GFP_KERNEL ); +if (!priv) +return -ENOMEM ; + +platform_set_drvdata (pdev, priv); + + res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); + base =devm_ioremap_resource (dev, res); +if (IS_ERR (base)) +return PTR_ERR (base); + + priv->mode =PHY_MODE_USB_HOST ; + + priv->regmap =devm_regmap_init_mmio (dev, base, + &phy_meson_gxl_usb2_regmap_conf); +if (IS_ERR (priv->regmap)) +return PTR_ERR (priv->regmap); + + phy =devm_phy_create (dev,NULL , &phy_meson_gxl_usb2_ops); +if (IS_ERR (phy)) { +dev_err (dev,"failed to create PHY\n" ); +return PTR_ERR (phy); + } + +phy_set_drvdata (phy, priv); + + phy_provider =devm_of_phy_provider_register (dev, of_phy_simple_xlate); + +return PTR_ERR_OR_ZERO (phy_provider); +} + +static const struct of_device_id phy_meson_gxl_usb2_of_match[] = { + { .compatible ="amlogic,meson-gxl-usb2-phy" , }, + { }, +}; +MODULE_DEVICE_TABLE (of, phy_meson_gxl_usb2_of_match); + +static struct platform_driver phy_meson_gxl_usb2_driver = { + .probe = phy_meson_gxl_usb2_probe, + .driver = { + .name ="phy-meson-gxl-usb2" , + .of_match_table = phy_meson_gxl_usb2_of_match, + }, +}; +module_platform_driver (phy_meson_gxl_usb2_driver); + +MODULE_AUTHOR ("Martin Blumenstingl <[email protected]>" ); +MODULE_DESCRIPTION ("Meson GXL and GXM USB2 PHY driver" ); +MODULE_LICENSE ("GPL v2" ); --
Quoted 2 lines
2.12.2
the devicetree documentation already got Rob's ACK. is there anything that I still need to fix? I would really like to see this getting into 4.13
PATCH v3 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Hi,
Quoted 318 lines · Martin Blumenstingl
Hi Kishon,
Quoted 314 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 12 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 261 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 274 insertions(+) create mode 100644 drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +12
-0@@ -511,4 +511,16 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + endmenudrivers/phy/Makefile +1
-0@@ -62,3 +62,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.odrivers/phy/phy-meson-gxl-usb2.c new file +259
-0@@ -0,0 +1,261 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_reset (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +if (!priv->is_enabled) +return 0 ; + +/* reset the PHY and wait until settings are stabilized */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); +udelay (RESET_COMPLETE_TIME ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); +udelay (RESET_COMPLETE_TIME ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +phy_meson_gxl_usb2_reset (phy); + + priv->mode = mode; + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_off (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + + priv->is_enabled =0 ; + +/* power off the PHY by putting it into reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_on (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); +int ret; + + priv->is_enabled =1 ; + +/* power on the PHY by taking it out of reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); + + ret =phy_meson_gxl_usb2_set_mode (phy, priv->mode); +if (ret) { +phy_meson_gxl_usb2_power_off (phy); + +dev_err (&phy->dev,"Failed to initialize PHY with mode %d\n" , + priv->mode); +return ret; + } + +return 0 ; +} + +static const struct phy_ops phy_meson_gxl_usb2_ops = { + .power_on = phy_meson_gxl_usb2_power_on, + .power_off = phy_meson_gxl_usb2_power_off, + .set_mode = phy_meson_gxl_usb2_set_mode, + .reset = phy_meson_gxl_usb2_reset, + .owner =THIS_MODULE , +}; + +static int phy_meson_gxl_usb2_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +struct phy_provider *phy_provider; +struct resource *res; +struct phy_meson_gxl_usb2_priv *priv; +struct phy *phy; +void __iomem *base; + + priv =devm_kzalloc (dev,sizeof (*priv),GFP_KERNEL ); +if (!priv) +return -ENOMEM ; + +platform_set_drvdata (pdev, priv); + + res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); + base =devm_ioremap_resource (dev, res); +if (IS_ERR (base)) +return PTR_ERR (base); + + priv->mode =PHY_MODE_USB_HOST ; + + priv->regmap =devm_regmap_init_mmio (dev, base, + &phy_meson_gxl_usb2_regmap_conf); +if (IS_ERR (priv->regmap)) +return PTR_ERR (priv->regmap); + + phy =devm_phy_create (dev,NULL , &phy_meson_gxl_usb2_ops); +if (IS_ERR (phy)) { +dev_err (dev,"failed to create PHY\n" ); +return PTR_ERR (phy); + } + +phy_set_drvdata (phy, priv); + + phy_provider =devm_of_phy_provider_register (dev, of_phy_simple_xlate); + +return PTR_ERR_OR_ZERO (phy_provider); +} + +static const struct of_device_id phy_meson_gxl_usb2_of_match[] = { + { .compatible ="amlogic,meson-gxl-usb2-phy" , }, + { }, +}; +MODULE_DEVICE_TABLE (of, phy_meson_gxl_usb2_of_match); + +static struct platform_driver phy_meson_gxl_usb2_driver = { + .probe = phy_meson_gxl_usb2_probe, + .driver = { + .name ="phy-meson-gxl-usb2" , + .of_match_table = phy_meson_gxl_usb2_of_match, + }, +}; +module_platform_driver (phy_meson_gxl_usb2_driver); + +MODULE_AUTHOR ("Martin Blumenstingl <[email protected]>" );
Quoted 8 lines
Quoted 5 lines
drivers/phy/phy-meson-gxl-usb2.c new file +2
-1+MODULE_DESCRIPTION ("Meson GXL and GXM USB2 PHY driver" ); +MODULE_LICENSE ("GPL v2" ); --2.12.2
the devicetree documentation already got Rob's ACK. is there anything that I still need to fix? I would really like to see this getting into 4.13
I don't have any further comments. I'll queue this once -rc1 is tagged. Btw Vivek Gautam has plans to change the directory structure of phy, so you might have to resend this patch once his patch is merged.
Vivek, since phy tree is already merged to Linus, can you send your restructuring patch asap based on linus latest?
Thanks
Kishon
PATCH v3 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Hi,
Quoted 329 lines · Kishon Vijay Abraham I
Hi,
Quoted 318 lines · Martin Blumenstingl
Hi Kishon,
Quoted 314 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 12 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 261 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 274 insertions(+)create mode 100644
drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +12
-0@@ -511,4 +511,16 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + endmenudrivers/phy/Makefile +1
-0@@ -62,3 +62,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.odrivers/phy/phy-meson-gxl-usb2.c new file +259
-0@@ -0,0 +1,261 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19, 17) +#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) +#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) +#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) +#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) +#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) +#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) +#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) +#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) +#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17, 14) +#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_reset (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +if (!priv->is_enabled) +return 0 ; + +/* reset the PHY and wait until settings are stabilized */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); +udelay (RESET_COMPLETE_TIME ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); +udelay (RESET_COMPLETE_TIME ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +phy_meson_gxl_usb2_reset (phy); + + priv->mode = mode; + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_off (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + + priv->is_enabled =0 ; + +/* power off the PHY by putting it into reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_on (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); +int ret; + + priv->is_enabled =1 ; + +/* power on the PHY by taking it out of reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); + + ret =phy_meson_gxl_usb2_set_mode (phy, priv->mode); +if (ret) { +phy_meson_gxl_usb2_power_off (phy); + +dev_err (&phy->dev,"Failed to initialize PHY with mode %d\n" , + priv->mode); +return ret; + } + +return 0 ; +} + +static const struct phy_ops phy_meson_gxl_usb2_ops = { + .power_on = phy_meson_gxl_usb2_power_on, + .power_off = phy_meson_gxl_usb2_power_off, + .set_mode = phy_meson_gxl_usb2_set_mode, + .reset = phy_meson_gxl_usb2_reset, + .owner =THIS_MODULE , +}; + +static int phy_meson_gxl_usb2_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +struct phy_provider *phy_provider; +struct resource *res; +struct phy_meson_gxl_usb2_priv *priv; +struct phy *phy; +void __iomem *base; + + priv =devm_kzalloc (dev,sizeof (*priv),GFP_KERNEL ); +if (!priv) +return -ENOMEM ; + +platform_set_drvdata (pdev, priv); + + res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); + base =devm_ioremap_resource (dev, res); +if (IS_ERR (base)) +return PTR_ERR (base); + + priv->mode =PHY_MODE_USB_HOST ; + + priv->regmap =devm_regmap_init_mmio (dev, base, + &phy_meson_gxl_usb2_regmap_conf); +if (IS_ERR (priv->regmap)) +return PTR_ERR (priv->regmap); + + phy =devm_phy_create (dev,NULL , &phy_meson_gxl_usb2_ops); +if (IS_ERR (phy)) { +dev_err (dev,"failed to create PHY\n" ); +return PTR_ERR (phy); + } + +phy_set_drvdata (phy, priv); + + phy_provider =devm_of_phy_provider_register (dev, of_phy_simple_xlate); + +return PTR_ERR_OR_ZERO (phy_provider); +} + +static const struct of_device_id phy_meson_gxl_usb2_of_match[] = { + { .compatible ="amlogic,meson-gxl-usb2-phy" , }, + { }, +}; +MODULE_DEVICE_TABLE (of, phy_meson_gxl_usb2_of_match); + +static struct platform_driver phy_meson_gxl_usb2_driver = { + .probe = phy_meson_gxl_usb2_probe, + .driver = { + .name ="phy-meson-gxl-usb2" , + .of_match_table = phy_meson_gxl_usb2_of_match, + }, +}; +module_platform_driver (phy_meson_gxl_usb2_driver); + +MODULE_AUTHOR ("Martin Blumenstingl <[email protected]>" );Quoted 8 lines
Quoted 5 lines
drivers/phy/phy-meson-gxl-usb2.c new file +2
-1+MODULE_DESCRIPTION ("Meson GXL and GXM USB2 PHY driver" ); +MODULE_LICENSE ("GPL v2" ); --2.12.2
the devicetree documentation already got Rob's ACK. is there anything that I still need to fix? I would really like to see this getting into 4.13
Quoted 6 lines
I don't have any further comments. I'll queue this once -rc1 is tagged. Btw Vivek Gautam has plans to change the directory structure of phy, so you might have to resend this patch once his patch is merged.
Vivek, since phy tree is already merged to Linus, can you send your restructuring patch asap based on linus latest?
Sure, I will send the patch soon this week.
Regards
Vivek
Quoted 3 lines
Thanks
Kishon
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
Quoted 349 lines · Vivek Gautam
Hi,
Quoted 345 lines · Kishon Vijay Abraham I
Hi,
Quoted 342 lines · Martin Blumenstingl
Hi Kishon,
Quoted 335 lines · Martin Blumenstingl
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/phy/Kconfig | 12 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-meson-gxl-usb2.c | 261 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 274 insertions(+)create mode 100644
drivers/phy/phy-meson-gxl-usb2.cdrivers/phy/Kconfig +12
-0@@ -511,4 +511,16 @@ config PHY_MESON8B_USB2 and GXBB SoCs. If unsure, say N. +config PHY_MESON_GXL_USB + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N. + endmenudrivers/phy/Makefile +0
-0@@ -62,3 +62,4 @@ obj-$(CONFIG_PHY_CYGNUS_PCIE) +=phy-bcm-cygnus-pcie.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.odrivers/phy/Makefile +1
-0+obj-$(CONFIG_PHY_MESON_GXL_USB) += phy-meson-gxl-usb2.odrivers/phy/phy-meson-gxl-usb2.c new file +4
-0@@ -0,0 +1,261 @@ +/* +* Meson GXL and GXM USB2 PHY driver +* +* Copyright (C) 2017 Martin Blumenstingl <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */drivers/phy/phy-meson-gxl-usb2.c new file +29
-0+ +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 +#define U2P_R0_BYPASS_SEL BIT(0) +#define U2P_R0_BYPASS_DM_EN BIT(1) +#define U2P_R0_BYPASS_DP_EN BIT(2) +#define U2P_R0_TXBITSTUFF_ENH BIT(3) +#define U2P_R0_TXBITSTUFF_EN BIT(4) +#define U2P_R0_DM_PULLDOWN BIT(5) +#define U2P_R0_DP_PULLDOWN BIT(6) +#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) +#define U2P_R0_DP_VBUS_VLD_EXT BIT(8) +#define U2P_R0_ADP_PRB_EN BIT(9) +#define U2P_R0_ADP_DISCHARGE BIT(10) +#define U2P_R0_ADP_CHARGE BIT(11) +#define U2P_R0_DRV_VBUS BIT(12) +#define U2P_R0_ID_PULLUP BIT(13) +#define U2P_R0_LOOPBACK_EN_B BIT(14) +#define U2P_R0_OTG_DISABLE BIT(15) +#define U2P_R0_COMMON_ONN BIT(16) +#define U2P_R0_FSEL_MASK GENMASK(19,17)
+ #defineU2P_R0_REF_CLK_SEL_MASKGENMASK(21,
20)drivers/phy/phy-meson-gxl-usb2.c new file +2
-0+#define U2P_R0_POWER_ON_RESET BIT(22) +#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24,23)
drivers/phy/phy-meson-gxl-usb2.c new file +18
-0+#define U2P_R0_ID_SET_ID_DQ BIT(25) +#define U2P_R0_ATE_RESET BIT(26) +#define U2P_R0_FSV_MINUS BIT(27) +#define U2P_R0_FSV_PLUS BIT(28) +#define U2P_R0_BYPASS_DM_DATA BIT(29) +#define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 +#define U2P_R1_BURN_IN_TEST BIT(0) +#define U2P_R1_ACA_ENABLE BIT(1) +#define U2P_R1_DCD_ENABLE BIT(2) +#define U2P_R1_VDAT_SRC_EN_B BIT(3) +#define U2P_R1_VDAT_DET_EN_B BIT(4) +#define U2P_R1_CHARGES_SEL BIT(5) +#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) +#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) +#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) +#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12,11)
+ #defineU2P_R1_TX_VREF_TUNE_MASKGENMASK(16,
13)
+ #defineU2P_R1_TX_FSLS_TUNE_MASKGENMASK(20,
17)
+ #defineU2P_R1_TX_HSXV_TUNE_MASKGENMASK(22,
21)
+ #defineU2P_R1_OTG_TUNE_MASKGENMASK(25,
23)
+ #defineU2P_R1_SQRX_TUNE_MASKGENMASK(28,
26)
+ #defineU2P_R1_COMP_DIS_TUNE_MASKGENMASK(31,
29)drivers/phy/phy-meson-gxl-usb2.c new file +9
-0+ +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 +#define U2P_R2_DATA_IN_MASK GENMASK(3, 0) +#define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4) +#define U2P_R2_ADDR_MASK GENMASK(11, 8) +#define U2P_R2_DATA_OUT_SEL BIT(12) +#define U2P_R2_CLK BIT(13) +#define U2P_R2_DATA_OUT_MASK GENMASK(17,14)
drivers/phy/phy-meson-gxl-usb2.c new file +162
-0+#define U2P_R2_ACA_PIN_RANGE_C BIT(18) +#define U2P_R2_ACA_PIN_RANGE_B BIT(19) +#define U2P_R2_ACA_PIN_RANGE_A BIT(20) +#define U2P_R2_ACA_PIN_GND BIT(21) +#define U2P_R2_ACA_PIN_FLOAT BIT(22) +#define U2P_R2_CHARGE_DETECT BIT(23) +#define U2P_R2_DEVICE_SESSION_VALID BIT(24) +#define U2P_R2_ADP_PROBE BIT(25) +#define U2P_R2_ADP_SENSE BIT(26) +#define U2P_R2_SESSION_END BIT(27) +#define U2P_R2_VBUS_VALID BIT(28) +#define U2P_R2_B_VALID BIT(29) +#define U2P_R2_A_VALID BIT(30) +#define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { +struct regmap *regmap; +enum phy_mode mode; +int is_enabled; +}; + +static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = { + .reg_bits =8 , + .val_bits =32 , + .reg_stride =4 , + .max_register =U2P_R3 , +}; + +static int phy_meson_gxl_usb2_reset (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +if (!priv->is_enabled) +return 0 ; + +/* reset the PHY and wait until settings are stabilized */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); +udelay (RESET_COMPLETE_TIME ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); +udelay (RESET_COMPLETE_TIME ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_set_mode (struct phy *phy,enum phy_mode mode) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + +switch (mode) { +case PHY_MODE_USB_HOST : +case PHY_MODE_USB_OTG : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +U2P_R0_DM_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +U2P_R0_DP_PULLDOWN ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP ,0 ); +break ; + +case PHY_MODE_USB_DEVICE : +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DM_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_DP_PULLDOWN , +0 ); +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_ID_PULLUP , +U2P_R0_ID_PULLUP ); +break ; + +default : +return -EINVAL ; + } + +phy_meson_gxl_usb2_reset (phy); + + priv->mode = mode; + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_off (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); + + priv->is_enabled =0 ; + +/* power off the PHY by putting it into reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET , +U2P_R0_POWER_ON_RESET ); + +return 0 ; +} + +static int phy_meson_gxl_usb2_power_on (struct phy *phy) +{ +struct phy_meson_gxl_usb2_priv *priv =phy_get_drvdata (phy); +int ret; + + priv->is_enabled =1 ; + +/* power on the PHY by taking it out of reset mode */ +regmap_update_bits (priv->regmap,U2P_R0 ,U2P_R0_POWER_ON_RESET ,0 ); + + ret =phy_meson_gxl_usb2_set_mode (phy, priv->mode); +if (ret) { +phy_meson_gxl_usb2_power_off (phy); + +dev_err (&phy->dev,"Failed to initialize PHY with mode %d\n" , + priv->mode); +return ret; + } + +return 0 ; +} + +static const struct phy_ops phy_meson_gxl_usb2_ops = { + .power_on = phy_meson_gxl_usb2_power_on, + .power_off = phy_meson_gxl_usb2_power_off, + .set_mode = phy_meson_gxl_usb2_set_mode, + .reset = phy_meson_gxl_usb2_reset, + .owner =THIS_MODULE , +}; + +static int phy_meson_gxl_usb2_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +struct phy_provider *phy_provider; +struct resource *res; +struct phy_meson_gxl_usb2_priv *priv; +struct phy *phy; +void __iomem *base; + + priv =devm_kzalloc (dev,sizeof (*priv),GFP_KERNEL ); +if (!priv) +return -ENOMEM ; + +platform_set_drvdata (pdev, priv); + + res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); + base =devm_ioremap_resource (dev, res); +if (IS_ERR (base)) +return PTR_ERR (base); + + priv->mode =PHY_MODE_USB_HOST ; + + priv->regmap =devm_regmap_init_mmio (dev, base, + &phy_meson_gxl_usb2_regmap_conf); +if (IS_ERR (priv->regmap)) +return PTR_ERR (priv->regmap); + + phy =devm_phy_create (dev,NULL , &phy_meson_gxl_usb2_ops); +if (IS_ERR (phy)) { +dev_err (dev,"failed to create PHY\n" ); +return PTR_ERR (phy); + } + +phy_set_drvdata (phy, priv); + + phy_provider = devm_of_phy_provider_register(dev,
of_phy_simple_xlate);drivers/phy/phy-meson-gxl-usb2.c new file +22
-0+ +return PTR_ERR_OR_ZERO (phy_provider); +} + +static const struct of_device_id phy_meson_gxl_usb2_of_match[] = { + { .compatible ="amlogic,meson-gxl-usb2-phy" , }, + { }, +}; +MODULE_DEVICE_TABLE (of, phy_meson_gxl_usb2_of_match); + +static struct platform_driver phy_meson_gxl_usb2_driver = { + .probe = phy_meson_gxl_usb2_probe, + .driver = { + .name ="phy-meson-gxl-usb2" , + .of_match_table = phy_meson_gxl_usb2_of_match, + }, +}; +module_platform_driver (phy_meson_gxl_usb2_driver); + +MODULE_AUTHOR ("Martin Blumenstingl <[email protected]>" ); +MODULE_DESCRIPTION ("Meson GXL and GXM USB2 PHY driver" ); +MODULE_LICENSE ("GPL v2" );Signature · 1 line
2.12.2the devicetree documentation already got Rob's ACK. is there anything that I still need to fix? I would really like to see this getting into 4.13
Quoted 8 lines
Quoted 6 lines
I don't have any further comments. I'll queue this once -rc1 is tagged. Btw Vivek Gautam has plans to change the directory structure of phy, so you might have to resend this patch once his patch is merged.
Vivek, since phy tree is already merged to Linus, can you send your restructuring patch asap based on linus latest?
Sure, I will send the patch soon this week.
Thanks Vivek.
-Kishon
Martin Blumenstingl
reviewerv4 cover Meson GXL USB2 PHY driver
In reply to Martin BlumenstinglThis series adds a driver for the USB2 PHYs found in Amlogic Meson GXL (and GXM) SoCs.
Devicetree changes are intentionally missing in this series because of various other problems that need to be resolved before we get USB host support working.
As usual we unfortunately don't have any documentation available. The register definitions were taken from the vendor's GPL kernel sources (see [5] if you are really interested). Translation to human readable names is done using the "best effort" algorithm.
The USB situation on GXL and GXM is a bit special:
the SoCs include both, a dwc3 and a dwc2 controller. The dwc3 controller IP only supports host-mode, while the dwc2 controller IP only supports device mode.
The dwc3 controller has all USB3 ports disabled. GXL has two USB2 ports enabled on dwc3's internal hub, while GXM has three USB2 ports enabled. This makes the initialization a bit special: to enable any of the dwc3 controller's USB2 ports *ALL* PHYs have to be initialized (probably due to the hub's routing logic).
The first USB2 PHY (hardware-wise) also supports OTG mode. The vendor kernel implements this through the USB3 PHY by re-routing the first USB2 PHY from the dwc3 controller to the dwc2 controller (which is disabled by default, but if the USB3 PHY detects that the port should enter device mode it enables the dwc2 controller).
To get USB host mode working the following steps are needed:
- xhci-plat must be able to manage more than one PHY for a controller, this is work-in-progress, see [0]
- there are some DMA handling issues in dwc3 and the rest of the USB stack, this is solved by the "sysdev" patches from [1]
- adding all USB related bits to meson-gxl.dtsi - this is work in progress but depends on the previous TODOs, see [2] and [3]
This supersedes my previous series "Meson GXL and GXM USB support" [4].
Changes since v3:
- rebased to apply on top of "phy: Group vendor specific phy drivers" (the whole series is based on the "fixes" branch in Kishon's linux-phy.git, commit a380b78b799b418 "phy: qualcomm: phy-qcom-qmp:
fix application of sizeof to pointer")
- renamed Kconfig symbol from PHY_MESON_GXL_USB to PHY_MESON_GXL_USB2 (as there is also a USB3 PHY within the SoC which needs a different drivers since it uses completely different registers)
Changes since v2:
- removed PHY mode parsing from phy_meson_gxl_usb2_probe (based on of_usb_get_dr_mode_by_phy()) because this will not work with the xhci-plat changes anyways. The driver now simply defaults to host mode until a consumer uses phy_set_mode().
- fixed a stray newline in drivers/phy/Kconfig b/drivers/phy/Kconfig (thanks for spotting this Kishon)
- simplified phy_meson_gxl_usb2_reset() by returning early (thanks Kishon for suggesting this improvement)
Changes since v1:
- rebased to the next branch of Kishon's linux-phy tree (currently at fe0134d071 "phy: phy-exynos-pcie: make it explicitly non-modular")
- added a missing call to phy_meson_gxl_usb2_power_off in the error case in phy_meson_gxl_usb2_power_on - thanks to Hendrik v. Raven for spotting this!
- moved the reset logic into a separate function and expose it through phy_ops.reset so it can be used by consumers of this PHY. phy_meson_gxl_usb2_set_mode still resets the PHY directly because this PHY will be configured by xhci-plat (from which we cannot call phy_reset() - see the discussion based on v1 of this patch: [6])
- added Rob Herring's ACK to patch #1 (the dt-binding documentation)
[0] https://www.spinics.net/lists/linux-usb/msg151837.html
[1] http://www.mail-archive.com/linux-usb at vger.kernel.org/msg87077.html
[2] https://github.com/xdarklight/linux/commit/e2b83785687fe859ae4bba8da8bb2fb2d7e32bfb
[3] https://github.com/xdarklight/linux/commit/203ab9ea5d1bea0bf066b6738010c8072b821d87
[4] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/001721.html
[5] https://github.com/khadas/linux/blob/76fd19ac41bb774e396ce8009ff665f29c26c535/include/linux/amlogic/usb-gxl.h
[6] http://lists.infradead.org/pipermail/linux-amlogic/2017-March/002777.html
Martin Blumenstingl (2):
Documentation: dt-bindings: Add documentation for the Meson GXL USB2
PHY
phy: meson: add USB2 PHY support for Meson GXL and GXM
.../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 ++ drivers/phy/amlogic/Kconfig | 13 + drivers/phy/amlogic/Makefile | 1 + drivers/phy/amlogic/phy-meson-gxl-usb2.c | 273 +++++++++++++++++++++ 4 files changed, 304 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb2.c
Signature · 1 line
2.13.0
Martin Blumenstingl
reviewerPATCH v4 1/2 Documentation: dt-bindings: Add documentation for the Meson GXL USB2 PHY
This adds the DT binding documentation for the USB2 PHY(s) found in the Meson GXL and GXM SoCs.
--- .../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt new file +17 -0
@@ -0,0 +1,17 @@ +* Amlogic Meson GXL and GXM USB2 PHY binding + +Required properties: +- compatible: Should be "amlogic,meson-gxl-usb2-phy" +- reg: The base address and length of the registers +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) + +Optional properties: +- phy-supply: see phy-bindings.txt in this directory + + +Example: + usb2_phy0: phy at 78000 { + compatible = "amlogic,meson-gxl-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0x78000 0x0 0x20>; + };
Signature · 1 line
2.13.0
PATCH v4 1/2 Documentation: dt-bindings: Add documentation for the Meson GXL USB2 PHY
Hi,
Quoted 5 lines · Martin Blumenstingl
This adds the DT binding documentation for the USB2 PHY(s) found in the Meson GXL and GXM SoCs.
Signed-off-by Martin Blumenstingl <[email protected]>Acked-by Rob Herring <[email protected]>
changed $subject to
dt-bindings: phy: meson-gxl-usb2-phy: Add documentation for the Meson GXL USB2 PHY
and merged.
Thanks
Kishon
Martin Blumenstingl
reviewerPATCH v4 1/2 Documentation: dt-bindings: Add documentation for the Meson GXL USB2 PHY
Hi Kishon,
Quoted 6 lines · Kishon Vijay Abraham I
Hi,
Quoted 3 lines · Martin Blumenstingl
This adds the DT binding documentation for the USB2 PHY(s) found in the Meson GXL and GXM SoCs.
Quoted 7 lines
Quoted 2 lines
Signed-off-by Martin Blumenstingl <[email protected]>Acked-by Rob Herring <[email protected]>changed $subject to
dt-bindings: phy: meson-gxl-usb2-phy: Add documentation for the Meson GXL USB2 PHYand merged.
oh, excellent catch - many thanks for fixing this up (and thus saving me another round)!
Regards,
Martin
Martin Blumenstingl
reviewerPATCH v4 2/2 phy: meson: add USB2 PHY support for Meson GXL and GXM
In reply to Martin BlumenstinglThis adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY).
Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have.
--- drivers/phy/amlogic/Kconfig | 13 ++ drivers/phy/amlogic/Makefile | 1 + drivers/phy/amlogic/phy-meson-gxl-usb2.c | 273 +++++++++++++++++++++++++++++++ 3 files changed, 287 insertions(+) create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb2.c
drivers/phy/amlogic/Kconfig +13 -0
@@ -12,3 +12,16 @@ config PHY_MESON8B_USB2 Enable this to support the Meson USB2 PHYs found in Meson8b and GXBB SoCs. If unsure, say N. + +config PHY_MESON_GXL_USB2 + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on USB_SUPPORT + select USB_COMMON + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHYs found in Meson + GXL and GXM SoCs. + If unsure, say N.
drivers/phy/amlogic/Makefile +1 -0
@@ -1 +1,2 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
drivers/phy/amlogic/phy-meson-gxl-usb2.c new file +273 -0
273 lines not on this page · raw message
Signature · 1 line
2.13.0