ARM: dts: add SDC2 and SDC4 to the MSM8660 family
Subsystems (2)
PATCH 1/2 ARM: dts: add SDC2 and SDC4 to the MSM8660 family
To make the picture complete, add DTS entries also for the second and fourth MMC/SD blocks on the MSM8660. SDC2 is an 8-bit interface and SDC4 is a 4-bit interface.
--- arch/arm/boot/dts/qcom-msm8660.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
arch/arm/boot/dts/qcom-msm8660.dtsi +31 -0
@@ -392,6 +392,22 @@ cap-mmc-highspeed; }; + sdcc2: sdcc at 12140000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12140000 0x8000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + }; + sdcc3: sdcc at 12180000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>;
@@ -408,6 +424,21 @@ no-1-8-v; }; + sdcc4: sdcc at 121c0000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x121c0000 0x8000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + }; + sdcc5: sdcc at 12200000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>;
Signature · 1 line
2.9.3
PATCH 1/2 ARM: dts: add SDC2 and SDC4 to the MSM8660 family
Quoted 5 lines · Linus Walleij
To make the picture complete, add DTS entries also for the second and fourth MMC/SD blocks on the MSM8660. SDC2 is an 8-bit interface and SDC4 is a 4-bit interface.
Signed-off-by Linus Walleij <[email protected]>
Regards,
Bjorn
PATCH 1/2 ARM: dts: add SDC2 and SDC4 to the MSM8660 family
In reply to Linus WalleijQuoted 19 lines · Linus Walleij
To make the picture complete, add DTS entries also for the second and fourth MMC/SD blocks on the MSM8660. SDC2 is an 8-bit interface and SDC4 is a 4-bit interface.
Signed-off-by Linus Walleij <[email protected]>--- arch/arm/boot/dts/qcom-msm8660.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)arch/arm/boot/dts/qcom-msm8660.dtsi +2
-0@@ -392,6 +392,22 @@ cap-mmc-highspeed; }; + sdcc2: sdcc at 12140000 { + status = "disabled";
arch/arm/boot/dts/qcom-msm8660.dtsi line 406
Quoted 10 lines
arch/arm/boot/dts/qcom-msm8660.dtsi +10
-0+ compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12140000 0x8000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + non-removable;
Should things like non-removable or max-frequency be specified in the base dts? Those seem like board attributes.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 1/2 ARM: dts: add SDC2 and SDC4 to the MSM8660 family
Quoted 8 lines · Stephen Boyd
arch/arm/boot/dts/qcom-msm8660.dtsi line 406
Quoted 3 lines · Linus Walleij
arch/arm/boot/dts/qcom-msm8660.dtsi +3
-0+ bus-width = <8>; + max-frequency = <48000000>; + non-removable;Should things like non-removable or max-frequency be specified in the base dts? Those seem like board attributes.
I dropped non-removable, which is obviously a board attribute.
max-frequency in this case is a cap on how high the IP can go in this (Qualcomm) variant, on this SoC. A board DTS may need to override it pushing it downwards because of line characteristics.
Yours,
Linus Walleij