ARM: dts: imx6qp: reference PCIe node by handle
Subsystems (2)
PATCH 1/3 ARM: dts: imx6qp: reference PCIe node by handle
By using the handle, we can avoid some duplication of the base DT and so avoid any maintenance overhead in the QP DT if the referenced node changes.
--- arch/arm/boot/dts/imx6qp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm/boot/dts/imx6qp.dtsi +4 -4
@@ -82,10 +82,6 @@ "ldb_di0", "ldb_di1", "prg"; }; - pcie: pcie at 0x01000000 { - compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; - }; - aips-bus at 02100000 { mmdc0: mmdc at 021b0000 { /* MMDC0 */ compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
@@ -110,3 +106,7 @@ "di0_sel", "di1_sel", "di2_sel", "di3_sel", "di0", "di1"; }; + +&pcie { + compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; +};
Signature · 1 line
2.11.0
PATCH 2/3 ARM: dts: imx6qp: reference MMDC node by handle and remove duplication
Referencing the node by handle make the QP DT more resilent against changes of the base DT. Also remove the duplicated reg property, it's not needed as it the same as in the base DT, just the compatible is actually different.
--- arch/arm/boot/dts/imx6qp.dtsi | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-)
arch/arm/boot/dts/imx6qp.dtsi +4 -7
@@ -81,13 +81,6 @@ "di0_sel", "di1_sel", "ldb_di0", "ldb_di1", "prg"; }; - - aips-bus at 02100000 { - mmdc0: mmdc at 021b0000 { /* MMDC0 */ - compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - }; - }; }; };
@@ -107,6 +100,10 @@ "di0", "di1"; }; +&mmdc0 { + compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; +}; + &pcie { compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; };
Signature · 1 line
2.11.0
PATCH 3/3 ARM: dts: imx6qp: correct IPU nodes
In reply to Lucas StachReference them by handle and remove the changed clocks that are copied from the downstream DT and are not part of the mainline binding.
--- arch/arm/boot/dts/imx6qp.dtsi | 34 ++++++++-------------------------- 1 file changed, 8 insertions(+), 26 deletions(-)
arch/arm/boot/dts/imx6qp.dtsi +8 -26
@@ -55,32 +55,6 @@ reg = <0x00960000 0x20000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - - ipu1: ipu at 02400000 { - compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; - clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>, - <&clks IMX6QDL_CLK_PRG0_APB>; - clock-names = "bus", - "di0", "di1", - "di0_sel", "di1_sel", - "ldb_di0", "ldb_di1", "prg"; - }; - - ipu2: ipu at 02800000 { - compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; - clocks = <&clks IMX6QDL_CLK_IPU2>, - <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>, - <&clks IMX6QDL_CLK_PRG1_APB>; - clock-names = "bus", - "di0", "di1", - "di0_sel", "di1_sel", - "ldb_di0", "ldb_di1", "prg"; - }; }; };
@@ -90,6 +64,14 @@ <0 119 IRQ_TYPE_LEVEL_HIGH>; }; +&ipu1 { + compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; +}; + +&ipu2 { + compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; +}; + &ldb { clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
Signature · 1 line
2.11.0
Shawn Guo
AppliedPATCH 1/3 ARM: dts: imx6qp: reference PCIe node by handle
In reply to Lucas StachQuoted 5 lines · Lucas Stach
By using the handle, we can avoid some duplication of the base DT and so avoid any maintenance overhead in the QP DT if the referenced node changes.
Signed-off-by Lucas Stach <[email protected]>
Applied all, thanks.