arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width

index afc0cefda3..5925bae69f 100644
@@ -230,6 +230,20 @@ static int serdes_max_lines_get(void)
 	return 0;
 }
 
+/*
+ * Tests have shown that on some boards the default width of the
+ * configuration pulse for the PEX link detection might lead to
+ * non-established PCIe links (link down). Especially under certain
+ * conditions (higher temperature) and with specific PCIe devices.
+ * To enable a board-specific detection pulse width this weak
+ * array "serdes_pex_pulse_width[4]" is introduced which can be
+ * overwritten if needed by a board-specific version. If the board
+ * code does not provide a non-weak version of this variable, the
+ * default value will be used. So nothing is changed from the
+ * current setup on the supported board.
+ */
+__weak u8 serdes_pex_pulse_width[4] = { 2, 2, 2, 2 };
+
 int serdes_phy_config(void)
 {
 	int status = MV_OK;

@@ -891,6 +905,23 @@ int serdes_phy_config(void)
 			pex_unit = line_num >> 2;
 			pex_line_num = line_num % 4;
 			if (0 == pex_line_num) {
+				/*
+				 * Configure the detection pulse with before
+				 * the reset is deasserted
+				 */
+
+				/* Read the old value (indirect access) */
+				reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+					  (0x48 << 16) | (1 << 31) |
+					  (pex_line_num << 24));
+				tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
+				tmp &= ~(1 << 31);	/* Clear read */
+				tmp &= ~(3 << 6);	/* Mask width */
+				/* Insert new detection pulse width */
+				tmp |= serdes_pex_pulse_width[pex_unit] << 6;
+				/* Write value back */
+				reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+
 				reg_write(PEX_PHY_ACCESS_REG(pex_unit),
 					  (0xC1 << 16) | 0x24);
 				DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),

index 4be7b61cd2..ab282536ec 100644
@@ -115,6 +115,13 @@ MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
 	},
 };
 
+/*
+ * Define a board-specific detection pulse-width array for the SerDes PCIe
+ * interfaces. If not defined in the board code, the default of currently 2
+ * is used. Values from 0...3 are possible (2 bits).
+ */
+u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
+
 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
 {
 	/* Only one mode supported for this board */

index ab282536ec..6a24e1c8a6 100644
@@ -298,3 +298,44 @@ int board_late_init(void)
 	return 0;
 }
 #endif
+
+#ifndef CONFIG_SPL_BUILD
+int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pci_dev_t bdf;
+	u16 ven_id, dev_id;
+
+	if (argc != 3)
+		return cmd_usage(cmdtp);
+
+	ven_id = simple_strtoul(argv[1], NULL, 16);
+	dev_id = simple_strtoul(argv[2], NULL, 16);
+
+	printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
+	       ven_id, dev_id);
+
+	/*
+	 * Check if the PCIe device is detected (somtimes its not available
+	 * on the PCIe bus)
+	 */
+	bdf = pci_find_device(ven_id, dev_id, 0);
+	if (bdf == -1) {
+		/* PCIe device not found! */
+		printf("Failed to find PCIe device\n");
+	} else {
+		/* PCIe device found! */
+		printf("PCIe device found, resetting board...\n");
+
+		/* default handling: SOFT reset */
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pcie,   3,   0,     do_pcie_test,
+	"Test for presence of a PCIe device",
+	"<VendorID> <DeviceID>"
+);
+#endif