ARM: dts: imx: add Gateworks Ventana GW5904 support

The Gateworks Ventana GW5904 is a single-board computer based on the NXP IMX6 SoC with the following features:
* IMX6 DualLite Soc (supports IMX6S,IMX6DL,IMX6Q)
* 2048MB DDR3 DRAM (4x64bit) (options up to 4GiB)
* 8GB eMMC
* Gateworks System Controller:
- hardware watchdog
- hardware monitor
- pushbutton controller
- EEPROM storage
- power control
* JTAG programmable
* 1x miniPCIe socket (with PCIe, USB)
* 1x miniPCIe socket (USB)
* 1x M.2 socket (USB, 2x SIM)
* Inertial Module (LSM9DS1 9DOF: 3x acc, 3x rate, 3x mag)
* GPS (optional uBlox EVA-M8M)
* Application headers:
- 2x RS232 UART (TX/RX/CTS/RTS)
- 8x TTL GPIO (3x configurable as PWM)
- 1x LVDS display 3D+C with i2c touch and PWM backlight
* MV88E6176 GbE Switch (uplink to IMX FEC)
* Front panel connectors:
- 1x user programmable LED
- 1x configurable user pushbutton
- 1x USB OTG
- 4x GbE LAN

Signed-off-by Tim Harvey <[email protected]>

---

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +36 -0

+		switch at 0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0>; /* MDIO address 0, switch 0 in tree */
+
+			port at 0 {
+				reg = <0>;
+				label = "lan4";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan3";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "lan2";
+			};
+
+			port at 3 {
+				reg = <3>;
+				label = "lan1";
+			};
+
+			port at 5 {
+				reg = <5>;
+				label = "cpu";
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};

Review

Quoted 9 lines

(quoted diff) +8 -0

+     dsa {
+             compatible = "marvell,dsa";
+             #address-cells = <2>;
+             #size-cells = <0>;
+
+             dsa,ethernet = <&fec>;
+             dsa,mii-bus = <&mdio>;
+

Please consider using the new binding for DSA switches, see:

https://patchwork.kernel.org/patch/9493037/

Quoted 26 lines

(quoted diff) +26 -0

+             switch at 0 {
+                     #address-cells = <1>;
+                     #size-cells = <0>;
+                     reg = <0 0>; /* MDIO address 0, switch 0 in tree */
+
+                     port at 0 {
+                             reg = <0>;
+                             label = "lan4";
+                     };
+
+                     port at 1 {
+                             reg = <1>;
+                             label = "lan3";
+                     };
+
+                     port at 2 {
+                             reg = <2>;
+                             label = "lan2";
+                     };
+
+                     port at 3 {
+                             reg = <3>;
+                             label = "lan1";
+                     };
+
+                     port at 5 {

Review

Quoted 10 lines

(quoted diff) +10 -0

+                             reg = <5>;
+                             label = "cpu";
+                             fixed-link {
+                                     speed = <1000>;
+                                     full-duplex;
+                             };
+                     };
+             };
+     };
+};

--
Florian

Quoted 12 lines · Florian Fainelli

Review

Quoted 9 lines

(quoted diff) +8 -0

+     dsa {
+             compatible = "marvell,dsa";
+             #address-cells = <2>;
+             #size-cells = <0>;
+
+             dsa,ethernet = <&fec>;
+             dsa,mii-bus = <&mdio>;
+

Please consider using the new binding for DSA switches, see:

Quoted 2 lines

https://patchwork.kernel.org/patch/9493037/

Hi Florian,

I tried the new binding first, but haven't gotten it to work yet. Let me make sure I understand what I should be doing.

This is a MV88E6176 so I first need to add dt support for that to the mv88e6xxx driver (which supports the device, just not via dt):

drivers/net/dsa/mv88e6xxx/chip.c +4 -0

index 03dc886..fd5c716 100644
@@ -4602,6 +4602,10 @@ static const struct of_device_id mv88e6xxx_of_match[] = {
                .data = &mv88e6xxx_table[MV88E6085],
        },
        {
+               .compatible = "marvell,mv88e6176",
+               .data = &mv88e6xxx_table[MV88E6176],
+       },
+       {
                .compatible = "marvell,mv88e6190",
                .data = &mv88e6xxx_table[MV88E6190],
        },

Then I remove the old binding and add the new binding as such:

&fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        status = "okay";

        mdio {
                #address-cells = <1>;
                #size-cells = <0>;

                switch0 at 0 {
                        compatible = "marvell,mv88e6176";

                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0>;

                        ports {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                port at 0 {
                                        reg = <0>;
                                        label = "lan0";
                                };

                                port at 1 {
                                        reg = <1>;
                                        label = "lan1";
                                };

                                port at 2 {
                                        reg = <2>;
                                        label = "lan2";
                                };

                                port at 3 {
                                        reg = <3>;
                                        label = "lan3";
                                };

                                port at 5 {
                                        reg = <5>;
                                        label = "cpu";
                                        ethernet = <&fec>;
                                        fixed-link {
                                                speed = <1000>;
                                                full-duplex;
                                        };
                                };
                        };
                };
        };
};

This does give me eth0, lan1, lan2, lan3, lan4 netdevs but when I bring up eth0 I crash:

root at ventana:~# ifconfig eth0 up

[   45.826516] ------------[ cut here ]------------
[   45.831169] Kernel BUG at c01923cc [verbose debug info unavailable]
[   45.837461] Internal error: Oops - BUG: 0 [#1] SMP ARM
[   45.842617] Modules linked in:
[   45.845692] CPU: 0 PID: 486 Comm: ifconfig Tainted: G        W
 4.11.0-rc1-00020-g0885e48-dirty #537
[   45.855265] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[   45.861805] task: ee2e55c0 task.stack: eddd2000
[   45.866348] PC is at mod_timer+0x1e4/0x22c
[   45.870456] LR is at add_timer+0x20/0x28
[   45.874391] pc : [<c01923cc>]    lr : [<c0192434>]    psr: 600e0093
[   45.874391] sp : eddd3c20  ip : eddd3c60  fp : eddd3c5c
[   45.885878] r10: 00000200  r9 : ee828818  r8 : 00000064
[   45.891112] r7 : ee802e00  r6 : ffff9d19  r5 : ee802e00  r4 : ee21b350
[   45.897649] r3 : 00000000  r2 : 00000000  r1 : ffff9d19  r0 : ee21b350
[   45.904187] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment none
[   45.911417] Control: 10c5387d  Table: 3dea804a  DAC: 00000051
[   45.917173] Process ifconfig (pid: 486, stack limit = 0xeddd2210)
[   45.923275] Stack: (0xeddd3c20 to 0xeddd4000)
[   45.927647] 3c20: c01257f8 c01256e8 000005e9 c01402fc 00000004
00000004 ee802e00 ee21b350
[   45.935838] 3c40: ee802e00 00000064 ee828818 00000200 eddd3c6c
eddd3c60 c0192434 c01921f4
[   45.944029] 3c60: eddd3c94 eddd3c70 c014026c c0192420 00000064
ee21b330 eddd3c94 600e0013
[   45.952220] 3c80: ee21b330 00000004 eddd3cbc eddd3c98 c01403d8
c01401f0 ee21b000 00000000
[   45.960410] 3ca0: c05f9e7c c05f9e7c 00000008 ee828818 eddd3ccc
eddd3cc0 c05e71a0 c0140368
[   45.968600] 3cc0: eddd3cec eddd3cd0 c05e945c c05e7188 eddd3d60
ee21b000 ee837000 c05f9e7c
[   45.976791] 3ce0: eddd3d14 eddd3cf0 c05e94c0 c05e9430 00000000
ee837000 eddd3d23 00000000
[   45.984981] 3d00: c1649b9c ee828818 eddd3dbc eddd3d18 c05f9e14
c05e9484 00000000 c05f7d48
[   45.993171] 3d20: 32000000 30383831 652e3030 72656874 2d74656e
00000031 000003e8 000000c8
[   46.001361] 3d40: c0172424 c0171cf4 000003e8 000000c8 014000c0
00000000 c1649b9c ee828814
[   46.009551] 3d60: 38383132 2e303030 65687465 74656e72 303a312d
ee800030 eddd3dbc eddd3d88
[   46.017742] 3d80: c021e458 c09a2f30 eddd3dbc c05fcde0 c05f8cc0
f11ba000 ee837000 ee828000
[   46.025931] 3da0: 00000000 f11ba000 ee837000 ee828000 eddd3df4
eddd3dc0 c05fce40 c05f9d18
[   46.034122] 3dc0: 00000001 ee83766c eddd3df4 ee837000 00000000
c0a6a9d4 ee837030 00000000
[   46.042311] 3de0: bebeaeaa 00000000 eddd3e1c eddd3df8 c078dde0
c05fcbd0 eddd3e1c ee837000
[   46.050502] 3e00: ee837000 00000001 00001043 00001002 eddd3e44
eddd3e20 c078e098 c078dd3c
[   46.058692] 3e20: ee837000 ee83713c 00001002 ee20d80c 00000000
bebeaeaa eddd3e6c eddd3e48
[   46.066881] 3e40: c078e17c c078e014 00000000 eddd3e90 00000000
ee20d80c bebeaaac bebeaeaa
[   46.075071] 3e60: eddd3edc eddd3e70 c080895c c078e168 c0e6b180
bebeaaac 00000020 ee20d80c
[   46.083261] 3e80: ee20d800 00000014 ee837000 00008914 30687465
00000000 00000000 00000000
[   46.091451] 3ea0: b6f81043 bebeaeaa 0000002c 0001b3b8 b6f81002
00008914 ed872920 bebeaaac
[   46.099642] 3ec0: ed872900 00000004 eddd2000 00000000 eddd3eec
eddd3ee0 c080b334 c0808230
[   46.107832] 3ee0: eddd3f0c eddd3ef0 c076bab4 c080b1a4 bebeaaac
ed872920 edf05140 c023af64
[   46.116022] 3f00: eddd3f7c eddd3f10 c023a5a4 c076b968 ffffff9c
eddb6000 fffffffe c0107f44
[   46.124213] 3f20: eddd2000 00000000 eddd3f4c eddd3f38 c0236b2c
c021cb88 fffffffe ffffff9c
[   46.132402] 3f40: eddd3f94 eddd3f50 c02242b8 c0236ad4 c0227ef8
edf05140 00000004 edf05140
[   46.140593] 3f60: 00008914 bebeaaac eddd2000 00000000 eddd3fa4
eddd3f80 c023af64 c023a514
[   46.148782] 3f80: 0001b8f0 0001b6c8 bebeab74 00000036 c0107f44
eddd2000 00000000 eddd3fa8
[   46.156972] 3fa0: c0107da0 c023af34 0001b8f0 0001b6c8 00000004
00008914 bebeaaac 00001002
[   46.165162] 3fc0: 0001b8f0 0001b6c8 bebeab74 00000036 00000000
00000000 0001b8f8 00000000
[   46.173352] 3fe0: 0001b07c bebeaa9c 0000accf b6f17c66 000e0030
00000004 00000000 00000000
[   46.181534] Backtrace:
[   46.184000] [<c01921e8>] (mod_timer) from [<c0192434>] (add_timer+0x20/0x28)
[   46.191062]  r10:00000200 r9:ee828818 r8:00000064 r7:ee802e00
r6:ee21b350 r5:ee802e00
[   46.198899]  r4:00000004
[   46.201453] [<c0192414>] (add_timer) from [<c014026c>]
(__queue_delayed_work+0x88/0x178)
[   46.209560] [<c01401e4>] (__queue_delayed_work) from [<c01403d8>]
(queue_delayed_work_on+0x7c/0x84)
[   46.218615]  r6:00000004 r5:ee21b330 r4:600e0013
[   46.223254] [<c014035c>] (queue_delayed_work_on) from [<c05e71a0>]
(phy_start_machine+0x24/0x2c)
[   46.232051]  r9:ee828818 r8:00000008 r7:c05f9e7c r6:c05f9e7c
r5:00000000 r4:ee21b000
[   46.239811] [<c05e717c>] (phy_start_machine) from [<c05e945c>]
(phy_connect_direct+0x38/0x54)
[   46.248351] [<c05e9424>] (phy_connect_direct) from [<c05e94c0>]
(phy_connect+0x48/0x80)
[   46.256367]  r7:c05f9e7c r6:ee837000 r5:ee21b000 r4:eddd3d60
[   46.262043] [<c05e9478>] (phy_connect) from [<c05f9e14>]
(fec_enet_mii_probe+0x108/0x170)
[   46.270234]  r9:ee828818 r8:c1649b9c r7:00000000 r6:eddd3d23
r5:ee837000 r4:00000000
[   46.277991] [<c05f9d0c>] (fec_enet_mii_probe) from [<c05fce40>]
(fec_enet_open+0x27c/0x344)
[   46.286351]  r6:ee828000 r5:ee837000 r4:f11ba000
[   46.290985] [<c05fcbc4>] (fec_enet_open) from [<c078dde0>]
(__dev_open+0xb0/0x118)
[   46.298567]  r10:00000000 r9:bebeaeaa r8:00000000 r7:ee837030
r6:c0a6a9d4 r5:00000000
[   46.306404]  r4:ee837000
[   46.308950] [<c078dd30>] (__dev_open) from [<c078e098>]
(__dev_change_flags+0x90/0x154)
[   46.316963]  r7:00001002 r6:00001043 r5:00000001 r4:ee837000
[   46.322635] [<c078e008>] (__dev_change_flags) from [<c078e17c>]
(dev_change_flags+0x20/0x50)
[   46.331085]  r9:bebeaeaa r8:00000000 r7:ee20d80c r6:00001002
r5:ee83713c r4:ee837000
[   46.338844] [<c078e15c>] (dev_change_flags) from [<c080895c>]
(devinet_ioctl+0x738/0x838)
[   46.347033]  r9:bebeaeaa r8:bebeaaac r7:ee20d80c r6:00000000
r5:eddd3e90 r4:00000000
[   46.354790] [<c0808224>] (devinet_ioctl) from [<c080b334>]
(inet_ioctl+0x19c/0x1c8)
[   46.362459]  r10:00000000 r9:eddd2000 r8:00000004 r7:ed872900
r6:bebeaaac r5:ed872920
[   46.370296]  r4:00008914
[   46.372848] [<c080b198>] (inet_ioctl) from [<c076bab4>]
(sock_ioctl+0x158/0x32c)
[   46.380262] [<c076b95c>] (sock_ioctl) from [<c023a5a4>]
(do_vfs_ioctl+0x9c/0xa20)
[   46.387756]  r7:c023af64 r6:edf05140 r5:ed872920 r4:bebeaaac
[   46.393429] [<c023a508>] (do_vfs_ioctl) from [<c023af64>]
(SyS_ioctl+0x3c/0x64)
[   46.400751]  r10:00000000 r9:eddd2000 r8:bebeaaac r7:00008914
r6:edf05140 r5:00000004
[   46.408589]  r4:edf05140
[   46.411141] [<c023af28>] (SyS_ioctl) from [<c0107da0>]
(ret_fast_syscall+0x0/0x1c)
[   46.418724]  r9:eddd2000 r8:c0107f44 r7:00000036 r6:bebeab74
r5:0001b6c8 r4:0001b8f0
[   46.426479] Code: eaffffbd e1a0500a e1a0a005 eaffffcc (e7f001f2)
[   46.432587] ---[ end trace c923534ad86e0767 ]---

Segmentation fault
root at ventana:~# [ 67.156856] systemd-journald[202]: Successfully
sent stream file descriptor to service manager.

Is there something wrong with my dt node that you see or perhaps something else going on here required by the new binding?

Thanks,

Tim

Quoted 38 lines

Quoted 26 lines

(quoted diff) +26 -0

+             switch at 0 {
+                     #address-cells = <1>;
+                     #size-cells = <0>;
+                     reg = <0 0>; /* MDIO address 0, switch 0 in tree */
+
+                     port at 0 {
+                             reg = <0>;
+                             label = "lan4";
+                     };
+
+                     port at 1 {
+                             reg = <1>;
+                             label = "lan3";
+                     };
+
+                     port at 2 {
+                             reg = <2>;
+                             label = "lan2";
+                     };
+
+                     port at 3 {
+                             reg = <3>;
+                             label = "lan1";
+                     };
+
+                     port at 5 {

Review

Quoted 10 lines

(quoted diff) +10 -0

+                             reg = <5>;
+                             label = "cpu";
+                             fixed-link {
+                                     speed = <1000>;
+                                     full-duplex;
+                             };
+                     };
+             };
+     };
+};

--
Florian

Quoted 16 lines · Tim Harvey

Quoted 14 lines · Florian Fainelli

Review

Quoted 9 lines

(quoted diff) +8 -0

+     dsa {
+             compatible = "marvell,dsa";
+             #address-cells = <2>;
+             #size-cells = <0>;
+
+             dsa,ethernet = <&fec>;
+             dsa,mii-bus = <&mdio>;
+

Please consider using the new binding for DSA switches, see:

https://patchwork.kernel.org/patch/9493037/

Quoted 7 lines

Hi Florian,

I tried the new binding first, but haven't gotten it to work yet. Let me make sure I understand what I should be doing.

This is a MV88E6176 so I first need to add dt support for that to the mv88e6xxx driver (which supports the device, just not via dt):

Quoted 7 lines

Then I remove the old binding and add the new binding as such:

&fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        status = "okay";

You most likely need to declare a fixed PHY for the FEC to be setting up the link, speed and duplex?

Quoted 17 lines · Florian Fainelli

Quoted 16 lines · Tim Harvey

Quoted 14 lines · Florian Fainelli

Review

Quoted 9 lines

(quoted diff) +8 -0

+     dsa {
+             compatible = "marvell,dsa";
+             #address-cells = <2>;
+             #size-cells = <0>;
+
+             dsa,ethernet = <&fec>;
+             dsa,mii-bus = <&mdio>;
+

Please consider using the new binding for DSA switches, see:

https://patchwork.kernel.org/patch/9493037/

Quoted 7 lines

Quoted 7 lines

Hi Florian,

I tried the new binding first, but haven't gotten it to work yet. Let me make sure I understand what I should be doing.

This is a MV88E6176 so I first need to add dt support for that to the mv88e6xxx driver (which supports the device, just not via dt):

Hi Tim

Nope. The 6176 is compatible with the 6085.

Quoted 8 lines

Quoted 7 lines

Then I remove the old binding and add the new binding as such:

&fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        status = "okay";

Quoted 2 lines

You most likely need to declare a fixed PHY for the FEC to be setting up the link, speed and duplex?

Take a look at arch/arm/boot/dts/vf610-zii-dev* as an example. This uses a vf610, so is somewhat similar to the imx6. Same fec driver, but the mdio is more complex due to there being 3 switches.

Andrew

Thanks for the hint on the compatibility. I wonder if Documentation/devicetree/bindings/net/dsa/marvell.txt should have some notes added about switch device compatibility? It wasn't clear to me that these would be compatible.

What is the convention, if any, of the naming of the 'lan' ports (0 based vs 1 based, eth vs lan)? Is it strictly up to the board vendor? The board I'm supporting has a silkscreen that shows 'Port 1' through 'Port 4' so I was leaning towards 1 based.

Quoted 41 lines · Tim Harvey

Quoted 12 lines · Florian Fainelli

Review

Quoted 9 lines

(quoted diff) +8 -0

+     dsa {
+             compatible = "marvell,dsa";
+             #address-cells = <2>;
+             #size-cells = <0>;
+
+             dsa,ethernet = <&fec>;
+             dsa,mii-bus = <&mdio>;
+

Please consider using the new binding for DSA switches, see:

Quoted 2 lines

https://patchwork.kernel.org/patch/9493037/

Hi Florian,

I tried the new binding first, but haven't gotten it to work yet. Let me make sure I understand what I should be doing.

This is a MV88E6176 so I first need to add dt support for that to the mv88e6xxx driver (which supports the device, just not via dt):

drivers/net/dsa/mv88e6xxx/chip.c +4 -0

index 03dc886..fd5c716 100644
@@ -4602,6 +4602,10 @@ static const struct of_device_id mv88e6xxx_of_match[] = {
                .data = &mv88e6xxx_table[MV88E6085],
        },
        {
+               .compatible = "marvell,mv88e6176",
+               .data = &mv88e6xxx_table[MV88E6176],
+       },
+       {
                .compatible = "marvell,mv88e6190",
                .data = &mv88e6xxx_table[MV88E6190],
        },

Then I remove the old binding and add the new binding as such:

Quoted 5 lines

&fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        status = "okay";

You most likely need to declare a fixed PHY for the FEC to be setting up the link, speed and duplex?

Quoted 6 lines

Quoted 5 lines

&fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        status = "okay";

Quoted 2 lines

You most likely need to declare a fixed PHY for the FEC to be setting up the link, speed and duplex?

Florian,

Thanks - this appears to be the issue. I declared the fixed-phy down in the cpu port but I guess it needs to be done in the net device.

The Gateworks Ventana GW5904 is a single-board computer based on the NXP IMX6 SoC with the following features:
* IMX6 DualLite Soc (supports IMX6S,IMX6DL,IMX6Q)
* 2048MB DDR3 DRAM (4x64bit) (options up to 4GiB)
* 8GB eMMC
* Gateworks System Controller:
- hardware watchdog
- hardware monitor
- pushbutton controller
- EEPROM storage
- power control
* JTAG programmable
* 1x miniPCIe socket (with PCIe, USB)
* 1x miniPCIe socket (USB)
* 1x M.2 socket (USB, 2x SIM)
* Inertial Module (LSM9DS1 9DOF: 3x acc, 3x rate, 3x mag)
* GPS (optional uBlox EVA-M8M)
* Application headers:
- 2x RS232 UART (TX/RX/CTS/RTS)
- 8x TTL GPIO (3x configurable as PWM)
- 1x LVDS display 3D+C with i2c touch and PWM backlight
* MV88E6176 GbE Switch (uplink to IMX FEC)
* Front panel connectors:
- 1x user programmable LED
- 1x configurable user pushbutton
- 1x USB OTG
- 4x GbE LAN

Signed-off-by Tim Harvey <[email protected]>

---
 arch/arm/boot/dts/Makefile            |   2 +
 arch/arm/boot/dts/imx6dl-gw5904.dts   |  19 ++
 arch/arm/boot/dts/imx6q-gw5904.dts    |  23 ++
 arch/arm/boot/dts/imx6qdl-gw5904.dtsi | 609 ++++++++++++++++++++++++++++++++++
 4 files changed, 653 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6dl-gw5904.dts
 create mode 100644 arch/arm/boot/dts/imx6q-gw5904.dts
 create mode 100644 arch/arm/boot/dts/imx6qdl-gw5904.dtsi

arch/arm/boot/dts/Makefile +2 -0

index ccecd79..7843b65 100644
@@ -352,6 +352,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6dl-gw551x.dtb \
 	imx6dl-gw552x.dtb \
 	imx6dl-gw553x.dtb \
+	imx6dl-gw5904.dtb \
 	imx6dl-hummingboard.dtb \
 	imx6dl-icore.dtb \
 	imx6dl-icore-rqs.dtb \

@@ -395,6 +396,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6q-gw551x.dtb \
 	imx6q-gw552x.dtb \
 	imx6q-gw553x.dtb \
+	imx6q-gw5904.dtb \
 	imx6q-h100.dtb \
 	imx6q-hummingboard.dtb \
 	imx6q-icore.dtb \

arch/arm/boot/dts/imx6dl-gw5904.dts new file +0 -0

new file mode 100644
index 0000000..2318a55

arch/arm/boot/dts/imx6dl-gw5904.dts new file +9 -0

+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5904.dtsi"
+
+/ {
+	model = "Gateworks Ventana i.MX6 DualLite/Solo GW5904";
+	compatible = "gw,imx6dl-gw5904", "gw,ventana", "fsl,imx6dl";
+};

arch/arm/boot/dts/imx6q-gw5904.dts new file +23 -0

new file mode 100644
index 0000000..357dd7e
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5904.dtsi"
+
+/ {
+	model = "Gateworks Ventana i.MX6 Dual/Quad GW5904";
+	compatible = "gw,imx6q-gw5904", "gw,ventana", "fsl,imx6q";
+};
+
+&sata {
+	status = "okay";
+};

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +15 -0

new file mode 100644
index 0000000..da674b94
@@ -0,0 +1,609 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	/* these are used by bootloader for disabling nodes */

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +34 -0

+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm4 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		led0: user1 {
+			label = "user1";
+			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		led1: user2 {
+			label = "user2";
+			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+			default-state = "off";
+		};
+
+		led2: user3 {
+			label = "user3";
+			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
+			default-state = "off";
+		};
+	};
+

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +30 -0

+	};
+
+	reg_1p0v: regulator-1p0v {
+		compatible = "regulator-fixed";
+		regulator-name = "1P0V";
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1000000>;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_usb_h1_vbus: regulator-usb-h1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_h1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +21 -0

+		dsa,ethernet = <&fec>;
+		dsa,mii-bus = <&mdio>;
+
+		switch at 0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0>; /* MDIO address 0, switch 0 in tree */
+
+			port at 0 {
+				reg = <0>;
+				label = "lan4";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan3";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "lan2";

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +49 -0

+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	eeprom1: eeprom at 50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	eeprom2: eeprom at 51 {
+		compatible = "atmel,24c02";
+		reg = <0x51>;
+		pagesize = <16>;
+	};
+
+	eeprom3: eeprom at 52 {
+		compatible = "atmel,24c02";
+		reg = <0x52>;

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +89 -0

+		compatible = "nxp,pca9555";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	rtc: ds1672 at 68 {
+		compatible = "dallas,ds1672";
+		reg = <0x68>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	ltc3676: pmic at 3c {
+		compatible = "lltc,ltc3676";
+		reg = <0x3c>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+
+		regulators {
+			/* VDD_SOC (1+R1/R2 = 1.635) */
+			reg_vdd_soc: sw1 {
+				regulator-name = "vddsoc";
+				regulator-min-microvolt = <674400>;
+				regulator-max-microvolt = <1308000>;
+				lltc,fb-voltage-divider = <127000 200000>;
+				regulator-ramp-delay = <7000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
+			reg_1p8v: sw2 {
+				regulator-name = "vdd1p8";
+				regulator-min-microvolt = <1033310>;
+				regulator-max-microvolt = <2004000>;
+				lltc,fb-voltage-divider = <301000 200000>;
+				regulator-ramp-delay = <7000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* VDD_ARM (1+R1/R2 = 1.635) */
+			reg_vdd_arm: sw3 {
+				regulator-name = "vddarm";
+				regulator-min-microvolt = <674400>;
+				regulator-max-microvolt = <1308000>;
+				lltc,fb-voltage-divider = <127000 200000>;
+				regulator-ramp-delay = <7000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* VDD_DDR (1+R1/R2 = 2.105) */
+			reg_vdd_ddr: sw4 {
+				regulator-name = "vddddr";
+				regulator-min-microvolt = <868310>;
+				regulator-max-microvolt = <1684000>;
+				lltc,fb-voltage-divider = <221000 200000>;
+				regulator-ramp-delay = <7000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
+			reg_2p5v: ldo2 {
+				regulator-name = "vdd2p5";
+				regulator-min-microvolt = <2490375>;
+				regulator-max-microvolt = <2490375>;
+				lltc,fb-voltage-divider = <487000 200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* VDD_HIGH (1+R1/R2 = 4.17) */
+			reg_3p0v: ldo4 {
+				regulator-name = "vdd3p0";
+				regulator-min-microvolt = <3023250>;
+				regulator-max-microvolt = <3023250>;
+				lltc,fb-voltage-divider = <634000 200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +21 -0

+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+		wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&ldb {
+	status = "okay";
+
+	lvds-channel at 0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +10 -0

+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pwm2 {

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +13 -0

+
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +31 -0

+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_usb_h1_vbus>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	non-removable;
+	vmmc-supply = <&reg_3p3v>;
+	keep-power-in-suspend;
+	status = "okay";

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +189 -0

+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x4001b0b0 /* PHY_RST# */
+			>;
+		};
+
+		pinctrl_gpio_leds: gpioledsgrp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
+				MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
+				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
+				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
+				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_pcie: pciegrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_0__GPIO1_IO00	0x1b0b0 /* PCIE RST */
+			>;
+		};
+
+		pinctrl_pmic: pmicgrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_8__GPIO1_IO08	0x1b0b0 /* PMIC_IRQ# */
+			>;
+		};
+
+		pinctrl_pps: ppsgrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm3: pwm3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_pwm4: pwm4grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
+				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
+			>;
+		};
+
+		pinctrl_uart3: uart3grp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
+				MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+				MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+				MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
+			>;
+		};
+
+		pinctrl_uart4: uart4grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
+				MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
+				MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
+				MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
+			>;
+		};
+
+		pinctrl_uart5: uart5grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
+				MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
+			>;
+		};
+
+		pinctrl_usbotg: usbotggrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
+				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* PWR_EN */
+				MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x1b0b0 /* OC */
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+				MX6QDL_PAD_SD3_RST__SD3_RESET		0x10059
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
+				MX6QDL_PAD_SD3_RST__SD3_RESET		0x100b9
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170b9
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170b9
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170b9
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170b9
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
+				MX6QDL_PAD_SD3_RST__SD3_RESET		0x100f9
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170f9
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170f9
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170f9
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170f9
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_DISP0_DAT8__WDOG1_B		0x1b0b0
+			>;
+		};
+	};
+};

Signature · 1 line

2.7.4

On Fri, Mar 10, 2017 at 12:40:11PM -0800, Tim Harvey wrote:

Quoted 6 lines

arch/arm/boot/dts/imx6dl-gw5904.dts new file +5 -0

@@ -0,0 +1,19 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License

arch/arm/boot/dts/imx6dl-gw5904.dts line 10

Quoted 5 lines

arch/arm/boot/dts/imx6dl-gw5904.dts new file +5 -0

+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */

For new dts files, GPL/X11 dual licence is recommended. There are plenty of examples in arch/arm/boot/dts.

Quoted 19 lines

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +19 -0

+&ldb {
+     status = "okay";
+
+     lvds-channel at 0 {
+             fsl,data-mapping = "spwg";
+             fsl,data-width = <18>;
+             status = "okay";
+
+             display-timings {
+                     native-mode = <&timing0>;
+                     timing0: hsd100pxn1 {
+                             clock-frequency = <65000000>;
+                             hactive = <1024>;
+                             vactive = <768>;
+                             hback-porch = <220>;
+                             hfront-porch = <40>;
+                             vback-porch = <21>;
+                             vfront-porch = <7>;
+                             hsync-len = <60>;

arch/arm/boot/dts/imx6qdl-gw5904.dtsi line 329

Quoted 4 lines

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +4 -0

+                             vsync-len = <10>;
+                     };
+             };
+     };

Take a look at commit 4dc633e9b019 ("ARM: dts: sabrelite: use simple-panel instead of display-timings for LVDS0"), and consider to use simple-panel?

Quoted 6 lines

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +6 -0

+
+&pwm2 {
+     pinctrl-names = "default";
+     pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+     status = "disabled";
+};

arch/arm/boot/dts/imx6qdl-gw5904.dtsi line 349

Quoted 6 lines

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +6 -0

+
+&pwm3 {
+     pinctrl-names = "default";
+     pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+     status = "disabled";
+};

Why do you have these two devices but disable them?

Quoted 19 lines

Quoted 19 lines

+&ldb {

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +18 -0

+     status = "okay";
+
+     lvds-channel at 0 {
+             fsl,data-mapping = "spwg";
+             fsl,data-width = <18>;
+             status = "okay";
+
+             display-timings {
+                     native-mode = <&timing0>;
+                     timing0: hsd100pxn1 {
+                             clock-frequency = <65000000>;
+                             hactive = <1024>;
+                             vactive = <768>;
+                             hback-porch = <220>;
+                             hfront-porch = <40>;
+                             vback-porch = <21>;
+                             vfront-porch = <7>;
+                             hsync-len = <60>;

Quoted 8 lines

arch/arm/boot/dts/imx6qdl-gw5904.dtsi line 329

Quoted 4 lines

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +4 -0

+                             vsync-len = <10>;
+                     };
+             };
+     };

Take a look at commit 4dc633e9b019 ("ARM: dts: sabrelite: use simple-panel instead of display-timings for LVDS0"), and consider to use simple-panel?

I haven't moved to simple-panel yet because I have bootloader code that allows choosing/altering display timings with the goal being users don't need to recompile their device-tree or kernel to use a display with different timings. It seems to me that moving to simple-panel would make this even more difficult as while the bootloader could find and alter the panel's compatible property (in the case the kernel has a supported simple-panel compiled in) it no longer has access to the raw timings (in case the kernel doesn't have a simple-panel driver built-in already).

I do like the way simple-panel combines display timings with backlight, power supplies, dc bus, and a gpio enable but it doesn't encapsulate touch controller or expose timings to device-tree for easy manipulation.

What are you thoughts on this?

Quoted 2 lines

<snip>

Quoted 6 lines

Quoted 6 lines

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +6 -0

+
+&pwm2 {
+     pinctrl-names = "default";
+     pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+     status = "disabled";
+};

Quoted 8 lines

arch/arm/boot/dts/imx6qdl-gw5904.dtsi line 349

Quoted 6 lines

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +6 -0

+
+&pwm3 {
+     pinctrl-names = "default";
+     pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+     status = "disabled";
+};

Why do you have these two devices but disable them?

This is because I have a bootloader configuration that allows the user to choose between GPIO and PWM for the non-backlight PWM pins. I should probably add a comment to those nodes specifying that firmware modifies the status property.

The Gateworks Ventana GW5904 is a single-board computer based on the NXP IMX6 SoC with the following features:
* IMX6 DualLite Soc (supports IMX6S,IMX6DL,IMX6Q)
* 2048MB DDR3 DRAM (4x64bit) (options up to 4GiB)
* 8GB eMMC
* Gateworks System Controller:
- hardware watchdog
- hardware monitor
- pushbutton controller
- EEPROM storage
- power control
* JTAG programmable
* 1x miniPCIe socket (with PCIe, USB)
* 1x miniPCIe socket (USB)
* 1x M.2 socket (USB, 2x SIM)
* Inertial Module (LSM9DS1 9DOF: 3x acc, 3x rate, 3x mag)
* GPS (optional uBlox EVA-M8M)
* Application headers:
- 2x RS232 UART (TX/RX/CTS/RTS)
- 8x TTL GPIO (3x configurable as PWM)
- 1x LVDS display 3D+C with i2c touch and PWM backlight
* MV88E6176 GbE Switch (uplink to IMX FEC)
* Front panel connectors:
- 1x user programmable LED
- 1x configurable user pushbutton
- 1x USB OTG
- 4x GbE LAN

Signed-off-by Tim Harvey <[email protected]>

---
v2:
- updated switch to latest dsa bindings
- update to GPL/X11 dual license
- use stdout-path instead of bootargs
- sort devices under i2c by address
- fix node/label name on touchscreen node
- removed unnecessary status okay for pps node
- removed unnecessary container node in iomuxc
- replaced deprecated fsl,uart-has-rtscts with uart-has-rtscts

---
 arch/arm/boot/dts/Makefile            |   2 +
 arch/arm/boot/dts/imx6dl-gw5904.dts   |  19 +
 arch/arm/boot/dts/imx6q-gw5904.dts    |  23 ++
 arch/arm/boot/dts/imx6qdl-gw5904.dtsi | 641 ++++++++++++++++++++++++++++++++++
 4 files changed, 685 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6dl-gw5904.dts
 create mode 100644 arch/arm/boot/dts/imx6q-gw5904.dts
 create mode 100644 arch/arm/boot/dts/imx6qdl-gw5904.dtsi

arch/arm/boot/dts/Makefile +2 -0

index ccecd79..7843b65 100644
@@ -352,6 +352,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6dl-gw551x.dtb \
 	imx6dl-gw552x.dtb \
 	imx6dl-gw553x.dtb \
+	imx6dl-gw5904.dtb \
 	imx6dl-hummingboard.dtb \
 	imx6dl-icore.dtb \
 	imx6dl-icore-rqs.dtb \

@@ -395,6 +396,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6q-gw551x.dtb \
 	imx6q-gw552x.dtb \
 	imx6q-gw553x.dtb \
+	imx6q-gw5904.dtb \
 	imx6q-h100.dtb \
 	imx6q-hummingboard.dtb \
 	imx6q-icore.dtb \

arch/arm/boot/dts/imx6dl-gw5904.dts new file +19 -0

new file mode 100644
index 0000000..2318a55
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5904.dtsi"
+
+/ {
+	model = "Gateworks Ventana i.MX6 DualLite/Solo GW5904";
+	compatible = "gw,imx6dl-gw5904", "gw,ventana", "fsl,imx6dl";
+};

arch/arm/boot/dts/imx6q-gw5904.dts new file +0 -0

new file mode 100644
index 0000000..357dd7e

arch/arm/boot/dts/imx6q-gw5904.dts new file +13 -0

+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5904.dtsi"
+
+/ {
+	model = "Gateworks Ventana i.MX6 Dual/Quad GW5904";
+	compatible = "gw,imx6q-gw5904", "gw,ventana", "fsl,imx6q";
+};
+
+&sata {
+	status = "okay";
+};

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +153 -0

new file mode 100644
index 0000000..ed1fa97
@@ -0,0 +1,641 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	/* these are used by bootloader for disabling nodes */
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		usb0 = &usbh1;
+		usb1 = &usbotg;
+	};
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm4 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		led0: user1 {
+			label = "user1";
+			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		led1: user2 {
+			label = "user2";
+			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+			default-state = "off";
+		};
+
+		led2: user3 {
+			label = "user3";
+			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
+			default-state = "off";
+		};
+	};
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	pps {
+		compatible = "pps-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pps>;
+		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+	};
+
+	reg_1p0v: regulator-1p0v {
+		compatible = "regulator-fixed";
+		regulator-name = "1P0V";
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1000000>;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_usb_h1_vbus: regulator-usb-h1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_h1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +36 -0

+			compatible = "marvell,mv88e6085";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port at 0 {
+					reg = <0>;
+					label = "lan4";
+				};
+
+				port at 1 {
+					reg = <1>;
+					label = "lan3";
+				};
+
+				port at 2 {
+					reg = <2>;
+					label = "lan2";
+				};
+
+				port at 3 {
+					reg = <3>;
+					label = "lan1";
+				};
+
+				port at 5 {
+					reg = <5>;
+					label = "cpu";
+					ethernet = <&fec>;
+				};
+			};
+		};

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +21 -0

+		compatible = "nxp,pca9555";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	eeprom1: eeprom at 50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	eeprom2: eeprom at 51 {
+		compatible = "atmel,24c02";
+		reg = <0x51>;
+		pagesize = <16>;
+	};
+
+	eeprom3: eeprom at 52 {
+		compatible = "atmel,24c02";
+		reg = <0x52>;

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +82 -0

+		compatible = "dallas,ds1672";
+		reg = <0x68>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	ltc3676: pmic at 3c {
+		compatible = "lltc,ltc3676";
+		reg = <0x3c>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+
+		regulators {
+			/* VDD_SOC (1+R1/R2 = 1.635) */
+			reg_vdd_soc: sw1 {
+				regulator-name = "vddsoc";
+				regulator-min-microvolt = <674400>;
+				regulator-max-microvolt = <1308000>;
+				lltc,fb-voltage-divider = <127000 200000>;
+				regulator-ramp-delay = <7000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
+			reg_1p8v: sw2 {
+				regulator-name = "vdd1p8";
+				regulator-min-microvolt = <1033310>;
+				regulator-max-microvolt = <2004000>;
+				lltc,fb-voltage-divider = <301000 200000>;
+				regulator-ramp-delay = <7000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* VDD_ARM (1+R1/R2 = 1.635) */
+			reg_vdd_arm: sw3 {
+				regulator-name = "vddarm";
+				regulator-min-microvolt = <674400>;
+				regulator-max-microvolt = <1308000>;
+				lltc,fb-voltage-divider = <127000 200000>;
+				regulator-ramp-delay = <7000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* VDD_DDR (1+R1/R2 = 2.105) */
+			reg_vdd_ddr: sw4 {
+				regulator-name = "vddddr";
+				regulator-min-microvolt = <868310>;
+				regulator-max-microvolt = <1684000>;
+				lltc,fb-voltage-divider = <221000 200000>;
+				regulator-ramp-delay = <7000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
+			reg_2p5v: ldo2 {
+				regulator-name = "vdd2p5";
+				regulator-min-microvolt = <2490375>;
+				regulator-max-microvolt = <2490375>;
+				lltc,fb-voltage-divider = <487000 200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* VDD_HIGH (1+R1/R2 = 4.17) */
+			reg_3p0v: ldo4 {
+				regulator-name = "vdd3p0";
+				regulator-min-microvolt = <3023250>;
+				regulator-max-microvolt = <3023250>;
+				lltc,fb-voltage-divider = <634000 200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};

arch/arm/boot/dts/imx6qdl-gw5904.dtsi new file +309 -0

+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+		wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&ldb {
+	status = "okay";
+
+	lvds-channel at 0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
+			};
+		};
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+	status = "disabled";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+	status = "disabled";
+};
+
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_usb_h1_vbus>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	non-removable;
+	vmmc-supply = <&reg_3p3v>;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+};
+
+&iomuxc {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x4001b0b0 /* PHY_RST# */
+		>;
+	};
+
+	pinctrl_gpio_leds: gpioledsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
+			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
+			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
+			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_0__GPIO1_IO00	0x1b0b0 /* PCIE RST */
+		>;
+	};
+
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_8__GPIO1_IO08	0x1b0b0 /* PMIC_IRQ# */
+		>;
+	};
+
+	pinctrl_pps: ppsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm4: pwm4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
+			MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+			MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+			MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
+			MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
+			MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
+			MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
+		>;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* PWR_EN */
+			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x1b0b0 /* OC */
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+			MX6QDL_PAD_SD3_RST__SD3_RESET		0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
+			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
+			MX6QDL_PAD_SD3_RST__SD3_RESET		0x100b9
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170b9
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170b9
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170b9
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170b9
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
+			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
+			MX6QDL_PAD_SD3_RST__SD3_RESET		0x100f9
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170f9
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170f9
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170f9
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170f9
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT8__WDOG1_B		0x1b0b0
+		>;
+	};
+};

Signature · 1 line

2.7.4