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drivers/fsi: Add more time between clocking and data sampling

PATCH In review Christopher Bostic 3 participants 3 messages Mar 15, 2017 – Mar 17, 2017 FSI

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Christopher Bostic

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#0 lore raw

PATCH 1/1 drivers/fsi: Add more time between clocking and data sampling

Under high work loads the ARM core can occasionaly hit invalid timings between the FSI clock and data lines which leads to data crc errors. Add further delay between clock switch and data line changes.

Signed-off-by Christopher Bostic <[email protected]>
---
 drivers/fsi/fsi-master-gpio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/fsi/fsi-master-gpio.c +4 -4
index a8976d5..a93453f 100644
@@ -13,7 +13,7 @@
 
 #include "fsi-master.h"
 
-#define	FSI_GPIO_STD_DLY	1	/* Standard pin delay in nS */
+#define	FSI_GPIO_STD_DLY	1	/* Standard pin delay in uS */
 #define	FSI_ECHO_DELAY_CLOCKS	16	/* Number clocks for echo delay */
 #define	FSI_PRE_BREAK_CLOCKS	50	/* Number clocks to prep for break */
 #define	FSI_BREAK_CLOCKS	256	/* Number of clocks to issue break */

@@ -86,9 +86,9 @@ static void clock_toggle(struct fsi_master_gpio *master, int count)
 	int i;
 
 	for (i = 0; i < count; i++) {
-		ndelay(FSI_GPIO_STD_DLY);
+		udelay(FSI_GPIO_STD_DLY);
 		gpiod_set_value(master->gpio_clk, 0);
-		ndelay(FSI_GPIO_STD_DLY);
+		udelay(FSI_GPIO_STD_DLY);
 		gpiod_set_value(master->gpio_clk, 1);
 	}
 }

@@ -97,7 +97,7 @@ static int sda_in(struct fsi_master_gpio *master)
 {
 	int in;
 
-	ndelay(FSI_GPIO_STD_DLY);
+	udelay(FSI_GPIO_STD_DLY);
 	in = gpiod_get_value(master->gpio_data);
 	return in ? 1 : 0;
 }
Signature · 1 line
1.8.2.2
Acked-by on v1 1/1
#1 lore raw
Quoted 45 lines · Christopher Bostic

Under high work loads the ARM core can occasionaly hit invalid timings between the FSI clock and data lines which leads to data crc errors. Add further delay between clock switch and data line changes.

Signed-off-by Christopher Bostic <[email protected]>
---
 drivers/fsi/fsi-master-gpio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/fsi/fsi-master-gpio.c +4 -5
index a8976d5..a93453f 100644
@@ -13,7 +13,7 @@
 
 #include "fsi-master.h"
 
-#define        FSI_GPIO_STD_DLY        1       /* Standard pin delay in nS */
+#define        FSI_GPIO_STD_DLY        1       /* Standard pin delay in uS */
 #define        FSI_ECHO_DELAY_CLOCKS   16      /* Number clocks for echo delay */
 #define        FSI_PRE_BREAK_CLOCKS    50      /* Number clocks to prep for break */
 #define        FSI_BREAK_CLOCKS        256     /* Number of clocks to issue break */

@@ -86,9 +86,9 @@ static void clock_toggle(struct fsi_master_gpio *master, int count)
        int i;
 
        for (i = 0; i < count; i++) {
-               ndelay(FSI_GPIO_STD_DLY);
+               udelay(FSI_GPIO_STD_DLY);
                gpiod_set_value(master->gpio_clk, 0);
-               ndelay(FSI_GPIO_STD_DLY);
+               udelay(FSI_GPIO_STD_DLY);
                gpiod_set_value(master->gpio_clk, 1);
        }
 }

@@ -97,7 +97,7 @@ static int sda_in(struct fsi_master_gpio *master)
 {
        int in;
 
-       ndelay(FSI_GPIO_STD_DLY);
+       udelay(FSI_GPIO_STD_DLY);
        in = gpiod_get_value(master->gpio_data);
        return in ? 1 : 0;
 }
--
Quoted 2 lines

1.8.2.2

Acked-by Andrew Geissler <[email protected]>
#2 lore raw
In reply to Christopher Bostic

Hi Chris

Quoted 17 lines · Christopher Bostic

Under high work loads the ARM core can occasionaly hit invalid timings between the FSI clock and data lines which leads to data crc errors. Add further delay between clock switch and data line changes.

Signed-off-by Christopher Bostic <[email protected]>

---
drivers/fsi/fsi-master-gpio.c | 8 ++++----

1 file changed, 4 insertions(+), 4 deletions(-)
drivers/fsi/fsi-master-gpio.c +0 -0
index a8976d5..a93453f 100644

drivers/fsi/fsi-master-gpio.c line 16

Quoted 5 lines
drivers/fsi/fsi-master-gpio.c +1 -1
@@ -13,7 +13,7 @@
 
 #include "fsi-master.h"
 
-#define	FSI_GPIO_STD_DLY	1	/* Standard pin delay in nS */
+#define	FSI_GPIO_STD_DLY	1	/* Standard pin delay in uS */

How did you arrive at 1000x ? Does this mean we spend 1000x spinning the core when sending data out?

I wonder if 100x or even 10x might still get rid of enough of the jitter?

Quoted 26 lines
drivers/fsi/fsi-master-gpio.c +3 -3
 #define	FSI_ECHO_DELAY_CLOCKS	16	/* Number clocks for echo delay */
 #define	FSI_PRE_BREAK_CLOCKS	50	/* Number clocks to prep for break */
 #define	FSI_BREAK_CLOCKS	256	/* Number of clocks to issue break */

@@ -86,9 +86,9 @@ static void clock_toggle(struct fsi_master_gpio *master, int count)
 	int i;
 
 	for (i = 0; i < count; i++) {
-		ndelay(FSI_GPIO_STD_DLY);
+		udelay(FSI_GPIO_STD_DLY);
 		gpiod_set_value(master->gpio_clk, 0);
-		ndelay(FSI_GPIO_STD_DLY);
+		udelay(FSI_GPIO_STD_DLY);
 		gpiod_set_value(master->gpio_clk, 1);
 	}
 }

@@ -97,7 +97,7 @@ static int sda_in(struct fsi_master_gpio *master)
 {
 	int in;
 
-	ndelay(FSI_GPIO_STD_DLY);
+	udelay(FSI_GPIO_STD_DLY);
 	in = gpiod_get_value(master->gpio_data);
 	return in ? 1 : 0;
 }
Signature · 1 line
1.8.2.2

thx - brad