ti: ARM: svc: Question about switching to am57xx HYP mode.

Dear All,

I do have a question regarding switching from SVC to HYP mode on AM57xx SoC.

Just after going out of reset (room bootloader):
------------------------------------------------

Breakpoint 1, _start () at arch/arm/lib/vectors.S:54
54 b reset
(gdb) mo info
Core number : 0
Core state : debug mode (ARM)
Debug entry cause : Breakpoint
Current PC : 0x40300000
Current CPSR : 0x400000d3 (Supervisor)
Current SPSR : 0x00000000
(gdb)

Here the A bit in CPSR is cleared - the "Imprecise Data Abort mask" is disabled.

Then we enter the HYP mode (due to LPAE u-boot support):
Breakpoint 39, switch_to_hypervisor () at arch/arm/cpu/armv7/omap-common/lowlevel_init.S:35

After end of this ASM procedure we got following CPSR for HYP mode:

Breakpoint 41, switch_to_hypervisor_ret () at
arch/arm/cpu/armv7/start.S:57 57 and r1, r0,
#0x1f @ mask mode bits (gdb) mo info
Core number : 0
Core state : debug mode (ARM)
Debug entry cause : Breakpoint
Current PC : 0x4030005c
Current CPSR : 0x000001da (Hyp)
Current SPSR : 0x00000010
(gdb)

And here the A bit "Imprecise Abort Bit" [8] is masked.

Why such operation is performed in the SMC call (which switches to HYP)?

I could try to disable it by hand (cpsie A), but I'm not sure if this has no "side effects".

Best regards,

Lukasz Majewski

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Hi Lukasz,

This seems to be the default behavior in the ROM Code when we do an SMC call which switches to HYP mode.

A, bit[8] Asynchronous abort mask bit.
I, bit[7]
IRQ mask bit.
F, bit[6] FIQ mask bit.

Are set which means they are masked.

From the interaction i had with the ROM code team you can unmask the A bit/bit[8] if needed.

Regards,
Keerthy