Add PPv2.2 support to the mvpp2 ethernet driver and enable it for A7k/8k

PATCH Superseded Stefan Roese 2 participants 57 messages Mar 23, 2017 – Mar 29, 2017

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Network drivers Arm (32-bit) Bitops API

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Stefan Roese

author

2017-03-23 16:01 UTC #0 lore raw

v2 cover Add PPv2.2 support to the mvpp2 ethernet driver and enable it for A7k/8k

This patchset does the following things:

- It brings the latest Linux changes from the mvpp2 ethernet driver done by Thomas Petazzoni to the U-Boot version of this driver. This enables the usage of this driver on the new Marvell Armada 7k / 8k ARMv8 SoCs.

- This driver is enabled for the currently available Armada 7k / 8k boards and the necessary configuration is done to the config header.

v2 status:
The GoP / NetC patch has been split into multiple smaller patches for easier review. The code for untested / unsupported interfaces (like QSGMII, XAUI and RXAUI) has been removed for now.

Thanks,
Stefan

Changes in v2:
- Added Reviewed-by from Tom and Joe
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next, mostly smaller changes, making checkpatch happy.
- New patch
- Fixed small typo in commit text

Stefan Roese (22):
bitops.h: Include bitsperlong.h as needed for GENMASK_ULL
net: mvpp2: Round up top tx buffer boundaries for dcache ops
net: mvpp2: enable building on 64-bit platforms (more U-Boot specific)
net: mvpp2: Add MDIO support for PPv2.2
net: mvpp2: Move probe function from MISC to ETH DM driver
net: mvpp2.c: Clear all buffer / descriptor areas before usage
net: mvpp2: Enable compilation for Armada 7K/8K platforms
arm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driver
net: mvpp2: Handle eth device naming in multi-CP case correctly
net: mvpp2: Add remove function that is called before the OS is
started
net: mvpp2: Add RX and TX FIFO configuration for PPv2.2
net: include/phy.h: Add new PHY interface modes
net: mvpp2: Restructure probe / init functions
net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB
SGMII
net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)
net: mvpp2: Add GoP and NetC support for port 0 (SFI)
net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID
net: mvpp2: Enable PHY polling mode on PPv2.2
net: mvpp2: Configure SMI PHY address needed for PHY polling
net: mvpp2: Remove unreferenced in_use_thresh from struct
mvpp2_bm_pool
arm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G
arm64: mvebu: Enable CONFIG_PHY_MARVELL in Armada7k/8k-DB defconfig

Thomas Petazzoni (23):
net: mvpp2: simplify mvpp2_bm_bufs_add()
net: mvpp2: remove unused register definitions
net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT
net: mvpp2: simplify MVPP2_PRS_RI_* definitions
net: mvpp2: enable building on 64-bit platforms
net: mvpp2: use "dma" instead of "phys" where appropriate
net: mvpp2: remove support for buffer header
net: mvpp2: store physical address of buffer in rx_desc->buf_cookie
net: mvpp2: add and use accessors for TX/RX descriptors
net: mvpp2: add hw_version field in "struct mvpp2"
net: mvpp2: introduce an intermediate union for the TX/RX descriptors
net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors
net: mvpp2: adjust the allocation/free of BM pools for PPv2.2
net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2
net: mvpp2: adapt mvpp2_defaults_set() to PPv2.2
net: mvpp2: adjust mvpp2_{rxq,txq}_init for PPv2.2
net: mvpp2: handle register mapping and access for PPv2.2
net: mvpp2: handle misc PPv2.1/PPv2.2 differences
net: mvpp2: add AXI bridge initialization for PPv2.2
net: mvpp2: rework RXQ interrupt group initialization for PPv2.2
net: mvpp2: adapt rxq distribution to PPv2.2
net: mvpp2: finally add the PPv2.2 compatible string
arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K

 arch/arm/dts/armada-7040-db.dts       |   27 +-
 arch/arm/dts/armada-8040-db.dts       |   16 +
 arch/arm/dts/armada-cp110-master.dtsi |   37 +
 arch/arm/dts/armada-cp110-slave.dtsi  |   37 +
 configs/mvebu_db-88f7040_defconfig    |    3 +-
 configs/mvebu_db-88f8040_defconfig    |    3 +-
 drivers/net/Kconfig                   |    6 +-
 drivers/net/mvpp2.c                   | 2045 ++++++++++++++++++++++++++++-----
 include/configs/mvebu_armada-8k.h     |    8 +
 include/linux/bitops.h                |    1 +
 include/phy.h                         |    6 +
 11 files changed, 1873 insertions(+), 316 deletions(-)

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #1 lore raw

PATCH v2 1/45 bitops.h: Include bitsperlong.h as needed for GENMASK_ULL

The macro GENMASK_ULL needs the BITS_PER_LONG_LONG macro which is defined in the bitsperlong.h header. Lets include this header as the upcoming A7k/8k support in the Marvell mvpp2 ethernet driver uses this macro.

Signed-off-by Stefan Roese <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Reviewed-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Reviewed-by from Tom and Joe

 include/linux/bitops.h | 1 +
 1 file changed, 1 insertion(+)

include/linux/bitops.h +1 -0

index 1b2e4915a0..576b15dc53 100644
@@ -2,6 +2,7 @@
 #define _LINUX_BITOPS_H
 
 #include <asm/types.h>
+#include <asm-generic/bitsperlong.h>
 #include <linux/compiler.h>
 
 #define BIT(nr)			(1UL << (nr))

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #2 lore raw

PATCH v2 2/45 net: mvpp2: Round up top tx buffer boundaries for dcache ops

In reply to Stefan Roese

check_cache_range() warns that the top boundaries are not properly aligned when flushing or invalidating the buffers and make these operations fail.

This gets rid of the warnings:
CACHE: Misaligned operation at range ...

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

drivers/net/mvpp2.c +2 -1

index 88e88b903b..93eb1f2dd4 100644
@@ -3972,7 +3972,8 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
 		| MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
 
 	/* Flush tx data */
-	flush_dcache_range((u32)packet, (u32)packet + length);
+	flush_dcache_range((unsigned long)packet,
+			   (unsigned long)packet + ALIGN(length, PKTALIGN));
 
 	/* Enable transmit */
 	mb();

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #3 lore raw

PATCH v2 3/45 net: mvpp2: simplify mvpp2_bm_bufs_add()

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

The mvpp2_bm_bufs_add() currently creates a fake cookie by calling mvpp2_bm_cookie_pool_set(), just to be able to call mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID.

Instead of doing this convoluted thing, just call mvpp2_bm_pool_put() directly, since we have the BM pool ID.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/net/mvpp2.c +3 -3

index 93eb1f2dd4..365180d456 100644
@@ -2390,7 +2390,6 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 			     struct mvpp2_bm_pool *bm_pool, int buf_num)
 {
 	int i;
-	u32 bm;
 
 	if (buf_num < 0 ||
 	    (buf_num + bm_pool->buf_num > bm_pool->size)) {

@@ -2400,10 +2399,11 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 		return 0;
 	}
 
-	bm = mvpp2_bm_cookie_pool_set(0, bm_pool->id);
 	for (i = 0; i < buf_num; i++) {
-		mvpp2_pool_refill(port, bm, (u32)buffer_loc.rx_buffer[i],
+		mvpp2_bm_pool_put(port, bm_pool->id,
+				  (u32)buffer_loc.rx_buffer[i],
 				  (u32)buffer_loc.rx_buffer[i]);
+
 	}
 
 	/* Update BM driver with number of buffers added to pool */

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #4 lore raw

PATCH v2 4/45 net: mvpp2: remove unused register definitions

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 4 ----
 1 file changed, 4 deletions(-)

drivers/net/mvpp2.c +0 -4

index 365180d456..42df1b7e02 100644
@@ -294,10 +294,6 @@ do {									\
 #define MVPP2_SRC_ADDR_HIGH			0x28
 #define MVPP2_PHY_AN_CFG0_REG			0x34
 #define     MVPP2_PHY_AN_STOP_SMI0_MASK		BIT(7)
-#define MVPP2_MIB_COUNTERS_BASE(port)		(0x1000 + ((port) >> 1) * \
-						0x400 + (port) * 0x400)
-#define     MVPP2_MIB_LATE_COLLISION		0x7c
-#define MVPP2_ISR_SUM_MASK_REG			0x220c
 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG	0x305c
 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT		0x27

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #5 lore raw

PATCH v2 5/45 net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/net/mvpp2.c +1 -1

index 42df1b7e02..74ae1a2d2a 100644
@@ -295,7 +295,7 @@ do {									\
 #define MVPP2_PHY_AN_CFG0_REG			0x34
 #define     MVPP2_PHY_AN_STOP_SMI0_MASK		BIT(7)
 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG	0x305c
-#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT		0x27
+#define     MVPP2_EXT_GLOBAL_CTRL_DEFAULT	0x27
 
 /* Per-port registers */
 #define MVPP2_GMAC_CTRL_0_REG			0x0

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #6 lore raw

PATCH v2 6/45 net: mvpp2: simplify MVPP2_PRS_RI_* definitions

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which doesn't compile nicely on 64-bit. Moreover, those definitions are in fact unneeded, since they are always used in combination with a bit mask that ensures only the appropriate bits are modified.

Therefore, such definitions should just be set to 0x0. In addition, as suggested by Russell King, we change the _MASK definitions to also use the BIT() macro so that it is clear they are related to the values defined afterwards.

For example:

 #define MVPP2_PRS_RI_L2_CAST_MASK              0x600
 #define MVPP2_PRS_RI_L2_UCAST                  ~(BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_MCAST                  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST                  BIT(10)

becomes

 #define MVPP2_PRS_RI_L2_CAST_MASK              (BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_UCAST                  0x0
 #define MVPP2_PRS_RI_L2_MCAST                  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST                  BIT(10)

Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and MVPP2_PRS_RI_L2_BCAST) are always applied with MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)).

It fixes the following warnings when building the driver on a 64-bit platform (which is not possible as of this commit, but will be enabled in a follow-up commit):

drivers/net/ethernet/marvell/mvpp2.c: In function ‘mvpp2_prs_mac_promisc_set’:
drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly truncated to unsigned type [-Woverflow]

 #define MVPP2_PRS_RI_L2_UCAST   ~(BIT(9) | BIT(10))
                                  ^
drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro ‘MVPP2_PRS_RI_L2_UCAST’
     mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

drivers/net/mvpp2.c +8 -8

index 74ae1a2d2a..769680ac45 100644
@@ -572,28 +572,28 @@ enum mvpp2_tag_type {
 /* Sram result info bits assignment */
 #define MVPP2_PRS_RI_MAC_ME_MASK		0x1
 #define MVPP2_PRS_RI_DSA_MASK			0x2
-#define MVPP2_PRS_RI_VLAN_MASK			0xc
-#define MVPP2_PRS_RI_VLAN_NONE			~(BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_MASK			(BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_NONE			0x0
 #define MVPP2_PRS_RI_VLAN_SINGLE		BIT(2)
 #define MVPP2_PRS_RI_VLAN_DOUBLE		BIT(3)
 #define MVPP2_PRS_RI_VLAN_TRIPLE		(BIT(2) | BIT(3))
 #define MVPP2_PRS_RI_CPU_CODE_MASK		0x70
 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC		BIT(4)
-#define MVPP2_PRS_RI_L2_CAST_MASK		0x600
-#define MVPP2_PRS_RI_L2_UCAST			~(BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_CAST_MASK		(BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_UCAST			0x0
 #define MVPP2_PRS_RI_L2_MCAST			BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST			BIT(10)
 #define MVPP2_PRS_RI_PPPOE_MASK			0x800
-#define MVPP2_PRS_RI_L3_PROTO_MASK		0x7000
-#define MVPP2_PRS_RI_L3_UN			~(BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_PROTO_MASK		(BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_UN			0x0
 #define MVPP2_PRS_RI_L3_IP4			BIT(12)
 #define MVPP2_PRS_RI_L3_IP4_OPT			BIT(13)
 #define MVPP2_PRS_RI_L3_IP4_OTHER		(BIT(12) | BIT(13))
 #define MVPP2_PRS_RI_L3_IP6			BIT(14)
 #define MVPP2_PRS_RI_L3_IP6_EXT			(BIT(12) | BIT(14))
 #define MVPP2_PRS_RI_L3_ARP			(BIT(13) | BIT(14))
-#define MVPP2_PRS_RI_L3_ADDR_MASK		0x18000
-#define MVPP2_PRS_RI_L3_UCAST			~(BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_ADDR_MASK		(BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_UCAST			0x0
 #define MVPP2_PRS_RI_L3_MCAST			BIT(15)
 #define MVPP2_PRS_RI_L3_BCAST			(BIT(15) | BIT(16))
 #define MVPP2_PRS_RI_IP_FRAG_MASK		0x20000

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #7 lore raw

PATCH v2 7/45 net: mvpp2: enable building on 64-bit platforms

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

The mvpp2 is going to be extended to support the Marvell Armada 7K/8K platform, which is ARM64. As a preparation to this work, this commit enables building the mvpp2 driver on ARM64, by:

- Adjusting the Kconfig dependency

- Fixing the types used in the driver so that they are 32/64-bits compliant. We use dma_addr_t for DMA addresses, and unsigned long for virtual addresses.

It is worth mentioning that after this commit, the driver is for now still only used on 32-bits platforms, and will only work on 32-bits platforms.

Changed by Stefan for U-Boot:
Removed the Kconfig change as it does not apply to U-Boot this way.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

drivers/net/mvpp2.c +8 -6

index 769680ac45..d5085909e4 100644
@@ -2219,7 +2219,8 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 	if (!bm_pool->virt_addr)
 		return -ENOMEM;
 
-	if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVPP2_BM_POOL_PTR_ALIGN)) {
+	if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
+			MVPP2_BM_POOL_PTR_ALIGN)) {
 		dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
 			bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
 		return -ENOMEM;

@@ -2359,14 +2360,15 @@ static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
 }
 
 /* Get pool number from a BM cookie */
-static inline int mvpp2_bm_cookie_pool_get(u32 cookie)
+static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
 {
 	return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
 }
 
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
-				     u32 buf_phys_addr, u32 buf_virt_addr)
+				     dma_addr_t buf_phys_addr,
+				     unsigned long buf_virt_addr)
 {
 	mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
 	mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);

@@ -2397,8 +2399,8 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 
 	for (i = 0; i < buf_num; i++) {
 		mvpp2_bm_pool_put(port, bm_pool->id,
-				  (u32)buffer_loc.rx_buffer[i],
-				  (u32)buffer_loc.rx_buffer[i]);
+				  (dma_addr_t)buffer_loc.rx_buffer[i],
+				  (unsigned long)buffer_loc.rx_buffer[i]);
 
 	}

@@ -3333,7 +3335,7 @@ static int mvpp2_rx_refill(struct mvpp2_port *port,
 			   struct mvpp2_bm_pool *bm_pool,
 			   u32 bm, u32 phys_addr)
 {
-	mvpp2_pool_refill(port, bm, phys_addr, phys_addr);
+	mvpp2_pool_refill(port, bm, phys_addr, (unsigned long)phys_addr);
 	return 0;
 }

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #8 lore raw

PATCH v2 8/45 net: mvpp2: enable building on 64-bit platforms (more U-Boot specific)

In reply to Stefan Roese

Some more U-Boot specific 64bit support changes, mostly changing u32 to unsigned long.

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

drivers/net/mvpp2.c +15 ~~-10~~

index d5085909e4..82d3ff9c35 100644
@@ -959,7 +959,7 @@ struct mvpp2_bm_pool {
 	int pkt_size;
 
 	/* BPPE virtual base address */
-	u32 *virt_addr;
+	unsigned long *virt_addr;
 	/* BPPE physical base address */
 	dma_addr_t phys_addr;

@@ -1003,8 +1003,8 @@ struct buffer_location {
 	struct mvpp2_tx_desc *aggr_tx_descs;
 	struct mvpp2_tx_desc *tx_descs;
 	struct mvpp2_rx_desc *rx_descs;
-	u32 *bm_pool[MVPP2_BM_POOLS_NUM];
-	u32 *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
+	unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
+	unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
 	int first_rxq;
 };

@@ -3963,8 +3963,8 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
 	tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
 	tx_desc->phys_txq = txq->id;
 	tx_desc->data_size = length;
-	tx_desc->packet_offset = (u32)packet & MVPP2_TX_DESC_ALIGN;
-	tx_desc->buf_phys_addr = (u32)packet & ~MVPP2_TX_DESC_ALIGN;
+	tx_desc->packet_offset = (unsigned long)packet & MVPP2_TX_DESC_ALIGN;
+	tx_desc->buf_phys_addr = (unsigned long)packet & ~MVPP2_TX_DESC_ALIGN;
 	/* First and Last descriptor */
 	tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
 		| MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;

@@ -4088,24 +4088,29 @@ static int mvpp2_base_probe(struct udevice *dev)
 
 	/* Align buffer area for descs and rx_buffers to 1MiB */
 	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
-	mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
+	mmu_set_region_dcache_behaviour((unsigned long)bd_space,
+					BD_SPACE, DCACHE_OFF);
 
 	buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
 	size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
 
-	buffer_loc.tx_descs = (struct mvpp2_tx_desc *)((u32)bd_space + size);
+	buffer_loc.tx_descs =
+		(struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
 	size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
 
-	buffer_loc.rx_descs = (struct mvpp2_rx_desc *)((u32)bd_space + size);
+	buffer_loc.rx_descs =
+		(struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
 	size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
 
 	for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
-		buffer_loc.bm_pool[i] = (u32 *)((u32)bd_space + size);
+		buffer_loc.bm_pool[i] =
+			(unsigned long *)((unsigned long)bd_space + size);
 		size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32);
 	}
 
 	for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
-		buffer_loc.rx_buffer[i] = (u32 *)((u32)bd_space + size);
+		buffer_loc.rx_buffer[i] =
+			(unsigned long *)((unsigned long)bd_space + size);
 		size += RX_BUFFER_SIZE;
 	}

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #9 lore raw

PATCH v2 9/45 net: mvpp2: use "dma" instead of "phys" where appropriate

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

As indicated by Russell King, the mvpp2 driver currently uses a lot "phys" or "phys_addr" to store what really is a DMA address. This commit clarifies this by using "dma" or "dma_addr" where appropriate.

This is especially important as we are going to introduce more changes where the distinction between physical address and DMA address will be key.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 61 +++++++++++++++++++++++++++--------------------------
 1 file changed, 31 insertions(+), 30 deletions(-)

drivers/net/mvpp2.c +31 ~~-30~~

index 82d3ff9c35..53ddb330e9 100644
@@ -799,7 +799,7 @@ struct mvpp2_tx_desc {
 	u8  packet_offset;	/* the offset from the buffer beginning	*/
 	u8  phys_txq;		/* destination queue ID			*/
 	u16 data_size;		/* data size of transmitted packet in bytes */
-	u32 buf_phys_addr;	/* physical addr of transmitted buffer	*/
+	u32 buf_dma_addr;	/* physical addr of transmitted buffer	*/
 	u32 buf_cookie;		/* cookie for access to TX buffer in tx path */
 	u32 reserved1[3];	/* hw_cmd (for future use, BM, PON, PNC) */
 	u32 reserved2;		/* reserved (for future use)		*/

@@ -809,7 +809,7 @@ struct mvpp2_rx_desc {
 	u32 status;		/* info about received packet		*/
 	u16 reserved1;		/* parser_info (for future use, PnC)	*/
 	u16 data_size;		/* size of received packet in bytes	*/
-	u32 buf_phys_addr;	/* physical address of the buffer	*/
+	u32 buf_dma_addr;	/* physical address of the buffer	*/
 	u32 buf_cookie;		/* cookie for access to RX buffer in rx path */
 	u16 reserved2;		/* gem_port_id (for future use, PON)	*/
 	u16 reserved3;		/* csum_l4 (for future use, PnC)	*/

@@ -864,7 +864,7 @@ struct mvpp2_tx_queue {
 	struct mvpp2_tx_desc *descs;
 
 	/* DMA address of the Tx DMA descriptors array */
-	dma_addr_t descs_phys;
+	dma_addr_t descs_dma;
 
 	/* Index of the last Tx DMA descriptor */
 	int last_desc;

@@ -887,7 +887,7 @@ struct mvpp2_rx_queue {
 	struct mvpp2_rx_desc *descs;
 
 	/* DMA address of the RX DMA descriptors array */
-	dma_addr_t descs_phys;
+	dma_addr_t descs_dma;
 
 	/* Index of the last RX DMA descriptor */
 	int last_desc;

@@ -960,8 +960,8 @@ struct mvpp2_bm_pool {
 
 	/* BPPE virtual base address */
 	unsigned long *virt_addr;
-	/* BPPE physical base address */
-	dma_addr_t phys_addr;
+	/* BPPE DMA base address */
+	dma_addr_t dma_addr;
 
 	/* Ports using BM pool */
 	u32 port_map;

@@ -971,7 +971,7 @@ struct mvpp2_bm_pool {
 };
 
 struct mvpp2_buff_hdr {
-	u32 next_buff_phys_addr;
+	u32 next_buff_dma_addr;
 	u32 next_buff_virt_addr;
 	u16 byte_count;
 	u16 info;

@@ -2215,7 +2215,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 	u32 val;
 
 	bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
-	bm_pool->phys_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
+	bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
 	if (!bm_pool->virt_addr)
 		return -ENOMEM;

@@ -2227,7 +2227,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 	}
 
 	mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
-		    bm_pool->phys_addr);
+		    bm_pool->dma_addr);
 	mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 
 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));

@@ -2367,20 +2367,21 @@ static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
 
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
-				     dma_addr_t buf_phys_addr,
+				     dma_addr_t buf_dma_addr,
 				     unsigned long buf_virt_addr)
 {
 	mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
-	mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
+	mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
 }
 
 /* Refill BM pool */
 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
-			      u32 phys_addr, u32 cookie)
+			      dma_addr_t dma_addr,
+			      u32 cookie)
 {
 	int pool = mvpp2_bm_cookie_pool_get(bm);
 
-	mvpp2_bm_pool_put(port, pool, phys_addr, cookie);
+	mvpp2_bm_pool_put(port, pool, dma_addr, cookie);
 }
 
 /* Allocate buffers for the pool */

@@ -2944,7 +2945,7 @@ static int mvpp2_aggr_txq_init(struct udevice *dev,
 {
 	/* Allocate memory for TX descriptors */
 	aggr_txq->descs = buffer_loc.aggr_tx_descs;
-	aggr_txq->descs_phys = (dma_addr_t)buffer_loc.aggr_tx_descs;
+	aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
 	if (!aggr_txq->descs)
 		return -ENOMEM;

@@ -2961,7 +2962,7 @@ static int mvpp2_aggr_txq_init(struct udevice *dev,
 	/* Set Tx descriptors queue starting address */
 	/* indirect access */
 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
-		    aggr_txq->descs_phys);
+		    aggr_txq->descs_dma);
 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
 
 	return 0;

@@ -2976,7 +2977,7 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
 
 	/* Allocate memory for RX descriptors */
 	rxq->descs = buffer_loc.rx_descs;
-	rxq->descs_phys = (dma_addr_t)buffer_loc.rx_descs;
+	rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
 	if (!rxq->descs)
 		return -ENOMEM;

@@ -2990,7 +2991,7 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
 
 	/* Set Rx descriptors queue starting address - indirect access */
 	mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
-	mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys);
+	mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_dma);
 	mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
 	mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);

@@ -3017,7 +3018,7 @@ static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
 		struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
 		u32 bm = mvpp2_bm_cookie_build(rx_desc);
 
-		mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
+		mvpp2_pool_refill(port, bm, rx_desc->buf_dma_addr,
 				  rx_desc->buf_cookie);
 	}
 	mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);

@@ -3032,7 +3033,7 @@ static void mvpp2_rxq_deinit(struct mvpp2_port *port,
 	rxq->descs             = NULL;
 	rxq->last_desc         = 0;
 	rxq->next_desc_to_proc = 0;
-	rxq->descs_phys        = 0;
+	rxq->descs_dma         = 0;
 
 	/* Clear Rx descriptors queue starting address and size;
 	 * free descriptor number

@@ -3055,7 +3056,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
 
 	/* Allocate memory for Tx descriptors */
 	txq->descs = buffer_loc.tx_descs;
-	txq->descs_phys = (dma_addr_t)buffer_loc.tx_descs;
+	txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
 	if (!txq->descs)
 		return -ENOMEM;

@@ -3067,7 +3068,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
 
 	/* Set Tx descriptors queue starting address - indirect access */
 	mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
-	mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys);
+	mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
 	mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
 					     MVPP2_TXQ_DESC_SIZE_MASK);
 	mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);

@@ -3119,7 +3120,7 @@ static void mvpp2_txq_deinit(struct mvpp2_port *port,
 	txq->descs             = NULL;
 	txq->last_desc         = 0;
 	txq->next_desc_to_proc = 0;
-	txq->descs_phys        = 0;
+	txq->descs_dma         = 0;
 
 	/* Set minimum bandwidth for disabled TXQs */
 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);

@@ -3333,9 +3334,9 @@ static void mvpp2_rx_error(struct mvpp2_port *port,
 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
 static int mvpp2_rx_refill(struct mvpp2_port *port,
 			   struct mvpp2_bm_pool *bm_pool,
-			   u32 bm, u32 phys_addr)
+			   u32 bm, dma_addr_t dma_addr)
 {
-	mvpp2_pool_refill(port, bm, phys_addr, (unsigned long)phys_addr);
+	mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
 	return 0;
 }

@@ -3854,7 +3855,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	struct mvpp2_port *port = dev_get_priv(dev);
 	struct mvpp2_rx_desc *rx_desc;
 	struct mvpp2_bm_pool *bm_pool;
-	dma_addr_t phys_addr;
+	dma_addr_t dma_addr;
 	u32 bm, rx_status;
 	int pool, rx_bytes, err;
 	int rx_received;

@@ -3885,7 +3886,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	rx_desc = mvpp2_rxq_next_desc_get(rxq);
 	rx_status = rx_desc->status;
 	rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE;
-	phys_addr = rx_desc->buf_phys_addr;
+	dma_addr = rx_desc->buf_dma_addr;
 
 	bm = mvpp2_bm_cookie_build(rx_desc);
 	pool = mvpp2_bm_cookie_pool_get(bm);

@@ -3903,12 +3904,12 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
 		mvpp2_rx_error(port, rx_desc);
 		/* Return the buffer to the pool */
-		mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
+		mvpp2_pool_refill(port, bm, rx_desc->buf_dma_addr,
 				  rx_desc->buf_cookie);
 		return 0;
 	}
 
-	err = mvpp2_rx_refill(port, bm_pool, bm, phys_addr);
+	err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
 	if (err) {
 		netdev_err(port->dev, "failed to refill BM pools\n");
 		return 0;

@@ -3919,7 +3920,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	mvpp2_rxq_status_update(port, rxq->id, 1, 1);
 
 	/* give packet to stack - skip on first n bytes */
-	data = (u8 *)phys_addr + 2 + 32;
+	data = (u8 *)dma_addr + 2 + 32;
 
 	if (rx_bytes <= 0)
 		return 0;

@@ -3964,7 +3965,7 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
 	tx_desc->phys_txq = txq->id;
 	tx_desc->data_size = length;
 	tx_desc->packet_offset = (unsigned long)packet & MVPP2_TX_DESC_ALIGN;
-	tx_desc->buf_phys_addr = (unsigned long)packet & ~MVPP2_TX_DESC_ALIGN;
+	tx_desc->buf_dma_addr = (unsigned long)packet & ~MVPP2_TX_DESC_ALIGN;
 	/* First and Last descriptor */
 	tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
 		| MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #10 lore raw

PATCH v2 10/45 net: mvpp2: remove support for buffer header

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next, mostly smaller changes, making checkpatch happy.

 drivers/net/mvpp2.c | 20 --------------------
 1 file changed, 20 deletions(-)

drivers/net/mvpp2.c +0 ~~-20~~

index 53ddb330e9..90ab6d718b 100644
@@ -970,22 +970,6 @@ struct mvpp2_bm_pool {
 	int in_use_thresh;
 };
 
-struct mvpp2_buff_hdr {
-	u32 next_buff_dma_addr;
-	u32 next_buff_virt_addr;
-	u16 byte_count;
-	u16 info;
-	u8  reserved1;		/* bm_qset (for future use, BM)		*/
-};
-
-/* Buffer header info bits */
-#define MVPP2_B_HDR_INFO_MC_ID_MASK	0xfff
-#define MVPP2_B_HDR_INFO_MC_ID(info)	((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
-#define MVPP2_B_HDR_INFO_LAST_OFFS	12
-#define MVPP2_B_HDR_INFO_LAST_MASK	BIT(12)
-#define MVPP2_B_HDR_INFO_IS_LAST(info) \
-	   ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
-
 /* Static declaractions */
 
 /* Number of RXQs used by single port */

@@ -3892,10 +3876,6 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	pool = mvpp2_bm_cookie_pool_get(bm);
 	bm_pool = &port->priv->bm_pools[pool];
 
-	/* Check if buffer header is used */
-	if (rx_status & MVPP2_RXD_BUF_HDR)
-		return 0;
-
 	/* In case of an error, release the requested buffer pointer
 	 * to the Buffer Manager. This request process is controlled
 	 * by the hardware, and the information about the buffer is

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #11 lore raw

PATCH v2 11/45 net: mvpp2: store physical address of buffer in rx_desc->buf_cookie

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

drivers/net/mvpp2.c +9 -4

index 90ab6d718b..17ce0e9f7d 100644
@@ -2352,20 +2352,25 @@ static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 				     dma_addr_t buf_dma_addr,
-				     unsigned long buf_virt_addr)
+				     unsigned long buf_phys_addr)
 {
-	mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
+	/* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
+	 * returned in the "cookie" field of the RX
+	 * descriptor. Instead of storing the virtual address, we
+	 * store the physical address
+	 */
+	mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
 	mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
 }
 
 /* Refill BM pool */
 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
 			      dma_addr_t dma_addr,
-			      u32 cookie)
+			      phys_addr_t phys_addr)
 {
 	int pool = mvpp2_bm_cookie_pool_get(bm);
 
-	mvpp2_bm_pool_put(port, pool, dma_addr, cookie);
+	mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
 }
 
 /* Allocate buffers for the pool */

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #12 lore raw

PATCH v2 12/45 net: mvpp2: add and use accessors for TX/RX descriptors

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

The PPv2.2 IP has a different TX and RX descriptor layout compared to PPv2.1. In order to prepare for the introduction of PPv2.2 support in mvpp2, this commit adds accessors for the different fields of the TX and RX descriptors, and changes the code to use them.

For now, the mvpp2_port argument passed to the accessors is not used, but it will be used in follow-up to update the descriptor according to the version of the IP being used.

Apart from the mechanical changes to use the newly introduced accessors, a few other changes, needed to use the accessors, are made:

- The mvpp2_txq_inc_put() function now takes a mvpp2_port as first argument, as it is needed to use the accessors.

- Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first argument, for the same reason.

- In mvpp2_rx_error(), instead of accessing the RX descriptor in each case of the switch, we introduce a local variable to store the packet size.

- Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie" variable to store the RX descriptor cookie, rather than accessing it from the descriptor each time.

- In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the packet size from the TX descriptor, we use the actual value available in the function, which is used to set the TX descriptor packet size a few lines before.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 118 +++++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 93 insertions(+), 25 deletions(-)

drivers/net/mvpp2.c +93 ~~-25~~

index 17ce0e9f7d..d199eafe30 100644
@@ -1016,6 +1016,65 @@ static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
 	return readl(priv->base + offset);
 }
 
+static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
+				      struct mvpp2_tx_desc *tx_desc,
+				      dma_addr_t dma_addr)
+{
+	tx_desc->buf_dma_addr = dma_addr;
+}
+
+static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
+				  struct mvpp2_tx_desc *tx_desc,
+				  size_t size)
+{
+	tx_desc->data_size = size;
+}
+
+static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
+				 struct mvpp2_tx_desc *tx_desc,
+				 unsigned int txq)
+{
+	tx_desc->phys_txq = txq;
+}
+
+static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
+				 struct mvpp2_tx_desc *tx_desc,
+				 unsigned int command)
+{
+	tx_desc->command = command;
+}
+
+static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
+				    struct mvpp2_tx_desc *tx_desc,
+				    unsigned int offset)
+{
+	tx_desc->packet_offset = offset;
+}
+
+static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
+					    struct mvpp2_rx_desc *rx_desc)
+{
+	return rx_desc->buf_dma_addr;
+}
+
+static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
+					     struct mvpp2_rx_desc *rx_desc)
+{
+	return rx_desc->buf_cookie;
+}
+
+static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
+				    struct mvpp2_rx_desc *rx_desc)
+{
+	return rx_desc->data_size;
+}
+
+static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
+				   struct mvpp2_rx_desc *rx_desc)
+{
+	return rx_desc->status;
+}
+
 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
 {
 	txq_pcpu->txq_get_index++;

@@ -2779,11 +2838,15 @@ static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
 }
 
 /* Obtain BM cookie information from descriptor */
-static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc)
+static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
+				 struct mvpp2_rx_desc *rx_desc)
 {
-	int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >>
-		   MVPP2_RXD_BM_POOL_ID_OFFS;
 	int cpu = smp_processor_id();
+	int pool;
+
+	pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
+		MVPP2_RXD_BM_POOL_ID_MASK) >>
+		MVPP2_RXD_BM_POOL_ID_OFFS;
 
 	return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
 	       ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);

@@ -3005,10 +3068,11 @@ static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
 
 	for (i = 0; i < rx_received; i++) {
 		struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
-		u32 bm = mvpp2_bm_cookie_build(rx_desc);
+		u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
 
-		mvpp2_pool_refill(port, bm, rx_desc->buf_dma_addr,
-				  rx_desc->buf_cookie);
+		mvpp2_pool_refill(port, bm,
+				  mvpp2_rxdesc_dma_addr_get(port, rx_desc),
+				  mvpp2_rxdesc_cookie_get(port, rx_desc));
 	}
 	mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
 }

@@ -3302,20 +3366,21 @@ static void mvpp2_link_event(struct mvpp2_port *port)
 static void mvpp2_rx_error(struct mvpp2_port *port,
 			   struct mvpp2_rx_desc *rx_desc)
 {
-	u32 status = rx_desc->status;
+	u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
+	size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
 
 	switch (status & MVPP2_RXD_ERR_CODE_MASK) {
 	case MVPP2_RXD_ERR_CRC:
-		netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n",
-			   status, rx_desc->data_size);
+		netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
+			   status, sz);
 		break;
 	case MVPP2_RXD_ERR_OVERRUN:
-		netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n",
-			   status, rx_desc->data_size);
+		netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
+			   status, sz);
 		break;
 	case MVPP2_RXD_ERR_RESOURCE:
-		netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n",
-			   status, rx_desc->data_size);
+		netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
+			   status, sz);
 		break;
 	}
 }

@@ -3873,11 +3938,12 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 		return 0;
 
 	rx_desc = mvpp2_rxq_next_desc_get(rxq);
-	rx_status = rx_desc->status;
-	rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE;
-	dma_addr = rx_desc->buf_dma_addr;
+	rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
+	rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
+	rx_bytes -= MVPP2_MH_SIZE;
+	dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
 
-	bm = mvpp2_bm_cookie_build(rx_desc);
+	bm = mvpp2_bm_cookie_build(port, rx_desc);
 	pool = mvpp2_bm_cookie_pool_get(bm);
 	bm_pool = &port->priv->bm_pools[pool];

@@ -3889,8 +3955,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
 		mvpp2_rx_error(port, rx_desc);
 		/* Return the buffer to the pool */
-		mvpp2_pool_refill(port, bm, rx_desc->buf_dma_addr,
-				  rx_desc->buf_cookie);
+		mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
 		return 0;
 	}

@@ -3947,13 +4012,16 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
 
 	/* Get a descriptor for the first part of the packet */
 	tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
-	tx_desc->phys_txq = txq->id;
-	tx_desc->data_size = length;
-	tx_desc->packet_offset = (unsigned long)packet & MVPP2_TX_DESC_ALIGN;
-	tx_desc->buf_dma_addr = (unsigned long)packet & ~MVPP2_TX_DESC_ALIGN;
+	mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
+	mvpp2_txdesc_size_set(port, tx_desc, length);
+	mvpp2_txdesc_offset_set(port, tx_desc,
+				(dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
+	mvpp2_txdesc_dma_addr_set(port, tx_desc,
+				  (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
 	/* First and Last descriptor */
-	tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
-		| MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
+	mvpp2_txdesc_cmd_set(port, tx_desc,
+			     MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
+			     | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
 
 	/* Flush tx data */
 	flush_dcache_range((unsigned long)packet,

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #13 lore raw

PATCH v2 13/45 net: mvpp2: add hw_version field in "struct mvpp2"

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

In preparation to the introduction for the support of PPv2.2 in the mvpp2 driver, this commit adds a hw_version field to the struct mvpp2, and uses the .data field of the DT match table to fill it in.

Having the MVPP21 and MVPP22 definitions available will allow to start adding the necessary conditional code to support PPv2.2.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

drivers/net/mvpp2.c +10 -1

index d199eafe30..9683439d23 100644
@@ -707,6 +707,9 @@ struct mvpp2 {
 	/* Tclk value */
 	u32 tclk;
 
+	/* HW version */
+	enum { MVPP21, MVPP22 } hw_version;
+
 	struct mii_dev *bus;
 };

@@ -4132,6 +4135,9 @@ static int mvpp2_base_probe(struct udevice *dev)
 	u32 size = 0;
 	int i;
 
+	/* Save hw-version */
+	priv->hw_version = dev_get_driver_data(dev);
+
 	/*
 	 * U-Boot special buffer handling:
 	 *

@@ -4234,7 +4240,10 @@ static int mvpp2_base_bind(struct udevice *parent)
 }
 
 static const struct udevice_id mvpp2_ids[] = {
-	{ .compatible = "marvell,armada-375-pp2" },
+	{
+		.compatible = "marvell,armada-375-pp2",
+		.data = MVPP21,
+	},
 	{ }
 };

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #14 lore raw

PATCH v2 14/45 net: mvpp2: introduce an intermediate union for the TX/RX descriptors

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

Since the format of the HW descriptors is different between PPv2.1 and PPv2.2, this commit introduces an intermediate union, with for now only the PPv2.1 descriptors. The bulk of the driver code only manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the descriptors can only be accessed and modified through the accessor functions. A follow-up commit will add the descriptor definitions for PPv2.2.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 39 ++++++++++++++++++++++++++++-----------
 1 file changed, 28 insertions(+), 11 deletions(-)

drivers/net/mvpp2.c +28 ~~-11~~

index 9683439d23..f063b04e43 100644
@@ -797,7 +797,8 @@ struct mvpp2_port {
 #define MVPP2_RXD_L3_IP6		BIT(30)
 #define MVPP2_RXD_BUF_HDR		BIT(31)
 
-struct mvpp2_tx_desc {
+/* HW TX descriptor for PPv2.1 */
+struct mvpp21_tx_desc {
 	u32 command;		/* Options used by HW for packet transmitting.*/
 	u8  packet_offset;	/* the offset from the buffer beginning	*/
 	u8  phys_txq;		/* destination queue ID			*/

@@ -808,7 +809,8 @@ struct mvpp2_tx_desc {
 	u32 reserved2;		/* reserved (for future use)		*/
 };
 
-struct mvpp2_rx_desc {
+/* HW RX descriptor for PPv2.1 */
+struct mvpp21_rx_desc {
 	u32 status;		/* info about received packet		*/
 	u16 reserved1;		/* parser_info (for future use, PnC)	*/
 	u16 data_size;		/* size of received packet in bytes	*/

@@ -823,6 +825,21 @@ struct mvpp2_rx_desc {
 	u32 reserved8;
 };
 
+/* Opaque type used by the driver to manipulate the HW TX and RX
+ * descriptors
+ */
+struct mvpp2_tx_desc {
+	union {
+		struct mvpp21_tx_desc pp21;
+	};
+};
+
+struct mvpp2_rx_desc {
+	union {
+		struct mvpp21_rx_desc pp21;
+	};
+};
+
 /* Per-CPU Tx queue control */
 struct mvpp2_txq_pcpu {
 	int cpu;

@@ -1023,59 +1040,59 @@ static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
 				      struct mvpp2_tx_desc *tx_desc,
 				      dma_addr_t dma_addr)
 {
-	tx_desc->buf_dma_addr = dma_addr;
+	tx_desc->pp21.buf_dma_addr = dma_addr;
 }
 
 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
 				  struct mvpp2_tx_desc *tx_desc,
 				  size_t size)
 {
-	tx_desc->data_size = size;
+	tx_desc->pp21.data_size = size;
 }
 
 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
 				 struct mvpp2_tx_desc *tx_desc,
 				 unsigned int txq)
 {
-	tx_desc->phys_txq = txq;
+	tx_desc->pp21.phys_txq = txq;
 }
 
 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
 				 struct mvpp2_tx_desc *tx_desc,
 				 unsigned int command)
 {
-	tx_desc->command = command;
+	tx_desc->pp21.command = command;
 }
 
 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
 				    struct mvpp2_tx_desc *tx_desc,
 				    unsigned int offset)
 {
-	tx_desc->packet_offset = offset;
+	tx_desc->pp21.packet_offset = offset;
 }
 
 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
 					    struct mvpp2_rx_desc *rx_desc)
 {
-	return rx_desc->buf_dma_addr;
+	return rx_desc->pp21.buf_dma_addr;
 }
 
 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
 					     struct mvpp2_rx_desc *rx_desc)
 {
-	return rx_desc->buf_cookie;
+	return rx_desc->pp21.buf_cookie;
 }
 
 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
 				    struct mvpp2_rx_desc *rx_desc)
 {
-	return rx_desc->data_size;
+	return rx_desc->pp21.data_size;
 }
 
 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
 				   struct mvpp2_rx_desc *rx_desc)
 {
-	return rx_desc->status;
+	return rx_desc->pp21.status;
 }
 
 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #15 lore raw

PATCH v2 15/45 net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

This commit adds the definition of the PPv2.2 HW descriptors, adjusts the mvpp2_tx_desc and mvpp2_rx_desc structures accordingly, and adapts the accessors to work on both PPv2.1 and PPv2.2.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next, mostly smaller changes, making checkpatch happy.

 drivers/net/mvpp2.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 64 insertions(+), 9 deletions(-)

drivers/net/mvpp2.c +64 -9

index f063b04e43..605c8bcd70 100644
@@ -825,18 +825,42 @@ struct mvpp21_rx_desc {
 	u32 reserved8;
 };
 
+/* HW TX descriptor for PPv2.2 */
+struct mvpp22_tx_desc {
+	u32 command;
+	u8  packet_offset;
+	u8  phys_txq;
+	u16 data_size;
+	u64 reserved1;
+	u64 buf_dma_addr_ptp;
+	u64 buf_cookie_misc;
+};
+
+/* HW RX descriptor for PPv2.2 */
+struct mvpp22_rx_desc {
+	u32 status;
+	u16 reserved1;
+	u16 data_size;
+	u32 reserved2;
+	u32 reserved3;
+	u64 buf_dma_addr_key_hash;
+	u64 buf_cookie_misc;
+};
+
 /* Opaque type used by the driver to manipulate the HW TX and RX
  * descriptors
  */
 struct mvpp2_tx_desc {
 	union {
 		struct mvpp21_tx_desc pp21;
+		struct mvpp22_tx_desc pp22;
 	};
 };
 
 struct mvpp2_rx_desc {
 	union {
 		struct mvpp21_rx_desc pp21;
+		struct mvpp22_rx_desc pp22;
 	};
 };

@@ -1040,59 +1064,90 @@ static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
 				      struct mvpp2_tx_desc *tx_desc,
 				      dma_addr_t dma_addr)
 {
-	tx_desc->pp21.buf_dma_addr = dma_addr;
+	if (port->priv->hw_version == MVPP21) {
+		tx_desc->pp21.buf_dma_addr = dma_addr;
+	} else {
+		u64 val = (u64)dma_addr;
+
+		tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
+		tx_desc->pp22.buf_dma_addr_ptp |= val;
+	}
 }
 
 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
 				  struct mvpp2_tx_desc *tx_desc,
 				  size_t size)
 {
-	tx_desc->pp21.data_size = size;
+	if (port->priv->hw_version == MVPP21)
+		tx_desc->pp21.data_size = size;
+	else
+		tx_desc->pp22.data_size = size;
 }
 
 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
 				 struct mvpp2_tx_desc *tx_desc,
 				 unsigned int txq)
 {
-	tx_desc->pp21.phys_txq = txq;
+	if (port->priv->hw_version == MVPP21)
+		tx_desc->pp21.phys_txq = txq;
+	else
+		tx_desc->pp22.phys_txq = txq;
 }
 
 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
 				 struct mvpp2_tx_desc *tx_desc,
 				 unsigned int command)
 {
-	tx_desc->pp21.command = command;
+	if (port->priv->hw_version == MVPP21)
+		tx_desc->pp21.command = command;
+	else
+		tx_desc->pp22.command = command;
 }
 
 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
 				    struct mvpp2_tx_desc *tx_desc,
 				    unsigned int offset)
 {
-	tx_desc->pp21.packet_offset = offset;
+	if (port->priv->hw_version == MVPP21)
+		tx_desc->pp21.packet_offset = offset;
+	else
+		tx_desc->pp22.packet_offset = offset;
 }
 
 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
 					    struct mvpp2_rx_desc *rx_desc)
 {
-	return rx_desc->pp21.buf_dma_addr;
+	if (port->priv->hw_version == MVPP21)
+		return rx_desc->pp21.buf_dma_addr;
+	else
+		return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
 }
 
 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
 					     struct mvpp2_rx_desc *rx_desc)
 {
-	return rx_desc->pp21.buf_cookie;
+	if (port->priv->hw_version == MVPP21)
+		return rx_desc->pp21.buf_cookie;
+	else
+		return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
 }
 
 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
 				    struct mvpp2_rx_desc *rx_desc)
 {
-	return rx_desc->pp21.data_size;
+	if (port->priv->hw_version == MVPP21)
+		return rx_desc->pp21.data_size;
+	else
+		return rx_desc->pp22.data_size;
 }
 
 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
 				   struct mvpp2_rx_desc *rx_desc)
 {
-	return rx_desc->pp21.status;
+	if (port->priv->hw_version == MVPP21)
+		return rx_desc->pp21.status;
+	else
+		return rx_desc->pp22.status;
 }
 
 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #16 lore raw

PATCH v2 16/45 net: mvpp2: adjust the allocation/free of BM pools for PPv2.2

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

This commit adjusts the allocation and freeing of BM pools to support PPv2.2. This involves:

- Checking that the number of buffer pointers is a multiple of 16, as required by the hardware.

- Adjusting the size of the DMA coherent area allocated for buffer pointers. Indeed, PPv2.2 needs space for 2 pointers of 64-bits per buffer, as opposed to 2 pointers of 32-bits per buffer in PPv2.1. The size in bytes is now stored in a new field of the mvpp2_bm_pool structure.

- On PPv2.2, getting the physical and virtual address of each buffer requires reading the MVPP2_BM_ADDR_HIGH_ALLOC to get the high order bits of those addresses. A new utility function mvpp2_bm_bufs_get_addrs() is introduced to handle this.

- On PPv2.2, releasing a buffer requires writing the high order 32 bits of the physical address to MVPP2_BM_PHY_VIRT_HIGH_RLS_REG. We no longer need to write the virtual address to MVPP2_BM_VIRT_RLS_REG.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 39 ++++++++++++++++++++++++++++++++++++---
 1 file changed, 36 insertions(+), 3 deletions(-)

drivers/net/mvpp2.c +36 -3

index 605c8bcd70..4f4e6749dc 100644
@@ -251,14 +251,23 @@ do {									\
 #define MVPP2_BM_PHY_ALLOC_REG(pool)		(0x6400 + ((pool) * 4))
 #define     MVPP2_BM_PHY_ALLOC_GRNTD_MASK	BIT(0)
 #define MVPP2_BM_VIRT_ALLOC_REG			0x6440
+#define MVPP2_BM_ADDR_HIGH_ALLOC		0x6444
+#define     MVPP2_BM_ADDR_HIGH_PHYS_MASK	0xff
+#define     MVPP2_BM_ADDR_HIGH_VIRT_MASK	0xff00
+#define     MVPP2_BM_ADDR_HIGH_VIRT_SHIFT	8
 #define MVPP2_BM_PHY_RLS_REG(pool)		(0x6480 + ((pool) * 4))
 #define     MVPP2_BM_PHY_RLS_MC_BUFF_MASK	BIT(0)
 #define     MVPP2_BM_PHY_RLS_PRIO_EN_MASK	BIT(1)
 #define     MVPP2_BM_PHY_RLS_GRNTD_MASK		BIT(2)
 #define MVPP2_BM_VIRT_RLS_REG			0x64c0
-#define MVPP2_BM_MC_RLS_REG			0x64c4
+#define MVPP21_BM_MC_RLS_REG			0x64c4
 #define     MVPP2_BM_MC_ID_MASK			0xfff
 #define     MVPP2_BM_FORCE_RELEASE_MASK		BIT(12)
+#define MVPP22_BM_ADDR_HIGH_RLS_REG		0x64c4
+#define     MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK	0xff
+#define	    MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK	0xff00
+#define     MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT	8
+#define MVPP22_BM_MC_RLS_REG			0x64d4
 
 /* TX Scheduler registers */
 #define MVPP2_TXP_SCHED_PORT_INDEX_REG		0x8000

@@ -2332,6 +2341,12 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 {
 	u32 val;
 
+	/* Number of buffer pointers must be a multiple of 16, as per
+	 * hardware constraints
+	 */
+	if (!IS_ALIGNED(size, 16))
+		return -EINVAL;
+
 	bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
 	bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
 	if (!bm_pool->virt_addr)

@@ -2345,7 +2360,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 	}
 
 	mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
-		    bm_pool->dma_addr);
+		    lower_32_bits(bm_pool->dma_addr));
 	mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 
 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));

@@ -2488,6 +2503,21 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 				     dma_addr_t buf_dma_addr,
 				     unsigned long buf_phys_addr)
 {
+	if (port->priv->hw_version == MVPP22) {
+		u32 val = 0;
+
+		if (sizeof(dma_addr_t) == 8)
+			val |= upper_32_bits(buf_dma_addr) &
+				MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
+
+		if (sizeof(phys_addr_t) == 8)
+			val |= (upper_32_bits(buf_phys_addr)
+				<< MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
+				MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
+
+		mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
+	}
+
 	/* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
 	 * returned in the "cookie" field of the RX
 	 * descriptor. Instead of storing the virtual address, we

@@ -4237,7 +4267,10 @@ static int mvpp2_base_probe(struct udevice *dev)
 	for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
 		buffer_loc.bm_pool[i] =
 			(unsigned long *)((unsigned long)bd_space + size);
-		size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32);
+		if (priv->hw_version == MVPP21)
+			size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
+		else
+			size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
 	}
 
 	for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #17 lore raw

PATCH v2 17/45 net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

The MVPP2_RXQ_CONFIG_REG register has a slightly different layout between PPv2.1 and PPv2.2, so this commit adapts the functions modifying this register to accommodate for both the PPv2.1 and PPv2.2 cases.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

drivers/net/mvpp2.c +12 -7

index 4f4e6749dc..e5b42b9e66 100644
@@ -91,9 +91,11 @@ do {									\
 #define     MVPP2_SNOOP_PKT_SIZE_MASK		0x1ff
 #define     MVPP2_SNOOP_BUF_HDR_MASK		BIT(9)
 #define     MVPP2_RXQ_POOL_SHORT_OFFS		20
-#define     MVPP2_RXQ_POOL_SHORT_MASK		0x700000
+#define     MVPP21_RXQ_POOL_SHORT_MASK		0x700000
+#define     MVPP22_RXQ_POOL_SHORT_MASK		0xf00000
 #define     MVPP2_RXQ_POOL_LONG_OFFS		24
-#define     MVPP2_RXQ_POOL_LONG_MASK		0x7000000
+#define     MVPP21_RXQ_POOL_LONG_MASK		0x7000000
+#define     MVPP22_RXQ_POOL_LONG_MASK		0xf000000
 #define     MVPP2_RXQ_PACKET_OFFSET_OFFS	28
 #define     MVPP2_RXQ_PACKET_OFFSET_MASK	0x70000000
 #define     MVPP2_RXQ_DISABLE_MASK		BIT(31)

@@ -2467,17 +2469,20 @@ static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
 				    int lrxq, int long_pool)
 {
-	u32 val;
+	u32 val, mask;
 	int prxq;
 
 	/* Get queue physical ID */
 	prxq = port->rxqs[lrxq]->id;
 
-	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
-	val &= ~MVPP2_RXQ_POOL_LONG_MASK;
-	val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
-		    MVPP2_RXQ_POOL_LONG_MASK);
+	if (port->priv->hw_version == MVPP21)
+		mask = MVPP21_RXQ_POOL_LONG_MASK;
+	else
+		mask = MVPP22_RXQ_POOL_LONG_MASK;
 
+	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
+	val &= ~mask;
+	val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 }

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #18 lore raw

PATCH v2 18/45 net: mvpp2: adapt mvpp2_defaults_set() to PPv2.2

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

This commit modifies the mvpp2_defaults_set() function to not do the loopback and FIFO threshold initialization, which are not needed for PPv2.2.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

drivers/net/mvpp2.c +12 ~~-10~~

index e5b42b9e66..e75979b37a 100644
@@ -2755,16 +2755,18 @@ static void mvpp2_defaults_set(struct mvpp2_port *port)
 {
 	int tx_port_num, val, queue, ptxq, lrxq;
 
-	/* Configure port to loopback if needed */
-	if (port->flags & MVPP2_F_LOOPBACK)
-		mvpp2_port_loopback_set(port);
-
-	/* Update TX FIFO MIN Threshold */
-	val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
-	val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
-	/* Min. TX threshold must be less than minimal packet length */
-	val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
-	writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+	if (port->priv->hw_version == MVPP21) {
+		/* Configure port to loopback if needed */
+		if (port->flags & MVPP2_F_LOOPBACK)
+			mvpp2_port_loopback_set(port);
+
+		/* Update TX FIFO MIN Threshold */
+		val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+		val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+		/* Min. TX threshold must be less than minimal packet length */
+		val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
+		writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+	}
 
 	/* Disable Legacy WRR, Disable EJP, Release from reset */
 	tx_port_num = mvpp2_egress_port(port);

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #19 lore raw

PATCH v2 19/45 net: mvpp2: adjust mvpp2_{rxq, txq}_init for PPv2.2

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG registers have a slightly different layout, because they need to contain a 64-bit address for the RX and TX descriptor arrays. This commit adjusts those functions accordingly.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

drivers/net/mvpp2.c +21 -5

index e75979b37a..5e888e7394 100644
@@ -143,6 +143,7 @@ do {									\
 /* Descriptor Manager Top Registers */
 #define MVPP2_RXQ_NUM_REG			0x2040
 #define MVPP2_RXQ_DESC_ADDR_REG			0x2044
+#define     MVPP22_DESC_ADDR_OFFS		8
 #define MVPP2_RXQ_DESC_SIZE_REG			0x2048
 #define     MVPP2_RXQ_DESC_SIZE_MASK		0x3ff0
 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq)	(0x3000 + 4 * (rxq))

@@ -184,6 +185,7 @@ do {									\
 #define MVPP2_TXQ_RSVD_CLR_REG			0x20b8
 #define     MVPP2_TXQ_RSVD_CLR_OFFSET		16
 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu)	(0x2100 + 4 * (cpu))
+#define     MVPP22_AGGR_TXQ_DESC_ADDR_OFFS	8
 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu)	(0x2140 + 4 * (cpu))
 #define     MVPP2_AGGR_TXQ_DESC_SIZE_MASK	0x3ff0
 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu)		(0x2180 + 4 * (cpu))

@@ -3107,6 +3109,8 @@ static int mvpp2_aggr_txq_init(struct udevice *dev,
 			       int desc_num, int cpu,
 			       struct mvpp2 *priv)
 {
+	u32 txq_dma;
+
 	/* Allocate memory for TX descriptors */
 	aggr_txq->descs = buffer_loc.aggr_tx_descs;
 	aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;

@@ -3123,10 +3127,16 @@ static int mvpp2_aggr_txq_init(struct udevice *dev,
 	aggr_txq->next_desc_to_proc = mvpp2_read(priv,
 						 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
 
-	/* Set Tx descriptors queue starting address */
-	/* indirect access */
-	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
-		    aggr_txq->descs_dma);
+	/* Set Tx descriptors queue starting address indirect
+	 * access
+	 */
+	if (priv->hw_version == MVPP21)
+		txq_dma = aggr_txq->descs_dma;
+	else
+		txq_dma = aggr_txq->descs_dma >>
+			MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
+
+	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
 
 	return 0;

@@ -3137,6 +3147,8 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
 			  struct mvpp2_rx_queue *rxq)
 
 {
+	u32 rxq_dma;
+
 	rxq->size = port->rx_ring_size;
 
 	/* Allocate memory for RX descriptors */

@@ -3155,7 +3167,11 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
 
 	/* Set Rx descriptors queue starting address - indirect access */
 	mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
-	mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_dma);
+	if (port->priv->hw_version == MVPP21)
+		rxq_dma = rxq->descs_dma;
+	else
+		rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
+	mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
 	mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
 	mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #20 lore raw

PATCH v2 20/45 net: mvpp2: handle register mapping and access for PPv2.2

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

This commit adjusts the mvpp2 driver register mapping and access logic to support PPv2.2, to handle a number of differences.

Due to how the registers are laid out in memory, the Device Tree binding for the "reg" property is different:

- On PPv2.1, we had a first area for the common registers, and then one area per port.

- On PPv2.2, we have a first area for the common registers, and a second area for all the per-ports registers.

In addition, on PPv2.2, the area for the common registers is split into so-called "address spaces" of 64 KB each. They allow to access the same registers, but from different CPUs. Hence the introduction of cpu_base[] in 'struct mvpp2', and the modification of the mvpp2_write() and mvpp2_read() register accessors. For PPv2.1, the compatibility is preserved by using an "address space" size of 0.

Changed by Stefan for U-Boot:
Since we don't support multiple CPUs in U-Boot, I've removed all the code, macros and variables introduced in the Linux patch version for this.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next, mostly smaller changes, making checkpatch happy.

 drivers/net/mvpp2.c | 46 +++++++++++++++++++++++++++++++++++++---------
 1 file changed, 37 insertions(+), 9 deletions(-)

drivers/net/mvpp2.c +37 -9

index 5e888e7394..645a818df6 100644
@@ -342,6 +342,9 @@ do {									\
 #define      MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v)	(((v) << 6) & \
 					MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
 
+#define MVPP22_PORT_BASE			0x30e00
+#define MVPP22_PORT_OFFSET			0x1000
+
 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK	0xff
 
 /* Descriptor ring Macros */

@@ -702,6 +705,7 @@ struct mvpp2 {
 	/* Shared registers' base addresses */
 	void __iomem *base;
 	void __iomem *lms_base;
+	void __iomem *iface_base;
 
 	/* List of pointers to port structures */
 	struct mvpp2_port **port_list;

@@ -736,6 +740,11 @@ struct mvpp2_pcpu_stats {
 struct mvpp2_port {
 	u8 id;
 
+	/* Index of the port from the "group of ports" complex point
+	 * of view
+	 */
+	int gop_id;
+
 	int irq;
 
 	struct mvpp2 *priv;

@@ -3270,7 +3279,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
 
 	mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
 		    MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
-		    MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
+		    MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
 
 	/* WRR / EJP configuration - indirect access */
 	tx_port_num = mvpp2_egress_port(port);

@@ -3779,11 +3788,24 @@ static int mvpp2_port_probe(struct udevice *dev,
 	port->phy_interface = phy_mode;
 	port->phyaddr = phyaddr;
 
-	port->base = (void __iomem *)dev_get_addr_index(dev->parent,
-							priv_common_regs_num
-							+ id);
-	if (IS_ERR(port->base))
-		return PTR_ERR(port->base);
+	if (priv->hw_version == MVPP21) {
+		port->base = (void __iomem *)dev_get_addr_index(
+			dev->parent, priv_common_regs_num + id);
+		if (IS_ERR(port->base))
+			return PTR_ERR(port->base);
+	} else {
+		u32 gop_id;
+
+		gop_id = fdtdec_get_int(gd->fdt_blob, port_node,
+					"gop-port-id", -1);
+		if (id == -1) {
+			dev_err(&pdev->dev, "missing gop-port-id value\n");
+			return -EINVAL;
+		}
+
+		port->base = priv->iface_base + MVPP22_PORT_BASE +
+			gop_id * MVPP22_PORT_OFFSET;
+	}
 
 	port->tx_ring_size = MVPP2_MAX_TXD;
 	port->rx_ring_size = MVPP2_MAX_RXD;

@@ -4307,9 +4329,15 @@ static int mvpp2_base_probe(struct udevice *dev)
 	if (IS_ERR(priv->base))
 		return PTR_ERR(priv->base);
 
-	priv->lms_base = (void *)dev_get_addr_index(dev, 1);
-	if (IS_ERR(priv->lms_base))
-		return PTR_ERR(priv->lms_base);
+	if (priv->hw_version == MVPP21) {
+		priv->lms_base = (void *)dev_get_addr_index(dev, 1);
+		if (IS_ERR(priv->lms_base))
+			return PTR_ERR(priv->lms_base);
+	} else {
+		priv->iface_base = (void *)dev_get_addr_index(dev, 1);
+		if (IS_ERR(priv->iface_base))
+			return PTR_ERR(priv->iface_base);
+	}
 
 	/* Finally create and register the MDIO bus driver */
 	bus = mdio_alloc();

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #21 lore raw

PATCH v2 21/45 net: mvpp2: handle misc PPv2.1/PPv2.2 differences

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

This commit handles a few miscellaneous differences between PPv2.1 and PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY polling, etc.).

Changed by Stefan for U-Boot:
Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot version of this patch does not remove this function but simply adds the check for MVPP21 before the mvpp2_port_fc_adv_enable() call.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

drivers/net/mvpp2.c +19 -6

index 645a818df6..51922c06aa 100644
@@ -342,6 +342,9 @@ do {									\
 #define      MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v)	(((v) << 6) & \
 					MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
 
+#define MVPP22_SMI_MISC_CFG_REG			0x1204
+#define      MVPP22_SMI_POLLING_EN		BIT(10)
+
 #define MVPP22_PORT_BASE			0x30e00
 #define MVPP22_PORT_OFFSET			0x1000

@@ -3639,9 +3642,12 @@ static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
 
 static void mvpp2_port_power_up(struct mvpp2_port *port)
 {
+	struct mvpp2 *priv = port->priv;
+
 	mvpp2_port_mii_set(port);
 	mvpp2_port_periodic_xon_disable(port);
-	mvpp2_port_fc_adv_enable(port);
+	if (priv->hw_version == MVPP21)
+		mvpp2_port_fc_adv_enable(port);
 	mvpp2_port_reset(port);
 }

@@ -3892,9 +3898,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 		mvpp2_conf_mbus_windows(dram_target_info, priv);
 
 	/* Disable HW PHY polling */
-	val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
-	val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
-	writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+	if (priv->hw_version == MVPP21) {
+		val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+		val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
+		writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+	} else {
+		val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
+		val &= ~MVPP22_SMI_POLLING_EN;
+		writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
+	}
 
 	/* Allocate and initialize aggregated TXQs */
 	priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),

@@ -3920,8 +3932,9 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 		mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
 			    CONFIG_MV_ETH_RXQ);
 
-	writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
-	       priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
+	if (priv->hw_version == MVPP21)
+		writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
+		       priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
 
 	/* Allow cache snoop when transmiting packets */
 	mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #22 lore raw

PATCH v2 22/45 net: mvpp2: add AXI bridge initialization for PPv2.2

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this commit adds the necessary initialization of the AXI bridge.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

drivers/net/mvpp2.c +85 -0

index 51922c06aa..b56af82f92 100644
@@ -198,6 +198,34 @@ do {									\
 #define MVPP2_WIN_REMAP(w)			(0x4040 + ((w) << 2))
 #define MVPP2_BASE_ADDR_ENABLE			0x4060
 
+/* AXI Bridge Registers */
+#define MVPP22_AXI_BM_WR_ATTR_REG		0x4100
+#define MVPP22_AXI_BM_RD_ATTR_REG		0x4104
+#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG	0x4110
+#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG	0x4114
+#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG	0x4118
+#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG	0x411c
+#define MVPP22_AXI_RX_DATA_WR_ATTR_REG		0x4120
+#define MVPP22_AXI_TX_DATA_RD_ATTR_REG		0x4130
+#define MVPP22_AXI_RD_NORMAL_CODE_REG		0x4150
+#define MVPP22_AXI_RD_SNOOP_CODE_REG		0x4154
+#define MVPP22_AXI_WR_NORMAL_CODE_REG		0x4160
+#define MVPP22_AXI_WR_SNOOP_CODE_REG		0x4164
+
+/* Values for AXI Bridge registers */
+#define MVPP22_AXI_ATTR_CACHE_OFFS		0
+#define MVPP22_AXI_ATTR_DOMAIN_OFFS		12
+
+#define MVPP22_AXI_CODE_CACHE_OFFS		0
+#define MVPP22_AXI_CODE_DOMAIN_OFFS		4
+
+#define MVPP22_AXI_CODE_CACHE_NON_CACHE		0x3
+#define MVPP22_AXI_CODE_CACHE_WR_CACHE		0x7
+#define MVPP22_AXI_CODE_CACHE_RD_CACHE		0xb
+
+#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM	2
+#define MVPP22_AXI_CODE_DOMAIN_SYSTEM		3
+
 /* Interrupt Cause and Mask registers */
 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq)		(0x5200 + 4 * (rxq))
 #define MVPP2_ISR_RXQ_GROUP_REG(rxq)		(0x5400 + 4 * (rxq))

@@ -3879,6 +3907,60 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
 }
 
+static void mvpp2_axi_init(struct mvpp2 *priv)
+{
+	u32 val, rdval, wrval;
+
+	mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
+
+	/* AXI Bridge Configuration */
+
+	rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
+		<< MVPP22_AXI_ATTR_CACHE_OFFS;
+	rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+		<< MVPP22_AXI_ATTR_DOMAIN_OFFS;
+
+	wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
+		<< MVPP22_AXI_ATTR_CACHE_OFFS;
+	wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+		<< MVPP22_AXI_ATTR_DOMAIN_OFFS;
+
+	/* BM */
+	mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
+	mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
+
+	/* Descriptors */
+	mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
+	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
+	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
+	mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
+
+	/* Buffer Data */
+	mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
+	mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
+
+	val = MVPP22_AXI_CODE_CACHE_NON_CACHE
+		<< MVPP22_AXI_CODE_CACHE_OFFS;
+	val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
+		<< MVPP22_AXI_CODE_DOMAIN_OFFS;
+	mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
+	mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
+
+	val = MVPP22_AXI_CODE_CACHE_RD_CACHE
+		<< MVPP22_AXI_CODE_CACHE_OFFS;
+	val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+		<< MVPP22_AXI_CODE_DOMAIN_OFFS;
+
+	mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
+
+	val = MVPP22_AXI_CODE_CACHE_WR_CACHE
+		<< MVPP22_AXI_CODE_CACHE_OFFS;
+	val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+		<< MVPP22_AXI_CODE_DOMAIN_OFFS;
+
+	mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
+}
+
 /* Initialize network controller common part HW */
 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 {

@@ -3897,6 +3979,9 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 	if (dram_target_info)
 		mvpp2_conf_mbus_windows(dram_target_info, priv);
 
+	if (priv->hw_version == MVPP22)
+		mvpp2_axi_init(priv);
+
 	/* Disable HW PHY polling */
 	if (priv->hw_version == MVPP21) {
 		val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #23 lore raw

PATCH v2 23/45 net: mvpp2: rework RXQ interrupt group initialization for PPv2.2

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is configured, since it changed between PPv2.1 and PPv2.2.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next, mostly smaller changes, making checkpatch happy.

 drivers/net/mvpp2.c | 50 +++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 45 insertions(+), 5 deletions(-)

drivers/net/mvpp2.c +45 -5

index b56af82f92..16a9c75cf0 100644
@@ -228,7 +228,21 @@ do {									\
 
 /* Interrupt Cause and Mask registers */
 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq)		(0x5200 + 4 * (rxq))
-#define MVPP2_ISR_RXQ_GROUP_REG(rxq)		(0x5400 + 4 * (rxq))
+#define MVPP21_ISR_RXQ_GROUP_REG(rxq)		(0x5400 + 4 * (rxq))
+
+#define MVPP22_ISR_RXQ_GROUP_INDEX_REG          0x5400
+#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
+
+#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380
+
+#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG     0x5404
+#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK    0x1f
+#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK      0xf00
+#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET    8
+
 #define MVPP2_ISR_ENABLE_REG(port)		(0x5420 + 4 * (port))
 #define     MVPP2_ISR_ENABLE_INTERRUPT(mask)	((mask) & 0xffff)
 #define     MVPP2_ISR_DISABLE_INTERRUPT(mask)	(((mask) << 16) & 0xffff0000)

@@ -3747,7 +3761,19 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
 	}
 
 	/* Configure Rx queue group interrupt for this port */
-	mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ);
+	if (priv->hw_version == MVPP21) {
+		mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
+			    CONFIG_MV_ETH_RXQ);
+	} else {
+		u32 val;
+
+		val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
+		mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
+
+		val = (CONFIG_MV_ETH_RXQ <<
+		       MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
+		mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
+	}
 
 	/* Create Rx descriptor rings */
 	for (queue = 0; queue < rxq_number; queue++) {

@@ -4013,9 +4039,23 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 	mvpp2_rx_fifo_init(priv);
 
 	/* Reset Rx queue group interrupt configuration */
-	for (i = 0; i < MVPP2_MAX_PORTS; i++)
-		mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
-			    CONFIG_MV_ETH_RXQ);
+	for (i = 0; i < MVPP2_MAX_PORTS; i++) {
+		if (priv->hw_version == MVPP21) {
+			mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
+				    CONFIG_MV_ETH_RXQ);
+			continue;
+		} else {
+			u32 val;
+
+			val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
+			mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
+
+			val = (CONFIG_MV_ETH_RXQ <<
+			       MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
+			mvpp2_write(priv,
+				    MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
+		}
+	}
 
 	if (priv->hw_version == MVPP21)
 		writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #24 lore raw

PATCH v2 24/45 net: mvpp2: adapt rxq distribution to PPv2.2

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4 RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7 to the second port, 8->11 to the third port, etc.

In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate RXQs from the range of 32 RXQs available for each port. So port 0 must use RXQs in the range 0->31, port 1 in the range 32->63, etc.

This commit adapts the mvpp2 to this difference between PPv2.1 and PPv2.2:

- The constant definition MVPP2_MAX_RXQ is replaced by a new field 'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of RXQs per port. This field is initialized during ->probe() depending on the IP version.

- MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total number of RXQs by multiplying the number of ports by the maximum of RXQs per port. This was anyway used in only one place.

- In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted to cope with the different allocation strategy between PPv2.1 and PPv2.2. Due to this change, the 'next_first_rxq' argument of this function is no longer needed and is removed.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

---

Changes in v2: None

 drivers/net/mvpp2.c | 33 ++++++++++++++++++---------------
 1 file changed, 18 insertions(+), 15 deletions(-)

drivers/net/mvpp2.c +18 ~~-15~~

index 16a9c75cf0..c683fff53f 100644
@@ -454,9 +454,6 @@ do {									\
 /* Maximum number of TXQs used by single port */
 #define MVPP2_MAX_TXQ			8
 
-/* Maximum number of RXQs used by single port */
-#define MVPP2_MAX_RXQ			8
-
 /* Default number of TXQs in use */
 #define MVPP2_DEFAULT_TXQ		1

@@ -464,9 +461,6 @@ do {									\
 #define MVPP2_DEFAULT_RXQ		1
 #define CONFIG_MV_ETH_RXQ		8	/* increment by 8 */
 
-/* Total number of RXQs available to all ports */
-#define MVPP2_RXQ_TOTAL_NUM		(MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
-
 /* Max number of Rx descriptors */
 #define MVPP2_MAX_RXD			16

@@ -772,6 +766,9 @@ struct mvpp2 {
 	/* HW version */
 	enum { MVPP21, MVPP22 } hw_version;
 
+	/* Maximum number of RXQs per port */
+	unsigned int max_port_rxqs;
+
 	struct mii_dev *bus;
 };

@@ -3700,7 +3697,8 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
 	struct mvpp2_txq_pcpu *txq_pcpu;
 	int queue, cpu, err;
 
-	if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
+	if (port->first_rxq + rxq_number >
+	    MVPP2_MAX_PORTS * priv->max_port_rxqs)
 		return -EINVAL;
 
 	/* Disable port */

@@ -3808,8 +3806,7 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
 static int mvpp2_port_probe(struct udevice *dev,
 			    struct mvpp2_port *port,
 			    int port_node,
-			    struct mvpp2 *priv,
-			    int *next_first_rxq)
+			    struct mvpp2 *priv)
 {
 	int phy_node;
 	u32 id;

@@ -3843,7 +3840,10 @@ static int mvpp2_port_probe(struct udevice *dev,
 
 	port->priv = priv;
 	port->id = id;
-	port->first_rxq = *next_first_rxq;
+	if (priv->hw_version == MVPP21)
+		port->first_rxq = port->id * rxq_number;
+	else
+		port->first_rxq = port->id * priv->max_port_rxqs;
 	port->phy_node = phy_node;
 	port->phy_interface = phy_mode;
 	port->phyaddr = phyaddr;

@@ -3877,8 +3877,6 @@ static int mvpp2_port_probe(struct udevice *dev,
 	}
 	mvpp2_port_power_up(port);
 
-	/* Increment the first Rx queue number to be used by the next port */
-	*next_first_rxq += CONFIG_MV_ETH_RXQ;
 	priv->port_list[id] = port;
 	return 0;
 }

@@ -3995,7 +3993,8 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 	u32 val;
 
 	/* Checks for hardware constraints (U-Boot uses only one rxq) */
-	if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) {
+	if ((rxq_number > priv->max_port_rxqs) ||
+	    (txq_number > MVPP2_MAX_TXQ)) {
 		dev_err(&pdev->dev, "invalid queue size parameter\n");
 		return -EINVAL;
 	}

@@ -4388,8 +4387,7 @@ static int mvpp2_probe(struct udevice *dev)
 		return err;
 	}
 
-	return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
-				&buffer_loc.first_rxq);
+	return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
 }
 
 static const struct eth_ops mvpp2_ops = {

@@ -4477,6 +4475,11 @@ static int mvpp2_base_probe(struct udevice *dev)
 			return PTR_ERR(priv->iface_base);
 	}
 
+	if (priv->hw_version == MVPP21)
+		priv->max_port_rxqs = 8;
+	else
+		priv->max_port_rxqs = 32;
+
 	/* Finally create and register the MDIO bus driver */
 	bus = mdio_alloc();
 	if (!bus) {

Signature · 1 line

2.12.1

Joe Hershberger

2017-03-25 21:24 UTC #25 lore raw

PATCH v2 24/45 net: mvpp2: adapt rxq distribution to PPv2.2

Quoted 22 lines · Stefan Roese

From: Thomas Petazzoni <[email protected]>
In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4 RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7 to the second port, 8->11 to the third port, etc.
In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate RXQs from the range of 32 RXQs available for each port. So port 0 must use RXQs in the range 0->31, port 1 in the range 32->63, etc.
This commit adapts the mvpp2 to this difference between PPv2.1 and PPv2.2:
- The constant definition MVPP2_MAX_RXQ is replaced by a new field 'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of RXQs per port. This field is initialized during ->probe() depending on the IP version.
- MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total number of RXQs by multiplying the number of ports by the maximum of RXQs per port. This was anyway used in only one place.

Quoted 8 lines

- In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted to cope with the different allocation strategy between PPv2.1 and PPv2.2. Due to this change, the 'next_first_rxq' argument of this function is no longer needed and is removed.
Signed-off-by Thomas Petazzoni <[email protected]>
Signed-off-by Stefan Roese <[email protected]>
---

Acked-by Joe Hershberger <[email protected]>

Stefan Roese

author

2017-03-23 16:01 UTC #26 lore raw

PATCH v2 25/45 net: mvpp2: finally add the PPv2.2 compatible string

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

Now that the mvpp2 driver has been modified to accommodate the support for PPv2.2, we can finally advertise this support by adding the appropriate compatible string.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 4 ++++
 1 file changed, 4 insertions(+)

drivers/net/mvpp2.c +4 -0

index c683fff53f..16da28de69 100644
@@ -4541,6 +4541,10 @@ static const struct udevice_id mvpp2_ids[] = {
 		.compatible = "marvell,armada-375-pp2",
 		.data = MVPP21,
 	},
+	{
+		.compatible = "marvell,armada-7k-pp22",
+		.data = MVPP22,
+	},
 	{ }
 };

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #27 lore raw

PATCH v2 26/45 net: mvpp2: Add MDIO support for PPv2.2

In reply to Stefan Roese

In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver, currently only supporting the 32bit platforms (Armada 37x). This patch now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF can be used as well on these platforms.

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

drivers/net/mvpp2.c +13 -6

index 16da28de69..8751ee85e3 100644
@@ -397,7 +397,9 @@ do {									\
 	(((index) < (q)->last_desc) ? ((index) + 1) : 0)
 
 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
-#define MVPP2_SMI				0x0054
+#define MVPP21_SMI				0x0054
+/* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
+#define MVPP22_SMI				0x1200
 #define     MVPP2_PHY_REG_MASK			0x1f
 /* SMI register fields */
 #define     MVPP2_SMI_DATA_OFFS			0	/* Data */

@@ -745,6 +747,7 @@ struct mvpp2 {
 	void __iomem *base;
 	void __iomem *lms_base;
 	void __iomem *iface_base;
+	void __iomem *mdio_base;
 
 	/* List of pointers to port structures */
 	struct mvpp2_port **port_list;

@@ -4089,7 +4092,7 @@ static int smi_wait_ready(struct mvpp2 *priv)
 	/* wait till the SMI is not busy */
 	do {
 		/* read smi register */
-		smi_reg = readl(priv->lms_base + MVPP2_SMI);
+		smi_reg = readl(priv->mdio_base);
 		if (timeout-- == 0) {
 			printf("Error: SMI busy timeout\n");
 			return -EFAULT;

@@ -4131,14 +4134,14 @@ static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 		| MVPP2_SMI_OPCODE_READ;
 
 	/* write the smi register */
-	writel(smi_reg, priv->lms_base + MVPP2_SMI);
+	writel(smi_reg, priv->mdio_base);
 
 	/* wait till read value is ready */
 	timeout = MVPP2_SMI_TIMEOUT;
 
 	do {
 		/* read smi register */
-		smi_reg = readl(priv->lms_base + MVPP2_SMI);
+		smi_reg = readl(priv->mdio_base);
 		if (timeout-- == 0) {
 			printf("Err: SMI read ready timeout\n");
 			return -EFAULT;

@@ -4149,7 +4152,7 @@ static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 	for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
 		;
 
-	return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK;
+	return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK;
 }
 
 /*

@@ -4186,7 +4189,7 @@ static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 	smi_reg &= ~MVPP2_SMI_OPCODE_READ;
 
 	/* write the smi register */
-	writel(smi_reg, priv->lms_base + MVPP2_SMI);
+	writel(smi_reg, priv->mdio_base);
 
 	return 0;
 }

@@ -4469,10 +4472,14 @@ static int mvpp2_base_probe(struct udevice *dev)
 		priv->lms_base = (void *)dev_get_addr_index(dev, 1);
 		if (IS_ERR(priv->lms_base))
 			return PTR_ERR(priv->lms_base);
+
+		priv->mdio_base = priv->lms_base + MVPP21_SMI;
 	} else {
 		priv->iface_base = (void *)dev_get_addr_index(dev, 1);
 		if (IS_ERR(priv->iface_base))
 			return PTR_ERR(priv->iface_base);
+
+		priv->mdio_base = priv->iface_base + MVPP22_SMI;
 	}
 
 	if (priv->hw_version == MVPP21)

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #28 lore raw

PATCH v2 27/45 net: mvpp2: Move probe function from MISC to ETH DM driver

In reply to Stefan Roese

This patch moves the base_probe function mvpp2_base_probe() from the MISC driver to the ETH driver. When integrated in the MISC driver, probe is called too early before the U-Boot ethernet infrastructure (especially the MDIO / PHY interface) has been initialized. Resulting in errors in mdio_register().

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 80 ++++++++++++++++++++++++++++-------------------------
 1 file changed, 43 insertions(+), 37 deletions(-)

drivers/net/mvpp2.c +43 ~~-37~~

index 8751ee85e3..06909e6a3c 100644
@@ -773,6 +773,8 @@ struct mvpp2 {
 	unsigned int max_port_rxqs;
 
 	struct mii_dev *bus;
+
+	int probe_done;
 };
 
 struct mvpp2_pcpu_stats {

@@ -4377,42 +4379,6 @@ static void mvpp2_stop(struct udevice *dev)
 	mvpp2_cleanup_txqs(port);
 }
 
-static int mvpp2_probe(struct udevice *dev)
-{
-	struct mvpp2_port *port = dev_get_priv(dev);
-	struct mvpp2 *priv = dev_get_priv(dev->parent);
-	int err;
-
-	/* Initialize network controller */
-	err = mvpp2_init(dev, priv);
-	if (err < 0) {
-		dev_err(&pdev->dev, "failed to initialize controller\n");
-		return err;
-	}
-
-	return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
-}
-
-static const struct eth_ops mvpp2_ops = {
-	.start		= mvpp2_start,
-	.send		= mvpp2_send,
-	.recv		= mvpp2_recv,
-	.stop		= mvpp2_stop,
-};
-
-static struct driver mvpp2_driver = {
-	.name	= "mvpp2",
-	.id	= UCLASS_ETH,
-	.probe	= mvpp2_probe,
-	.ops	= &mvpp2_ops,
-	.priv_auto_alloc_size = sizeof(struct mvpp2_port),
-	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
-};
-
-/*
- * Use a MISC device to bind the n instances (child nodes) of the
- * network base controller in UCLASS_ETH.
- */
 static int mvpp2_base_probe(struct udevice *dev)
 {
 	struct mvpp2 *priv = dev_get_priv(dev);

@@ -4503,6 +4469,47 @@ static int mvpp2_base_probe(struct udevice *dev)
 	return mdio_register(bus);
 }
 
+static int mvpp2_probe(struct udevice *dev)
+{
+	struct mvpp2_port *port = dev_get_priv(dev);
+	struct mvpp2 *priv = dev_get_priv(dev->parent);
+	int err;
+
+	/* Only call the probe function for the parent once */
+	if (!priv->probe_done) {
+		err = mvpp2_base_probe(dev->parent);
+		priv->probe_done = 1;
+	}
+	/* Initialize network controller */
+	err = mvpp2_init(dev, priv);
+	if (err < 0) {
+		dev_err(&pdev->dev, "failed to initialize controller\n");
+		return err;
+	}
+
+	return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
+}
+
+static const struct eth_ops mvpp2_ops = {
+	.start		= mvpp2_start,
+	.send		= mvpp2_send,
+	.recv		= mvpp2_recv,
+	.stop		= mvpp2_stop,
+};
+
+static struct driver mvpp2_driver = {
+	.name	= "mvpp2",
+	.id	= UCLASS_ETH,
+	.probe	= mvpp2_probe,
+	.ops	= &mvpp2_ops,
+	.priv_auto_alloc_size = sizeof(struct mvpp2_port),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+/*
+ * Use a MISC device to bind the n instances (child nodes) of the
+ * network base controller in UCLASS_ETH.
+ */
 static int mvpp2_base_bind(struct udevice *parent)
 {
 	const void *blob = gd->fdt_blob;

@@ -4560,6 +4567,5 @@ U_BOOT_DRIVER(mvpp2_base) = {
 	.id	= UCLASS_MISC,
 	.of_match = mvpp2_ids,
 	.bind	= mvpp2_base_bind,
-	.probe	= mvpp2_base_probe,
 	.priv_auto_alloc_size = sizeof(struct mvpp2),
 };

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #29 lore raw

PATCH v2 28/45 net: mvpp2.c: Clear all buffer / descriptor areas before usage

In reply to Stefan Roese

This fixes problems noticed with the PPv2.2 A7k/8k port, when not all elements of the descriptors had been cleared before use.

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 3 +++
 1 file changed, 3 insertions(+)

drivers/net/mvpp2.c +3 -0

index 06909e6a3c..b9e0fdcc82 100644
@@ -4429,6 +4429,9 @@ static int mvpp2_base_probe(struct udevice *dev)
 		size += RX_BUFFER_SIZE;
 	}
 
+	/* Clear the complete area so that all descriptors are cleared */
+	memset(bd_space, 0, size);
+
 	/* Save base addresses for later use */
 	priv->base = (void *)dev_get_addr_index(dev, 0);
 	if (IS_ERR(priv->base))

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #30 lore raw

PATCH v2 29/45 net: mvpp2: Enable compilation for Armada 7K/8K platforms

In reply to Stefan Roese

Since Armada 7K/8K is also equipped with a newer version of the MVPP2 ethernet controller, lets enable compilation of this driver for these platforms.

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/net/Kconfig +3 -3

index 70e36611ea..8aa92790f4 100644
@@ -124,12 +124,12 @@ config FEC_MXC
 	  NXP i.MX processors.
 
 config MVPP2
-	bool "Marvell Armada 375 network interface support"
-	depends on ARMADA_375
+	bool "Marvell Armada 375/7K/8K network interface support"
+	depends on ARMADA_375 || ARMADA_8K
 	select PHYLIB
 	help
 	  This driver supports the network interface units in the
-	  Marvell ARMADA 375 SoC.
+	  Marvell ARMADA 375, 7K and 8K SoCs.
 
 config MACB
 	bool "Cadence MACB/GEM Ethernet Interface"

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #31 lore raw

PATCH v2 30/45 arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K

In reply to Stefan Roese

From: Thomas Petazzoni <[email protected]>

This commit adds the description of the PPv2.2 hardware block for the Marvell Armada 7K and Armada 8K processors, and their corresponding Armada 7040 and 8040 Development boards.

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 arch/arm/dts/armada-7040-db.dts       | 25 +++++++++++++++++++++++
 arch/arm/dts/armada-8040-db.dts       | 16 +++++++++++++++
 arch/arm/dts/armada-cp110-master.dtsi | 37 +++++++++++++++++++++++++++++++++++
 arch/arm/dts/armada-cp110-slave.dtsi  | 37 +++++++++++++++++++++++++++++++++++
 4 files changed, 115 insertions(+)

arch/arm/dts/armada-7040-db.dts +25 -0

index 63442df8f3..776bc7831d 100644
@@ -209,3 +209,28 @@
 	no-1-8-v;
 	non-removable;
 };
+
+&cpm_mdio {
+	phy0: ethernet-phy at 0 {
+		reg = <0>;
+	};
+	phy1: ethernet-phy at 1 {
+		reg = <1>;
+	};
+};
+
+&cpm_ethernet {
+	status = "okay";
+};
+
+&cpm_eth1 {
+	status = "okay";
+	phy = <&phy0>;
+	phy-mode = "sgmii";
+};
+
+&cpm_eth2 {
+	status = "okay";
+	phy = <&phy1>;
+	phy-mode = "rgmii-id";
+};

arch/arm/dts/armada-8040-db.dts +16 -0

index 40def9d6cd..f1f196f563 100644
@@ -283,3 +283,19 @@
 &cps_utmi0 {
 	status = "okay";
 };
+
+&cpm_mdio {
+	phy1: ethernet-phy at 1 {
+		reg = <1>;
+	};
+};
+
+&cpm_ethernet {
+	status = "okay";
+};
+
+&cpm_eth2 {
+	status = "okay";
+	phy = <&phy1>;
+	phy-mode = "rgmii-id";
+};

arch/arm/dts/armada-cp110-master.dtsi +37 -0

index 661a69679e..a450f3fd7c 100644
@@ -61,6 +61,43 @@
 			interrupt-parent = <&gic>;
 			ranges = <0x0 0x0 0xf2000000 0x2000000>;
 
+			cpm_ethernet: ethernet at 0 {
+				compatible = "marvell,armada-7k-pp22";
+				reg = <0x0 0x100000>, <0x129000 0xb000>;
+				clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
+				clock-names = "pp_clk", "gop_clk", "mg_clk";
+				status = "disabled";
+				dma-coherent;
+
+				cpm_eth0: eth0 {
+					interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <0>;
+					gop-port-id = <0>;
+					status = "disabled";
+				};
+
+				cpm_eth1: eth1 {
+					interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <1>;
+					gop-port-id = <2>;
+					status = "disabled";
+				};
+
+				cpm_eth2: eth2 {
+					interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <2>;
+					gop-port-id = <3>;
+					status = "disabled";
+				};
+			};
+
+			cpm_mdio: mdio at 12a200 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "marvell,orion-mdio";
+				reg = <0x12a200 0x10>;
+			};
+
 			cpm_syscon0: system-controller at 440000 {
 				compatible = "marvell,cp110-system-controller0",
 					     "syscon";

arch/arm/dts/armada-cp110-slave.dtsi +37 -0

index 92ef55cf26..50898a8da6 100644
@@ -61,6 +61,43 @@
 			interrupt-parent = <&gic>;
 			ranges = <0x0 0x0 0xf4000000 0x2000000>;
 
+			cps_ethernet: ethernet at 0 {
+				compatible = "marvell,armada-7k-pp22";
+				reg = <0x0 0x100000>, <0x129000 0xb000>;
+				clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
+				clock-names = "pp_clk", "gop_clk", "mg_clk";
+				status = "disabled";
+				dma-coherent;
+
+				cps_eth0: eth0 {
+					interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <0>;
+					gop-port-id = <0>;
+					status = "disabled";
+				};
+
+				cps_eth1: eth1 {
+					interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <1>;
+					gop-port-id = <2>;
+					status = "disabled";
+				};
+
+				cps_eth2: eth2 {
+					interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+					port-id = <2>;
+					gop-port-id = <3>;
+					status = "disabled";
+				};
+			};
+
+			cps_mdio: mdio at 12a200 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "marvell,orion-mdio";
+				reg = <0x12a200 0x10>;
+			};
+
 			cps_syscon0: system-controller at 440000 {
 				compatible = "marvell,cp110-system-controller0",
 					     "syscon";

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #32 lore raw

PATCH v2 31/45 arm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driver

In reply to Stefan Roese

Since we've now integrated the A7k/8k support in the mvpp2 ethernet driver, lets enable the support for both Marvell developments boards.

Signed-off-by Stefan Roese <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 configs/mvebu_db-88f7040_defconfig | 2 +-
 configs/mvebu_db-88f8040_defconfig | 2 +-
 include/configs/mvebu_armada-8k.h  | 8 ++++++++
 3 files changed, 10 insertions(+), 2 deletions(-)

configs/mvebu_db-88f7040_defconfig +1 -1

index f20158a117..fdafeb6607 100644
@@ -47,7 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCIE_DW_MVEBU=y

configs/mvebu_db-88f8040_defconfig +1 -1

index 3611b845fe..9866e19778 100644
@@ -47,7 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCIE_DW_MVEBU=y

include/configs/mvebu_armada-8k.h +8 -0

index a8a9d15b5e..8ee5f27a97 100644
@@ -81,6 +81,14 @@
 #define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
 #define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
 
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_PHY_GIGE		/* GbE speed/duplex detect */
+#define CONFIG_ARP_TIMEOUT	200
+#define CONFIG_NET_RETRY_COUNT	50
+
 /* USB 2.0 */
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #33 lore raw

PATCH v2 32/45 net: mvpp2: Handle eth device naming in multi-CP case correctly

In reply to Stefan Roese

Currently, the naming of the ethernet ports is not handled correctly in the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP also instantiates an ethernet controller with the same device ID's. This patch now takes this into account and adds the required base-id so that the slave-CP ethernet devices will be named "mvpp2-3 ...".

This patch also updates my Copyright notice to include 2017 as well.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

drivers/net/mvpp2.c +10 -1

index b9e0fdcc82..2328c25850 100644
@@ -6,7 +6,7 @@
  * Marcin Wojtas <[email protected]>
  *
  * U-Boot version:
- * Copyright (C) 2016 Stefan Roese <[email protected]>
+ * Copyright (C) 2016-2017 Stefan Roese <[email protected]>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any

@@ -1090,6 +1090,8 @@ static int rxq_number = MVPP2_DEFAULT_RXQ;
 /* Number of TXQs used by single port */
 static int txq_number = MVPP2_DEFAULT_TXQ;
 
+static int base_id;
+
 #define MVPP2_DRIVER_NAME "mvpp2"
 #define MVPP2_DRIVER_VERSION "1.0"

@@ -4523,6 +4525,7 @@ static int mvpp2_base_bind(struct udevice *parent)
 	char *name;
 	int subnode;
 	u32 id;
+	int base_id_add;
 
 	/* Lookup eth driver */
 	drv = lists_uclass_lookup(UCLASS_ETH);

@@ -4531,7 +4534,12 @@ static int mvpp2_base_bind(struct udevice *parent)
 		return -ENOENT;
 	}
 
+	base_id_add = base_id;
+
 	fdt_for_each_subnode(subnode, blob, node) {
+		/* Increment base_id for all subnodes, also the disabled ones */
+		base_id++;
+
 		/* Skip disabled ports */
 		if (!fdtdec_get_is_enabled(blob, subnode))
 			continue;

@@ -4541,6 +4549,7 @@ static int mvpp2_base_bind(struct udevice *parent)
 			return -ENOMEM;
 
 		id = fdtdec_get_int(blob, subnode, "port-id", -1);
+		id += base_id_add;
 
 		name = calloc(1, 16);
 		sprintf(name, "mvpp2-%d", id);

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:01 UTC #34 lore raw

PATCH v2 33/45 net: mvpp2: Add remove function that is called before the OS is started

In reply to Stefan Roese

This patch adds a remove function to the mvpp2 ethernet driver which is called before the OS is started, doing:

- Allocate the used buffers back from the buffer manager
- Stop the BM activity

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

drivers/net/mvpp2.c +24 -0

index 2328c25850..e13a679e33 100644
@@ -2454,6 +2454,13 @@ static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
 			       struct mvpp2_bm_pool *bm_pool)
 {
+	int i;
+
+	for (i = 0; i < bm_pool->buf_num; i++) {
+		/* Allocate buffer back from the buffer manager */
+		mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
+	}
+
 	bm_pool->buf_num = 0;
 }

@@ -4495,6 +4502,21 @@ static int mvpp2_probe(struct udevice *dev)
 	return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
 }
 
+/*
+ * Empty BM pool and stop its activity before the OS is started
+ */
+static int mvpp2_remove(struct udevice *dev)
+{
+	struct mvpp2_port *port = dev_get_priv(dev);
+	struct mvpp2 *priv = port->priv;
+	int i;
+
+	for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
+		mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
+
+	return 0;
+}
+
 static const struct eth_ops mvpp2_ops = {
 	.start		= mvpp2_start,
 	.send		= mvpp2_send,

@@ -4506,9 +4528,11 @@ static struct driver mvpp2_driver = {
 	.name	= "mvpp2",
 	.id	= UCLASS_ETH,
 	.probe	= mvpp2_probe,
+	.remove = mvpp2_remove,
 	.ops	= &mvpp2_ops,
 	.priv_auto_alloc_size = sizeof(struct mvpp2_port),
 	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.flags	= DM_FLAG_ACTIVE_DMA,
 };
 
 /*

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:02 UTC #35 lore raw

PATCH v2 34/45 net: mvpp2: Add RX and TX FIFO configuration for PPv2.2

In reply to Stefan Roese

This patch adds the PPv2.2 specific FIFO configuration to the mvpp2 driver. The RX FIFO packet data size is changed to the recommended FIFO sizes. The TX FIFO configuration is newly added.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

---

Changes in v2: None

 drivers/net/mvpp2.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 68 insertions(+), 7 deletions(-)

drivers/net/mvpp2.c +68 -7

index e13a679e33..4863336985 100644
@@ -482,9 +482,23 @@ do {									\
 #define MVPP2_TX_DESC_ALIGN		(MVPP2_DESC_ALIGNED_SIZE - 1)
 
 /* RX FIFO constants */
-#define MVPP2_RX_FIFO_PORT_DATA_SIZE	0x2000
-#define MVPP2_RX_FIFO_PORT_ATTR_SIZE	0x80
-#define MVPP2_RX_FIFO_PORT_MIN_PKT	0x80
+#define MVPP21_RX_FIFO_PORT_DATA_SIZE		0x2000
+#define MVPP21_RX_FIFO_PORT_ATTR_SIZE		0x80
+#define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE	0x8000
+#define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE	0x2000
+#define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE	0x1000
+#define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE	0x200
+#define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE	0x80
+#define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE	0x40
+#define MVPP2_RX_FIFO_PORT_MIN_PKT		0x80
+
+/* TX general registers */
+#define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port)	(0x8860 + ((eth_tx_port) << 2))
+#define MVPP22_TX_FIFO_SIZE_MASK		0xf
+
+/* TX FIFO constants */
+#define MVPP2_TX_FIFO_DATA_SIZE_10KB		0xa
+#define MVPP2_TX_FIFO_DATA_SIZE_3KB		0x3
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \

@@ -3934,10 +3948,35 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
 	int port;
 
 	for (port = 0; port < MVPP2_MAX_PORTS; port++) {
-		mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
-			    MVPP2_RX_FIFO_PORT_DATA_SIZE);
-		mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
-			    MVPP2_RX_FIFO_PORT_ATTR_SIZE);
+		if (priv->hw_version == MVPP22) {
+			if (port == 0) {
+				mvpp2_write(priv,
+					    MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
+				mvpp2_write(priv,
+					    MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
+			} else if (port == 1) {
+				mvpp2_write(priv,
+					    MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
+				mvpp2_write(priv,
+					    MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
+			} else {
+				mvpp2_write(priv,
+					    MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
+				mvpp2_write(priv,
+					    MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+					    MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
+			}
+		} else {
+			mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+				    MVPP21_RX_FIFO_PORT_DATA_SIZE);
+			mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+				    MVPP21_RX_FIFO_PORT_ATTR_SIZE);
+		}
 	}
 
 	mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,

@@ -3945,6 +3984,24 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
 }
 
+/* Initialize Tx FIFO's */
+static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
+{
+	int port, val;
+
+	for (port = 0; port < MVPP2_MAX_PORTS; port++) {
+		/* Port 0 supports 10KB TX FIFO */
+		if (port == 0) {
+			val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
+				MVPP22_TX_FIFO_SIZE_MASK;
+		} else {
+			val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
+				MVPP22_TX_FIFO_SIZE_MASK;
+		}
+		mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
+	}
+}
+
 static void mvpp2_axi_init(struct mvpp2 *priv)
 {
 	u32 val, rdval, wrval;

@@ -4051,6 +4108,10 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 	/* Rx Fifo Init */
 	mvpp2_rx_fifo_init(priv);
 
+	/* Tx Fifo Init */
+	if (priv->hw_version == MVPP22)
+		mvpp2_tx_fifo_init(priv);
+
 	/* Reset Rx queue group interrupt configuration */
 	for (i = 0; i < MVPP2_MAX_PORTS; i++) {
 		if (priv->hw_version == MVPP21) {

Signature · 1 line

2.12.1

Joe Hershberger

2017-03-25 20:32 UTC #36 lore raw

PATCH v2 34/45 net: mvpp2: Add RX and TX FIFO configuration for PPv2.2

Quoted 8 lines · Stefan Roese

This patch adds the PPv2.2 specific FIFO configuration to the mvpp2 driver. The RX FIFO packet data size is changed to the recommended FIFO sizes. The TX FIFO configuration is newly added.
Signed-off-by Stefan Roese <[email protected]>
Cc Stefan Chulski <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Nadav Haklai <[email protected]>

Acked-by Joe Hershberger <[email protected]>

Stefan Roese

author

2017-03-23 16:02 UTC #37 lore raw

PATCH v2 35/45 net: include/phy.h: Add new PHY interface modes

In reply to Stefan Roese

This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 include/phy.h | 6 ++++++
 1 file changed, 6 insertions(+)

include/phy.h +6 -0

index 5477496e0e..8e507cd7a6 100644
@@ -61,6 +61,9 @@ typedef enum {
 	PHY_INTERFACE_MODE_RGMII_TXID,
 	PHY_INTERFACE_MODE_RTBI,
 	PHY_INTERFACE_MODE_XGMII,
+	PHY_INTERFACE_MODE_XAUI,
+	PHY_INTERFACE_MODE_RXAUI,
+	PHY_INTERFACE_MODE_SFI,
 	PHY_INTERFACE_MODE_NONE,	/* Must be last */
 
 	PHY_INTERFACE_MODE_COUNT,

@@ -80,6 +83,9 @@ static const char *phy_interface_strings[] = {
 	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
 	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
 	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
+	[PHY_INTERFACE_MODE_XAUI]		= "xaui",
+	[PHY_INTERFACE_MODE_RXAUI]		= "rxaui",
+	[PHY_INTERFACE_MODE_SFI]		= "sfi",
 	[PHY_INTERFACE_MODE_NONE]		= "",
 };

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:02 UTC #38 lore raw

PATCH v2 36/45 net: mvpp2: Restructure probe / init functions

In reply to Stefan Roese

This patch does a bit of restructuring of the probe / init functions, mainly to allow earlier register access as it is needed for the upcoming GoP (Group of Ports) and NetC (Net Complex) code.

Signed-off-by Stefan Roese <[email protected]>

Cc Joe Hershberger <[email protected]>

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 76 ++++++++++++++++++++++++++++++++---------------------
 1 file changed, 46 insertions(+), 30 deletions(-)

drivers/net/mvpp2.c +46 ~~-30~~

index 4863336985..ecefa21097 100644
@@ -3830,19 +3830,14 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
 	return 0;
 }
 
-/* Ports initialization */
-static int mvpp2_port_probe(struct udevice *dev,
-			    struct mvpp2_port *port,
-			    int port_node,
-			    struct mvpp2 *priv)
+static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 {
+	int port_node = dev_of_offset(dev);
+	const char *phy_mode_str;
 	int phy_node;
 	u32 id;
 	u32 phyaddr;
-	const char *phy_mode_str;
 	int phy_mode = -1;
-	int priv_common_regs_num = 2;
-	int err;
 
 	phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
 	if (phy_node < 0) {

@@ -3866,46 +3861,37 @@ static int mvpp2_port_probe(struct udevice *dev,
 
 	phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
 
-	port->priv = priv;
 	port->id = id;
-	if (priv->hw_version == MVPP21)
+	if (port->priv->hw_version == MVPP21)
 		port->first_rxq = port->id * rxq_number;
 	else
-		port->first_rxq = port->id * priv->max_port_rxqs;
+		port->first_rxq = port->id * port->priv->max_port_rxqs;
 	port->phy_node = phy_node;
 	port->phy_interface = phy_mode;
 	port->phyaddr = phyaddr;
 
-	if (priv->hw_version == MVPP21) {
-		port->base = (void __iomem *)dev_get_addr_index(
-			dev->parent, priv_common_regs_num + id);
-		if (IS_ERR(port->base))
-			return PTR_ERR(port->base);
-	} else {
-		u32 gop_id;
-
-		gop_id = fdtdec_get_int(gd->fdt_blob, port_node,
-					"gop-port-id", -1);
-		if (id == -1) {
-			dev_err(&pdev->dev, "missing gop-port-id value\n");
-			return -EINVAL;
-		}
+	return 0;
+}
 
-		port->base = priv->iface_base + MVPP22_PORT_BASE +
-			gop_id * MVPP22_PORT_OFFSET;
-	}
+/* Ports initialization */
+static int mvpp2_port_probe(struct udevice *dev,
+			    struct mvpp2_port *port,
+			    int port_node,
+			    struct mvpp2 *priv)
+{
+	int err;
 
 	port->tx_ring_size = MVPP2_MAX_TXD;
 	port->rx_ring_size = MVPP2_MAX_RXD;
 
 	err = mvpp2_port_init(dev, port);
 	if (err < 0) {
-		dev_err(&pdev->dev, "failed to init port %d\n", id);
+		dev_err(&pdev->dev, "failed to init port %d\n", port->id);
 		return err;
 	}
 	mvpp2_port_power_up(port);
 
-	priv->port_list[id] = port;
+	priv->port_list[port->id] = port;
 	return 0;
 }

@@ -4553,6 +4539,36 @@ static int mvpp2_probe(struct udevice *dev)
 		err = mvpp2_base_probe(dev->parent);
 		priv->probe_done = 1;
 	}
+
+	port->priv = dev_get_priv(dev->parent);
+
+	err = phy_info_parse(dev, port);
+	if (err)
+		return err;
+
+	/*
+	 * We need the port specific io base addresses at this stage, since
+	 * gop_port_init() accesses these registers
+	 */
+	if (priv->hw_version == MVPP21) {
+		int priv_common_regs_num = 2;
+
+		port->base = (void __iomem *)dev_get_addr_index(
+			dev->parent, priv_common_regs_num + port->id);
+		if (IS_ERR(port->base))
+			return PTR_ERR(port->base);
+	} else {
+		port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+					      "gop-port-id", -1);
+		if (port->id == -1) {
+			dev_err(&pdev->dev, "missing gop-port-id value\n");
+			return -EINVAL;
+		}
+
+		port->base = priv->iface_base + MVPP22_PORT_BASE +
+			port->gop_id * MVPP22_PORT_OFFSET;
+	}
+
 	/* Initialize network controller */
 	err = mvpp2_init(dev, priv);
 	if (err < 0) {

Signature · 1 line

2.12.1

Joe Hershberger

2017-03-25 21:30 UTC #39 lore raw

PATCH v2 36/45 net: mvpp2: Restructure probe / init functions

Quoted 6 lines · Stefan Roese

This patch does a bit of restructuring of the probe / init functions, mainly to allow earlier register access as it is needed for the upcoming GoP (Group of Ports) and NetC (Net Complex) code.
Signed-off-by Stefan Roese <[email protected]>
Cc Joe Hershberger <[email protected]>

Acked-by Joe Hershberger <[email protected]>

Stefan Roese

author

2017-03-23 16:02 UTC #40 lore raw

PATCH v2 37/45 net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMII

In reply to Stefan Roese

Read the "phy-speed" DT property to differentiate between 1 and 2.5GB SGMII operations. Please note that its unclear right now, if this DT property will be accepted in mainline Linux. If not, we need to revisit this code and change it to use the accepted property.

Signed-off-by Stefan Roese <[email protected]>

Cc Joe Hershberger <[email protected]>

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

drivers/net/mvpp2.c +11 -0

index ecefa21097..6f9a4137f8 100644
@@ -839,6 +839,8 @@ struct mvpp2_port {
 	unsigned int duplex;
 	unsigned int speed;
 
+	unsigned int phy_speed;		/* SGMII 1Gbps vs 2.5Gbps */
+
 	struct mvpp2_bm_pool *pool_long;
 	struct mvpp2_bm_pool *pool_short;

@@ -3859,6 +3861,15 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 		return -EINVAL;
 	}
 
+	/*
+	 * ToDo:
+	 * Not sure if this DT property "phy-speed" will get accepted, so
+	 * this might change later
+	 */
+	/* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
+	port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
+					 "phy-speed", 1000);
+
 	phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
 
 	port->id = id;

Signature · 1 line

2.12.1

Joe Hershberger

2017-03-25 21:31 UTC #41 lore raw

PATCH v2 37/45 net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMII

Quoted 7 lines · Stefan Roese

Read the "phy-speed" DT property to differentiate between 1 and 2.5GB SGMII operations. Please note that its unclear right now, if this DT property will be accepted in mainline Linux. If not, we need to revisit this code and change it to use the accepted property.
Signed-off-by Stefan Roese <[email protected]>
Cc Joe Hershberger <[email protected]>

Acked-by Joe Hershberger <[email protected]>

Stefan Roese

author

2017-03-23 16:02 UTC #42 lore raw

PATCH v2 38/45 net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)

In reply to Stefan Roese

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only RGMII and SGMII support have been added, as these are the only interfaces that this code has been tested with.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Cc Joe Hershberger <[email protected]>

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 766 +++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 758 insertions(+), 8 deletions(-)

drivers/net/mvpp2.c +758 -8

index 6f9a4137f8..76370faff0 100644
@@ -355,6 +355,7 @@ do {									\
 /* Per-port registers */
 #define MVPP2_GMAC_CTRL_0_REG			0x0
 #define      MVPP2_GMAC_PORT_EN_MASK		BIT(0)
+#define      MVPP2_GMAC_PORT_TYPE_MASK		BIT(1)
 #define      MVPP2_GMAC_MAX_RX_SIZE_OFFS	2
 #define      MVPP2_GMAC_MAX_RX_SIZE_MASK	0x7ffc
 #define      MVPP2_GMAC_MIB_CNTR_EN_MASK	BIT(15)

@@ -366,29 +367,131 @@ do {									\
 #define      MVPP2_GMAC_SA_LOW_OFFS		7
 #define MVPP2_GMAC_CTRL_2_REG			0x8
 #define      MVPP2_GMAC_INBAND_AN_MASK		BIT(0)
+#define      MVPP2_GMAC_SGMII_MODE_MASK		BIT(0)
 #define      MVPP2_GMAC_PCS_ENABLE_MASK		BIT(3)
 #define      MVPP2_GMAC_PORT_RGMII_MASK		BIT(4)
+#define      MVPP2_GMAC_PORT_DIS_PADING_MASK	BIT(5)
 #define      MVPP2_GMAC_PORT_RESET_MASK		BIT(6)
+#define      MVPP2_GMAC_CLK_125_BYPS_EN_MASK	BIT(9)
 #define MVPP2_GMAC_AUTONEG_CONFIG		0xc
 #define      MVPP2_GMAC_FORCE_LINK_DOWN		BIT(0)
 #define      MVPP2_GMAC_FORCE_LINK_PASS		BIT(1)
+#define      MVPP2_GMAC_EN_PCS_AN		BIT(2)
+#define      MVPP2_GMAC_AN_BYPASS_EN		BIT(3)
 #define      MVPP2_GMAC_CONFIG_MII_SPEED	BIT(5)
 #define      MVPP2_GMAC_CONFIG_GMII_SPEED	BIT(6)
 #define      MVPP2_GMAC_AN_SPEED_EN		BIT(7)
 #define      MVPP2_GMAC_FC_ADV_EN		BIT(9)
+#define      MVPP2_GMAC_EN_FC_AN		BIT(11)
 #define      MVPP2_GMAC_CONFIG_FULL_DUPLEX	BIT(12)
 #define      MVPP2_GMAC_AN_DUPLEX_EN		BIT(13)
+#define      MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG	BIT(15)
 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG		0x1c
 #define      MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS	6
 #define      MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK	0x1fc0
 #define      MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v)	(((v) << 6) & \
 					MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
+#define MVPP2_GMAC_CTRL_4_REG			0x90
+#define      MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK	BIT(0)
+#define      MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK	BIT(5)
+#define      MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK	BIT(6)
+#define      MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK	BIT(7)
 
-#define MVPP22_SMI_MISC_CFG_REG			0x1204
+/*
+ * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
+ * relative to port->base.
+ */
+
+/* Port Mac Control0 */
+#define MVPP22_XLG_CTRL0_REG			0x100
+#define      MVPP22_XLG_PORT_EN			BIT(0)
+#define      MVPP22_XLG_MAC_RESETN		BIT(1)
+#define      MVPP22_XLG_RX_FC_EN		BIT(7)
+#define      MVPP22_XLG_MIBCNT_DIS		BIT(13)
+/* Port Mac Control1 */
+#define MVPP22_XLG_CTRL1_REG			0x104
+#define      MVPP22_XLG_MAX_RX_SIZE_OFFS	0
+#define      MVPP22_XLG_MAX_RX_SIZE_MASK	0x1fff
+/* Port Interrupt Mask */
+#define MVPP22_XLG_INTERRUPT_MASK_REG		0x118
+#define      MVPP22_XLG_INTERRUPT_LINK_CHANGE	BIT(1)
+/* Port Mac Control3 */
+#define MVPP22_XLG_CTRL3_REG			0x11c
+#define      MVPP22_XLG_CTRL3_MACMODESELECT_MASK	(7 << 13)
+#define      MVPP22_XLG_CTRL3_MACMODESELECT_GMAC	(0 << 13)
+#define      MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC	(1 << 13)
+/* Port Mac Control4 */
+#define MVPP22_XLG_CTRL4_REG			0x184
+#define      MVPP22_XLG_FORWARD_802_3X_FC_EN	BIT(5)
+#define      MVPP22_XLG_FORWARD_PFC_EN		BIT(6)
+#define      MVPP22_XLG_MODE_DMA_1G		BIT(12)
+#define      MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK	BIT(14)
+
+/* XPCS registers */
+
+/* Global Configuration 0 */
+#define MVPP22_XPCS_GLOBAL_CFG_0_REG		0x0
+#define      MVPP22_XPCS_PCSRESET		BIT(0)
+#define      MVPP22_XPCS_PCSMODE_OFFS		3
+#define      MVPP22_XPCS_PCSMODE_MASK		(0x3 << \
+						 MVPP22_XPCS_PCSMODE_OFFS)
+#define      MVPP22_XPCS_LANEACTIVE_OFFS	5
+#define      MVPP22_XPCS_LANEACTIVE_MASK	(0x3 << \
+						 MVPP22_XPCS_LANEACTIVE_OFFS)
+
+/* MPCS registers */
+
+#define PCS40G_COMMON_CONTROL			0x14
+#define      FORWARD_ERROR_CORRECTION_MASK	BIT(1)
+
+#define PCS_CLOCK_RESET				0x14c
+#define      TX_SD_CLK_RESET_MASK		BIT(0)
+#define      RX_SD_CLK_RESET_MASK		BIT(1)
+#define      MAC_CLK_RESET_MASK			BIT(2)
+#define      CLK_DIVISION_RATIO_OFFS		4
+#define      CLK_DIVISION_RATIO_MASK		(0x7 << CLK_DIVISION_RATIO_OFFS)
+#define      CLK_DIV_PHASE_SET_MASK		BIT(11)
+
+/* System Soft Reset 1 */
+#define GOP_SOFT_RESET_1_REG			0x108
+#define     NETC_GOP_SOFT_RESET_OFFS		6
+#define     NETC_GOP_SOFT_RESET_MASK		(0x1 << \
+						 NETC_GOP_SOFT_RESET_OFFS)
+
+/* Ports Control 0 */
+#define NETCOMP_PORTS_CONTROL_0_REG		0x110
+#define     NETC_BUS_WIDTH_SELECT_OFFS		1
+#define     NETC_BUS_WIDTH_SELECT_MASK		(0x1 << \
+						 NETC_BUS_WIDTH_SELECT_OFFS)
+#define     NETC_GIG_RX_DATA_SAMPLE_OFFS	29
+#define     NETC_GIG_RX_DATA_SAMPLE_MASK	(0x1 << \
+						 NETC_GIG_RX_DATA_SAMPLE_OFFS)
+#define     NETC_CLK_DIV_PHASE_OFFS		31
+#define     NETC_CLK_DIV_PHASE_MASK		(0x1 << NETC_CLK_DIV_PHASE_OFFS)
+/* Ports Control 1 */
+#define NETCOMP_PORTS_CONTROL_1_REG		0x114
+#define     NETC_PORTS_ACTIVE_OFFSET(p)		(0 + p)
+#define     NETC_PORTS_ACTIVE_MASK(p)		(0x1 << \
+						 NETC_PORTS_ACTIVE_OFFSET(p))
+#define     NETC_PORT_GIG_RF_RESET_OFFS(p)	(28 + p)
+#define     NETC_PORT_GIG_RF_RESET_MASK(p)	(0x1 << \
+						 NETC_PORT_GIG_RF_RESET_OFFS(p))
+#define NETCOMP_CONTROL_0_REG			0x120
+#define     NETC_GBE_PORT0_SGMII_MODE_OFFS	0
+#define     NETC_GBE_PORT0_SGMII_MODE_MASK	(0x1 << \
+						 NETC_GBE_PORT0_SGMII_MODE_OFFS)
+#define     NETC_GBE_PORT1_SGMII_MODE_OFFS	1
+#define     NETC_GBE_PORT1_SGMII_MODE_MASK	(0x1 << \
+						 NETC_GBE_PORT1_SGMII_MODE_OFFS)
+#define     NETC_GBE_PORT1_MII_MODE_OFFS	2
+#define     NETC_GBE_PORT1_MII_MODE_MASK	(0x1 << \
+						 NETC_GBE_PORT1_MII_MODE_OFFS)
+
+#define MVPP22_SMI_MISC_CFG_REG			(MVPP22_SMI + 0x04)
 #define      MVPP22_SMI_POLLING_EN		BIT(10)
 
-#define MVPP22_PORT_BASE			0x30e00
-#define MVPP22_PORT_OFFSET			0x1000
+#define MVPP22_SMI_PHY_ADDR_REG(port)		(MVPP22_SMI + 0x04 + \
+						 (0x4 * (port)))
 
 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK	0xff

@@ -414,6 +517,50 @@ do {									\
 #define     MVPP2_PHY_ADDR_MASK			0x1f
 #define     MVPP2_PHY_REG_MASK			0x1f
 
+/* Additional PPv2.2 offsets */
+#define MVPP22_MPCS				0x007000
+#define MVPP22_XPCS				0x007400
+#define MVPP22_PORT_BASE			0x007e00
+#define MVPP22_PORT_OFFSET			0x001000
+#define MVPP22_RFU1				0x318000
+
+/* Maximum number of ports */
+#define MVPP22_GOP_MAC_NUM			4
+
+/* Sets the field located@the specified in data */
+#define MVPP2_RGMII_TX_FIFO_MIN_TH		0x41
+#define MVPP2_SGMII_TX_FIFO_MIN_TH		0x5
+#define MVPP2_SGMII2_5_TX_FIFO_MIN_TH		0xb
+
+enum mv_reset {RESET, UNRESET};
+
+/* Net Complex */
+enum mv_netc_topology {
+	MV_NETC_GE_MAC2_SGMII		=	BIT(0),
+	MV_NETC_GE_MAC3_SGMII		=	BIT(1),
+	MV_NETC_GE_MAC3_RGMII		=	BIT(2),
+};
+
+enum mv_netc_phase {
+	MV_NETC_FIRST_PHASE,
+	MV_NETC_SECOND_PHASE,
+};
+
+enum mv_netc_sgmii_xmi_mode {
+	MV_NETC_GBE_SGMII,
+	MV_NETC_GBE_XMII,
+};
+
+enum mv_netc_mii_mode {
+	MV_NETC_GBE_RGMII,
+	MV_NETC_GBE_MII,
+};
+
+enum mv_netc_lanes {
+	MV_NETC_LANE_23,
+	MV_NETC_LANE_45,
+};
+
 /* Various constants */
 
 /* Coalescing */

@@ -763,6 +910,12 @@ struct mvpp2 {
 	void __iomem *iface_base;
 	void __iomem *mdio_base;
 
+	void __iomem *mpcs_base;
+	void __iomem *xpcs_base;
+	void __iomem *rfu1_base;
+
+	u32 netc_config;
+
 	/* List of pointers to port structures */
 	struct mvpp2_port **port_list;

@@ -2833,6 +2986,570 @@ static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
 	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
 }
 
+/* PPv2.2 GoP/GMAC config */
+
+/* Set the MAC to reset or exit from reset */
+static int gop_gmac_reset(struct mvpp2_port *port, enum mv_reset reset)
+{
+	u32 val;
+
+	/* read - modify - write */
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	if (reset == RESET)
+		val |= MVPP2_GMAC_PORT_RESET_MASK;
+	else
+		val &= ~MVPP2_GMAC_PORT_RESET_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	return 0;
+}
+
+/*
+ * gop_gpcs_mode_cfg
+ *
+ * Configure port to working with Gig PCS or don't.
+ */
+static int gop_gpcs_mode_cfg(struct mvpp2_port *port, bool en)
+{
+	u32 val;
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	if (en)
+		val |= MVPP2_GMAC_PCS_ENABLE_MASK;
+	else
+		val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
+	/* enable / disable PCS on this port */
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	return 0;
+}
+
+static int gop_bypass_clk_cfg(struct mvpp2_port *port, bool en)
+{
+	u32 val;
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	if (en)
+		val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
+	else
+		val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
+	/* enable / disable PCS on this port */
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	return 0;
+}
+
+static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
+{
+	u32 val, thresh;
+
+	/*
+	 * Configure minimal level of the Tx FIFO before the lower part
+	 * starts to read a packet
+	 */
+	thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
+	val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+	val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+	val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
+	writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+
+	/* Disable bypass of sync module */
+	val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
+	val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
+	/* configure DP clock select according to mode */
+	val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
+	/* configure QSGMII bypass according to mode */
+	val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+	/*
+	 * Configure GIG MAC to 1000Base-X mode connected to a fiber
+	 * transceiver
+	 */
+	val |= MVPP2_GMAC_PORT_TYPE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+	/* configure AN 0x9268 */
+	val = MVPP2_GMAC_EN_PCS_AN |
+		MVPP2_GMAC_AN_BYPASS_EN |
+		MVPP2_GMAC_CONFIG_MII_SPEED  |
+		MVPP2_GMAC_CONFIG_GMII_SPEED     |
+		MVPP2_GMAC_FC_ADV_EN    |
+		MVPP2_GMAC_CONFIG_FULL_DUPLEX |
+		MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
+	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
+static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
+{
+	u32 val, thresh;
+
+	/*
+	 * Configure minimal level of the Tx FIFO before the lower part
+	 * starts to read a packet
+	 */
+	thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
+	val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+	val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+	val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
+	writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+
+	/* Disable bypass of sync module */
+	val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
+	val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
+	/* configure DP clock select according to mode */
+	val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
+	/* configure QSGMII bypass according to mode */
+	val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+	/* configure GIG MAC to SGMII mode */
+	val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+	/* configure AN */
+	val = MVPP2_GMAC_EN_PCS_AN |
+		MVPP2_GMAC_AN_BYPASS_EN |
+		MVPP2_GMAC_AN_SPEED_EN  |
+		MVPP2_GMAC_EN_FC_AN     |
+		MVPP2_GMAC_AN_DUPLEX_EN |
+		MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
+	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
+static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
+{
+	u32 val, thresh;
+
+	/*
+	 * Configure minimal level of the Tx FIFO before the lower part
+	 * starts to read a packet
+	 */
+	thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
+	val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+	val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+	val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
+	writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+
+	/* Disable bypass of sync module */
+	val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
+	val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
+	/* configure DP clock select according to mode */
+	val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
+	val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+	val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	val &= ~MVPP2_GMAC_PORT_DIS_PADING_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+	/* configure GIG MAC to SGMII mode */
+	val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+	/* configure AN 0xb8e8 */
+	val = MVPP2_GMAC_AN_BYPASS_EN |
+		MVPP2_GMAC_AN_SPEED_EN   |
+		MVPP2_GMAC_EN_FC_AN      |
+		MVPP2_GMAC_AN_DUPLEX_EN  |
+		MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
+	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+static int gop_gmac_mode_cfg(struct mvpp2_port *port)
+{
+	u32 val;
+
+	/* Set TX FIFO thresholds */
+	switch (port->phy_interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+		if (port->phy_speed == 2500)
+			gop_gmac_sgmii2_5_cfg(port);
+		else
+			gop_gmac_sgmii_cfg(port);
+		break;
+
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		gop_gmac_rgmii_cfg(port);
+		break;
+
+	default:
+		return -1;
+	}
+
+	/* Jumbo frame support - 0x1400*2= 0x2800 bytes */
+	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+	val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
+	val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
+	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+	/* PeriodicXonEn disable */
+	val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
+	val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
+
+	return 0;
+}
+
+static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
+{
+	u32 val;
+
+	/* relevant only for MAC0 (XLG0 and GMAC0) */
+	if (port->gop_id > 0)
+		return;
+
+	/* configure 1Gig MAC mode */
+	val = readl(port->base + MVPP22_XLG_CTRL3_REG);
+	val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+	val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
+	writel(val, port->base + MVPP22_XLG_CTRL3_REG);
+}
+
+static int gop_gpcs_reset(struct mvpp2_port *port, enum mv_reset act)
+{
+	u32 val;
+
+	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+	if (act == RESET)
+		val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
+	else
+		val |= MVPP2_GMAC_SGMII_MODE_MASK;
+	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+	return 0;
+}
+
+/*
+ * gop_port_init
+ *
+ * Init physical port. Configures the port mode and all it's elements
+ * accordingly.
+ * Does not verify that the selected mode/port number is valid at the
+ * core level.
+ */
+static int gop_port_init(struct mvpp2_port *port)
+{
+	int mac_num = port->gop_id;
+
+	if (mac_num >= MVPP22_GOP_MAC_NUM) {
+		netdev_err(NULL, "%s: illegal port number %d", __func__,
+			   mac_num);
+		return -1;
+	}
+
+	switch (port->phy_interface) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		gop_gmac_reset(port, RESET);
+
+		/* configure PCS */
+		gop_gpcs_mode_cfg(port, false);
+		gop_bypass_clk_cfg(port, true);
+
+		/* configure MAC */
+		gop_gmac_mode_cfg(port);
+		/* pcs unreset */
+		gop_gpcs_reset(port, UNRESET);
+
+		/* mac unreset */
+		gop_gmac_reset(port, UNRESET);
+		break;
+
+	case PHY_INTERFACE_MODE_SGMII:
+		/* configure PCS */
+		gop_gpcs_mode_cfg(port, true);
+
+		/* configure MAC */
+		gop_gmac_mode_cfg(port);
+		/* select proper Mac mode */
+		gop_xlg_2_gig_mac_cfg(port);
+
+		/* pcs unreset */
+		gop_gpcs_reset(port, UNRESET);
+		/* mac unreset */
+		gop_gmac_reset(port, UNRESET);
+		break;
+
+	default:
+		netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
+			   __func__, port->phy_interface);
+		return -1;
+	}
+
+	return 0;
+}
+
+static void gop_port_enable(struct mvpp2_port *port, bool enable)
+{
+	switch (port->phy_interface) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_SGMII:
+		if (enable)
+			mvpp2_port_enable(port);
+		else
+			mvpp2_port_disable(port);
+		break;
+
+	default:
+		netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
+			   port->phy_interface);
+		return;
+	}
+}
+
+/* RFU1 functions */
+static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
+{
+	return readl(priv->rfu1_base + offset);
+}
+
+static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
+{
+	writel(data, priv->rfu1_base + offset);
+}
+
+static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
+{
+	u32 val = 0;
+
+	if (gop_id == 2) {
+		if (phy_type == PHY_INTERFACE_MODE_SGMII)
+			val |= MV_NETC_GE_MAC2_SGMII;
+	}
+
+	if (gop_id == 3) {
+		if (phy_type == PHY_INTERFACE_MODE_SGMII)
+			val |= MV_NETC_GE_MAC3_SGMII;
+		else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
+			 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
+			val |= MV_NETC_GE_MAC3_RGMII;
+	}
+
+	return val;
+}
+
+static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
+	reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
+
+	val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
+	val &= NETC_PORTS_ACTIVE_MASK(gop_id);
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
+}
+
+static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
+	reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
+
+	val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
+	val &= NETC_GBE_PORT1_MII_MODE_MASK;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
+}
+
+static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
+	reg &= ~NETC_GOP_SOFT_RESET_MASK;
+
+	val <<= NETC_GOP_SOFT_RESET_OFFS;
+	val &= NETC_GOP_SOFT_RESET_MASK;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
+}
+
+static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
+	reg &= ~NETC_CLK_DIV_PHASE_MASK;
+
+	val <<= NETC_CLK_DIV_PHASE_OFFS;
+	val &= NETC_CLK_DIV_PHASE_MASK;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
+}
+
+static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
+	reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
+
+	val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
+	val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
+}
+
+static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
+					   u32 val)
+{
+	u32 reg, mask, offset;
+
+	if (gop_id == 2) {
+		mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
+		offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
+	} else {
+		mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
+		offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
+	}
+	reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
+	reg &= ~mask;
+
+	val <<= offset;
+	val &= mask;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
+}
+
+static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
+	reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
+
+	val <<= NETC_BUS_WIDTH_SELECT_OFFS;
+	val &= NETC_BUS_WIDTH_SELECT_MASK;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
+}
+
+static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
+{
+	u32 reg;
+
+	reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
+	reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
+
+	val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
+	val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
+
+	reg |= val;
+
+	gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
+}
+
+static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
+				  enum mv_netc_phase phase)
+{
+	switch (phase) {
+	case MV_NETC_FIRST_PHASE:
+		/* Set Bus Width to HB mode = 1 */
+		gop_netc_bus_width_select(priv, 1);
+		/* Select RGMII mode */
+		gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
+		break;
+
+	case MV_NETC_SECOND_PHASE:
+		/* De-assert the relevant port HB reset */
+		gop_netc_port_rf_reset(priv, gop_id, 1);
+		break;
+	}
+}
+
+static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
+				  enum mv_netc_phase phase)
+{
+	switch (phase) {
+	case MV_NETC_FIRST_PHASE:
+		/* Set Bus Width to HB mode = 1 */
+		gop_netc_bus_width_select(priv, 1);
+		/* Select SGMII mode */
+		if (gop_id >= 1) {
+			gop_netc_gbe_sgmii_mode_select(priv, gop_id,
+						       MV_NETC_GBE_SGMII);
+		}
+
+		/* Configure the sample stages */
+		gop_netc_sample_stages_timing(priv, 0);
+		/* Configure the ComPhy Selector */
+		/* gop_netc_com_phy_selector_config(netComplex); */
+		break;
+
+	case MV_NETC_SECOND_PHASE:
+		/* De-assert the relevant port HB reset */
+		gop_netc_port_rf_reset(priv, gop_id, 1);
+		break;
+	}
+}
+
+static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
+{
+	u32 c = priv->netc_config;
+
+	if (c & MV_NETC_GE_MAC2_SGMII)
+		gop_netc_mac_to_sgmii(priv, 2, phase);
+	else
+		gop_netc_mac_to_xgmii(priv, 2, phase);
+
+	if (c & MV_NETC_GE_MAC3_SGMII) {
+		gop_netc_mac_to_sgmii(priv, 3, phase);
+	} else {
+		gop_netc_mac_to_xgmii(priv, 3, phase);
+		if (c & MV_NETC_GE_MAC3_RGMII)
+			gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
+		else
+			gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
+	}
+
+	/* Activate gop ports 0, 2, 3 */
+	gop_netc_active_port(priv, 0, 1);
+	gop_netc_active_port(priv, 2, 1);
+	gop_netc_active_port(priv, 3, 1);
+
+	if (phase == MV_NETC_SECOND_PHASE) {
+		/* Enable the GOP internal clock logic */
+		gop_netc_gop_clock_logic_set(priv, 1);
+		/* De-assert GOP unit reset */
+		gop_netc_gop_reset(priv, 1);
+	}
+
+	return 0;
+}
+
 /* Set defaults to the MVPP2 port */
 static void mvpp2_defaults_set(struct mvpp2_port *port)
 {

@@ -3609,7 +4326,10 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
 	mvpp2_gmac_max_rx_size_set(port);
 	mvpp2_txp_max_tx_size_set(port);
 
-	mvpp2_port_enable(port);
+	if (port->priv->hw_version == MVPP21)
+		mvpp2_port_enable(port);
+	else
+		gop_port_enable(port, true);
 }
 
 /* Set hw internals when stopping port */

@@ -3619,7 +4339,11 @@ static void mvpp2_stop_dev(struct mvpp2_port *port)
 	mvpp2_ingress_disable(port);
 
 	mvpp2_egress_disable(port);
-	mvpp2_port_disable(port);
+
+	if (port->priv->hw_version == MVPP21)
+		mvpp2_port_disable(port);
+	else
+		gop_port_enable(port, false);
 }
 
 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)

@@ -3713,7 +4437,9 @@ static void mvpp2_port_power_up(struct mvpp2_port *port)
 {
 	struct mvpp2 *priv = port->priv;
 
-	mvpp2_port_mii_set(port);
+	/* On PPv2.2 the GoP / interface configuration has already been done */
+	if (priv->hw_version == MVPP21)
+		mvpp2_port_mii_set(port);
 	mvpp2_port_periodic_xon_disable(port);
 	if (priv->hw_version == MVPP21)
 		mvpp2_port_fc_adv_enable(port);

@@ -3733,7 +4459,10 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
 
 	/* Disable port */
 	mvpp2_egress_disable(port);
-	mvpp2_port_disable(port);
+	if (priv->hw_version == MVPP21)
+		mvpp2_port_disable(port);
+	else
+		gop_port_enable(port, false);
 
 	port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
 				  GFP_KERNEL);

@@ -4516,6 +5245,11 @@ static int mvpp2_base_probe(struct udevice *dev)
 			return PTR_ERR(priv->iface_base);
 
 		priv->mdio_base = priv->iface_base + MVPP22_SMI;
+
+		/* Store common base addresses for all ports */
+		priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
+		priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
+		priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
 	}
 
 	if (priv->hw_version == MVPP21)

@@ -4578,6 +5312,9 @@ static int mvpp2_probe(struct udevice *dev)
 
 		port->base = priv->iface_base + MVPP22_PORT_BASE +
 			port->gop_id * MVPP22_PORT_OFFSET;
+
+		/* GoP Init */
+		gop_port_init(port);
 	}
 
 	/* Initialize network controller */

@@ -4587,7 +5324,20 @@ static int mvpp2_probe(struct udevice *dev)
 		return err;
 	}
 
-	return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
+	err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
+	if (err)
+		return err;
+
+	if (priv->hw_version == MVPP22) {
+		priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
+							   port->phy_interface);
+
+		/* Netcomplex configurations for all ports */
+		gop_netc_init(priv, MV_NETC_FIRST_PHASE);
+		gop_netc_init(priv, MV_NETC_SECOND_PHASE);
+	}
+
+	return 0;
 }
 
 /*

Signature · 1 line

2.12.1

Joe Hershberger

2017-03-25 20:05 UTC #43 lore raw

PATCH v2 38/45 net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)

Quoted 24 lines · Stefan Roese

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only RGMII and SGMII support have been added, as these are the only interfaces that this code has been tested with.
Signed-off-by Stefan Roese <[email protected]>
Cc Stefan Chulski <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Joe Hershberger <[email protected]>
---
Changes in v2:
- New patch
 drivers/net/mvpp2.c | 766 +++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 758 insertions(+), 8 deletions(-)
drivers/net/mvpp2.c +0 -0
index 6f9a4137f8..76370faff0 100644

<snip>

drivers/net/mvpp2.c static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) · line 2992

Quoted 8 lines

drivers/net/mvpp2.c +4 -0

@@ -2833,6 +2986,570 @@ static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
        writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
 }
 
+/* PPv2.2 GoP/GMAC config */
+
+/* Set the MAC to reset or exit from reset */
+static int gop_gmac_reset(struct mvpp2_port *port, enum mv_reset reset)

Is this copied from somewhere? The enum parameter seems unnecessary. Why not just int for type?

Quoted 10 lines

drivers/net/mvpp2.c +10 -0

+{
+       u32 val;
+
+       /* read - modify - write */
+       val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+       if (reset == RESET)
+               val |= MVPP2_GMAC_PORT_RESET_MASK;
+       else
+               val &= ~MVPP2_GMAC_PORT_RESET_MASK;
+       writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);

drivers/net/mvpp2.c static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) · line 3012

Quoted 10 lines

drivers/net/mvpp2.c +10 -0

+
+       return 0;
+}
+
+/*
+ * gop_gpcs_mode_cfg
+ *
+ * Configure port to working with Gig PCS or don't.
+ */
+static int gop_gpcs_mode_cfg(struct mvpp2_port *port, bool en)

Similar here. Copied? Do we really use "bool" in U-Boot much? I care less about this one that the enum above, though.

Quoted 13 lines

drivers/net/mvpp2.c +13 -0

+{
+       u32 val;
+
+       val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+       if (en)
+               val |= MVPP2_GMAC_PCS_ENABLE_MASK;
+       else
+               val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
+       /* enable / disable PCS on this port */
+       writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+       return 0;
+}

<snip>

Stefan Roese

author

2017-03-27 11:17 UTC #44 lore raw

PATCH v2 38/45 net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)

Hi Joe,

Quoted 32 lines · Joe Hershberger

Quoted 24 lines · Stefan Roese
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only RGMII and SGMII support have been added, as these are the only interfaces that this code has been tested with.
Signed-off-by Stefan Roese <[email protected]>
Cc Stefan Chulski <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Joe Hershberger <[email protected]>
---
Changes in v2:
- New patch
 drivers/net/mvpp2.c | 766 +++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 758 insertions(+), 8 deletions(-)
drivers/net/mvpp2.c +0 -0
index 6f9a4137f8..76370faff0 100644
<snip>
Quoted 4 lines
drivers/net/mvpp2.c +0 -0
@@ -2833,6 +2986,570 @@ static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
        writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
 }
 

Quoted 7 lines

drivers/net/mvpp2.c static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) · line 2992
Quoted 4 lines
drivers/net/mvpp2.c +4 -0
+/* PPv2.2 GoP/GMAC config */
+
+/* Set the MAC to reset or exit from reset */
+static int gop_gmac_reset(struct mvpp2_port *port, enum mv_reset reset)
Is this copied from somewhere? The enum parameter seems unnecessary. Why not just int for type?

Yes, its copied from the original Marvell sources. And yes, I also am not fond of this additional enum (just forgot to get rid of it actually). I'll change it int instead.

Quoted 15 lines

drivers/net/mvpp2.c +15 -0

+{
+       u32 val;
+
+       /* read - modify - write */
+       val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+       if (reset == RESET)
+               val |= MVPP2_GMAC_PORT_RESET_MASK;
+       else
+               val &= ~MVPP2_GMAC_PORT_RESET_MASK;
+       writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+       return 0;
+}
+
+/*

Quoted 8 lines

drivers/net/mvpp2.c static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) · line 3012
Quoted 5 lines
drivers/net/mvpp2.c +5 -0
+ * gop_gpcs_mode_cfg
+ *
+ * Configure port to working with Gig PCS or don't.
+ */
+static int gop_gpcs_mode_cfg(struct mvpp2_port *port, bool en)
Similar here. Copied? Do we really use "bool" in U-Boot much? I care less about this one that the enum above, though.

Also copied, yes. "bool" is probably not used that much in U-Boot, even though somewhat in this Linux driver. I'll move to int though with these parameters.

Thanks,
Stefan

Stefan Roese

author

2017-03-23 16:02 UTC #45 lore raw

PATCH v2 39/45 net: mvpp2: Add GoP and NetC support for port 0 (SFI)

In reply to Stefan Roese

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver for the missing port 0. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only SFI support have been added, as this is the only interface that this code has been tested with. XAUI and RXAUI support might follow at a later stage.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Cc Joe Hershberger <[email protected]>

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 161 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 161 insertions(+)

drivers/net/mvpp2.c +161 -0

index 76370faff0..7b4f7a22bd 100644
@@ -3234,6 +3234,130 @@ static int gop_gpcs_reset(struct mvpp2_port *port, enum mv_reset act)
 	return 0;
 }
 
+/* Set the internal mux's to the required PCS in the PI */
+static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
+{
+	u32 val;
+	int lane;
+
+	switch (num_of_lanes) {
+	case 1:
+		lane = 0;
+		break;
+	case 2:
+		lane = 1;
+		break;
+	case 4:
+		lane = 2;
+		break;
+	default:
+		return -1;
+	}
+
+	/* configure XG MAC mode */
+	val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+	val &= ~MVPP22_XPCS_PCSMODE_OFFS;
+	val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
+	val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
+	writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+	return 0;
+}
+
+static int gop_mpcs_mode(struct mvpp2_port *port)
+{
+	u32 val;
+
+	/* configure PCS40G COMMON CONTROL */
+	val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+	val &= ~FORWARD_ERROR_CORRECTION_MASK;
+	writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+
+	/* configure PCS CLOCK RESET */
+	val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
+	val &= ~CLK_DIVISION_RATIO_MASK;
+	val |= 1 << CLK_DIVISION_RATIO_OFFS;
+	writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+	val &= ~CLK_DIV_PHASE_SET_MASK;
+	val |= MAC_CLK_RESET_MASK;
+	val |= RX_SD_CLK_RESET_MASK;
+	val |= TX_SD_CLK_RESET_MASK;
+	writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+	return 0;
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
+{
+	u32 val;
+
+	/* configure 10G MAC mode */
+	val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+	val |= MVPP22_XLG_RX_FC_EN;
+	writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+	val = readl(port->base + MVPP22_XLG_CTRL3_REG);
+	val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+	val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
+	writel(val, port->base + MVPP22_XLG_CTRL3_REG);
+
+	/* read - modify - write */
+	val = readl(port->base + MVPP22_XLG_CTRL4_REG);
+	val &= ~MVPP22_XLG_MODE_DMA_1G;
+	val |= MVPP22_XLG_FORWARD_PFC_EN;
+	val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
+	val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
+	writel(val, port->base + MVPP22_XLG_CTRL4_REG);
+
+	/* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
+	val = readl(port->base + MVPP22_XLG_CTRL1_REG);
+	val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
+	val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
+	writel(val, port->base + MVPP22_XLG_CTRL1_REG);
+
+	/* unmask link change interrupt */
+	val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+	val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
+	val |= 1; /* unmask summary bit */
+	writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+
+	return 0;
+}
+
+/* Set PCS to reset or exit from reset */
+static int gop_xpcs_reset(struct mvpp2_port *port, enum mv_reset reset)
+{
+	u32 val;
+
+	/* read - modify - write */
+	val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+	if (reset == RESET)
+		val &= ~MVPP22_XPCS_PCSRESET;
+	else
+		val |= MVPP22_XPCS_PCSRESET;
+	writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+	return 0;
+}
+
+/* Set the MAC to reset or exit from reset */
+static int gop_xlg_mac_reset(struct mvpp2_port *port, enum mv_reset reset)
+{
+	u32 val;
+
+	/* read - modify - write */
+	val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+	if (reset == RESET)
+		val &= ~MVPP22_XLG_MAC_RESETN;
+	else
+		val |= MVPP22_XLG_MAC_RESETN;
+	writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+	return 0;
+}
+
 /*
  * gop_port_init
  *

@@ -3245,6 +3369,7 @@ static int gop_gpcs_reset(struct mvpp2_port *port, enum mv_reset act)
 static int gop_port_init(struct mvpp2_port *port)
 {
 	int mac_num = port->gop_id;
+	int num_of_act_lanes;
 
 	if (mac_num >= MVPP22_GOP_MAC_NUM) {
 		netdev_err(NULL, "%s: illegal port number %d", __func__,

@@ -3285,6 +3410,22 @@ static int gop_port_init(struct mvpp2_port *port)
 		gop_gmac_reset(port, UNRESET);
 		break;
 
+	case PHY_INTERFACE_MODE_SFI:
+		num_of_act_lanes = 2;
+		mac_num = 0;
+		/* configure PCS */
+		gop_xpcs_mode(port, num_of_act_lanes);
+		gop_mpcs_mode(port);
+		/* configure MAC */
+		gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
+
+		/* pcs unreset */
+		gop_xpcs_reset(port, UNRESET);
+
+		/* mac unreset */
+		gop_xlg_mac_reset(port, UNRESET);
+		break;
+
 	default:
 		netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
 			   __func__, port->phy_interface);

@@ -3294,6 +3435,22 @@ static int gop_port_init(struct mvpp2_port *port)
 	return 0;
 }
 
+static void gop_xlg_mac_port_enable(struct mvpp2_port *port, bool enable)
+{
+	u32 val;
+
+	val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+	if (enable) {
+		/* Enable port and MIB counters update */
+		val |= MVPP22_XLG_PORT_EN;
+		val &= ~MVPP22_XLG_MIBCNT_DIS;
+	} else {
+		/* Disable port */
+		val &= ~MVPP22_XLG_PORT_EN;
+	}
+	writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+}
+
 static void gop_port_enable(struct mvpp2_port *port, bool enable)
 {
 	switch (port->phy_interface) {

@@ -3306,6 +3463,10 @@ static void gop_port_enable(struct mvpp2_port *port, bool enable)
 			mvpp2_port_disable(port);
 		break;
 
+	case PHY_INTERFACE_MODE_SFI:
+		gop_xlg_mac_port_enable(port, enable);
+
+		break;
 	default:
 		netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
 			   port->phy_interface);

Signature · 1 line

2.12.1

Joe Hershberger

2017-03-25 20:16 UTC #46 lore raw

PATCH v2 39/45 net: mvpp2: Add GoP and NetC support for port 0 (SFI)

Quoted 113 lines · Stefan Roese

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Cc Joe Hershberger <[email protected]>

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 161 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 161 insertions(+)

drivers/net/mvpp2.c +84 -0

index 76370faff0..7b4f7a22bd 100644
@@ -3234,6 +3234,130 @@ static int gop_gpcs_reset(struct mvpp2_port *port, enum mv_reset act)
        return 0;
 }
 
+/* Set the internal mux's to the required PCS in the PI */
+static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
+{
+       u32 val;
+       int lane;
+
+       switch (num_of_lanes) {
+       case 1:
+               lane = 0;
+               break;
+       case 2:
+               lane = 1;
+               break;
+       case 4:
+               lane = 2;
+               break;
+       default:
+               return -1;
+       }
+
+       /* configure XG MAC mode */
+       val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+       val &= ~MVPP22_XPCS_PCSMODE_OFFS;
+       val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
+       val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
+       writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+       return 0;
+}
+
+static int gop_mpcs_mode(struct mvpp2_port *port)
+{
+       u32 val;
+
+       /* configure PCS40G COMMON CONTROL */
+       val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+       val &= ~FORWARD_ERROR_CORRECTION_MASK;
+       writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+
+       /* configure PCS CLOCK RESET */
+       val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
+       val &= ~CLK_DIVISION_RATIO_MASK;
+       val |= 1 << CLK_DIVISION_RATIO_OFFS;
+       writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+       val &= ~CLK_DIV_PHASE_SET_MASK;
+       val |= MAC_CLK_RESET_MASK;
+       val |= RX_SD_CLK_RESET_MASK;
+       val |= TX_SD_CLK_RESET_MASK;
+       writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+       return 0;
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
+{
+       u32 val;
+
+       /* configure 10G MAC mode */
+       val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+       val |= MVPP22_XLG_RX_FC_EN;
+       writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+       val = readl(port->base + MVPP22_XLG_CTRL3_REG);
+       val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+       val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
+       writel(val, port->base + MVPP22_XLG_CTRL3_REG);
+
+       /* read - modify - write */
+       val = readl(port->base + MVPP22_XLG_CTRL4_REG);
+       val &= ~MVPP22_XLG_MODE_DMA_1G;
+       val |= MVPP22_XLG_FORWARD_PFC_EN;
+       val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
+       val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
+       writel(val, port->base + MVPP22_XLG_CTRL4_REG);
+
+       /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
+       val = readl(port->base + MVPP22_XLG_CTRL1_REG);
+       val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
+       val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
+       writel(val, port->base + MVPP22_XLG_CTRL1_REG);
+
+       /* unmask link change interrupt */

drivers/net/mvpp2.c static int gop_gpcs_reset(struct mvpp2_port *port, enum mv_reset act) · line 3330

Quoted 10 lines

drivers/net/mvpp2.c +10 -0

+       val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+       val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
+       val |= 1; /* unmask summary bit */
+       writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+
+       return 0;
+}
+
+/* Set PCS to reset or exit from reset */
+static int gop_xpcs_reset(struct mvpp2_port *port, enum mv_reset reset)

Same comment here on the enum for the reset command.

Quoted 105 lines

drivers/net/mvpp2.c +67 -1

+{
+       u32 val;
+
+       /* read - modify - write */
+       val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+       if (reset == RESET)
+               val &= ~MVPP22_XPCS_PCSRESET;
+       else
+               val |= MVPP22_XPCS_PCSRESET;
+       writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+       return 0;
+}
+
+/* Set the MAC to reset or exit from reset */
+static int gop_xlg_mac_reset(struct mvpp2_port *port, enum mv_reset reset)
+{
+       u32 val;
+
+       /* read - modify - write */
+       val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+       if (reset == RESET)
+               val &= ~MVPP22_XLG_MAC_RESETN;
+       else
+               val |= MVPP22_XLG_MAC_RESETN;
+       writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+       return 0;
+}
+
 /*
  * gop_port_init
  *

@@ -3245,6 +3369,7 @@ static int gop_gpcs_reset(struct mvpp2_port *port, enum mv_reset act)
 static int gop_port_init(struct mvpp2_port *port)
 {
        int mac_num = port->gop_id;
+       int num_of_act_lanes;
 
        if (mac_num >= MVPP22_GOP_MAC_NUM) {
                netdev_err(NULL, "%s: illegal port number %d", __func__,

@@ -3285,6 +3410,22 @@ static int gop_port_init(struct mvpp2_port *port)
                gop_gmac_reset(port, UNRESET);
                break;
 
+       case PHY_INTERFACE_MODE_SFI:
+               num_of_act_lanes = 2;
+               mac_num = 0;
+               /* configure PCS */
+               gop_xpcs_mode(port, num_of_act_lanes);
+               gop_mpcs_mode(port);
+               /* configure MAC */
+               gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
+
+               /* pcs unreset */
+               gop_xpcs_reset(port, UNRESET);
+
+               /* mac unreset */
+               gop_xlg_mac_reset(port, UNRESET);
+               break;
+
        default:
                netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
                           __func__, port->phy_interface);

@@ -3294,6 +3435,22 @@ static int gop_port_init(struct mvpp2_port *port)
        return 0;
 }
 
+static void gop_xlg_mac_port_enable(struct mvpp2_port *port, bool enable)
+{
+       u32 val;
+
+       val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+       if (enable) {
+               /* Enable port and MIB counters update */
+               val |= MVPP22_XLG_PORT_EN;
+               val &= ~MVPP22_XLG_MIBCNT_DIS;
+       } else {
+               /* Disable port */
+               val &= ~MVPP22_XLG_PORT_EN;
+       }
+       writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+}
+
 static void gop_port_enable(struct mvpp2_port *port, bool enable)
 {
        switch (port->phy_interface) {

@@ -3306,6 +3463,10 @@ static void gop_port_enable(struct mvpp2_port *port, bool enable)
                        mvpp2_port_disable(port);
                break;
 
+       case PHY_INTERFACE_MODE_SFI:
+               gop_xlg_mac_port_enable(port, enable);
+
+               break;
        default:
                netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
                           port->phy_interface);
--

2.12.1

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
https://lists.denx.de/listinfo/u-boot

Stefan Roese

author

2017-03-23 16:02 UTC #47 lore raw

PATCH v2 40/45 net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID

In reply to Stefan Roese

Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should be handled identical to PHY_INTERFACE_MODE_RGMII.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Cc Joe Hershberger <[email protected]>

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 1 +
 1 file changed, 1 insertion(+)

drivers/net/mvpp2.c +1 -0

index 7b4f7a22bd..d20d82e017 100644
@@ -2895,6 +2895,7 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
 		val |= MVPP2_GMAC_INBAND_AN_MASK;
 		break;
 	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
 		val |= MVPP2_GMAC_PORT_RGMII_MASK;
 	default:
 		val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;

Signature · 1 line

2.12.1

Joe Hershberger

2017-03-25 21:34 UTC #48 lore raw

PATCH v2 40/45 net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID

Quoted 8 lines · Stefan Roese

Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should be handled identical to PHY_INTERFACE_MODE_RGMII.
Signed-off-by Stefan Roese <[email protected]>
Cc Stefan Chulski <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Joe Hershberger <[email protected]>

Acked-by Joe Hershberger <[email protected]>

Stefan Roese

author

2017-03-23 16:02 UTC #49 lore raw

PATCH v2 41/45 net: mvpp2: Enable PHY polling mode on PPv2.2

In reply to Stefan Roese

Testing shows, that PHY polling needs to be enabled on Armada 7k/8k. Otherwise ethernet transfers will not work correctly. PHY polling is enabled per default after reset, so we do not need to specifically enable it, but this makes it clearer.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

drivers/net/mvpp2.c +3 -2

index d20d82e017..cc6d42255c 100644
@@ -4966,14 +4966,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 	if (priv->hw_version == MVPP22)
 		mvpp2_axi_init(priv);
 
-	/* Disable HW PHY polling */
 	if (priv->hw_version == MVPP21) {
+		/* Disable HW PHY polling */
 		val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
 		val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
 		writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
 	} else {
+		/* Enable HW PHY polling */
 		val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
-		val &= ~MVPP22_SMI_POLLING_EN;
+		val |= MVPP22_SMI_POLLING_EN;
 		writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
 	}

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:02 UTC #50 lore raw

PATCH v2 42/45 net: mvpp2: Configure SMI PHY address needed for PHY polling

In reply to Stefan Roese

On PPv2.2 we enable PHY polling, so we also need to configure the PHY address in the specific PHY address rgisters.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

drivers/net/mvpp2.c +11 -0

index cc6d42255c..086ce32851 100644
@@ -5338,6 +5338,14 @@ static void mvpp2_stop(struct udevice *dev)
 	mvpp2_cleanup_txqs(port);
 }
 
+static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
+{
+	writel(port->phyaddr, port->priv->iface_base +
+	       MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
+
+	return 0;
+}
+
 static int mvpp2_base_probe(struct udevice *dev)
 {
 	struct mvpp2 *priv = dev_get_priv(dev);

@@ -5476,6 +5484,9 @@ static int mvpp2_probe(struct udevice *dev)
 		port->base = priv->iface_base + MVPP22_PORT_BASE +
 			port->gop_id * MVPP22_PORT_OFFSET;
 
+		/* Set phy address of the port */
+		mvpp22_smi_phy_addr_cfg(port);
+
 		/* GoP Init */
 		gop_port_init(port);
 	}

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:02 UTC #51 lore raw

PATCH v2 43/45 net: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_pool

In reply to Stefan Roese

As pointed out by Stefan Chulski, this variable is unused and should be removed.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe
- Fixed small typo in commit text

 drivers/net/mvpp2.c | 4 ----
 1 file changed, 4 deletions(-)

drivers/net/mvpp2.c +0 -4

index 086ce32851..ec985977ba 100644
@@ -1247,9 +1247,6 @@ struct mvpp2_bm_pool {
 
 	/* Ports using BM pool */
 	u32 port_map;
-
-	/* Occupied buffers indicator */
-	int in_use_thresh;
 };
 
 /* Static declaractions */

@@ -2801,7 +2798,6 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 
 	/* Update BM driver with number of buffers added to pool */
 	bm_pool->buf_num += i;
-	bm_pool->in_use_thresh = bm_pool->buf_num / 4;
 
 	return i;
 }

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:02 UTC #52 lore raw

PATCH v2 44/45 arm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G

In reply to Stefan Roese

The default configuration for the COMPHY-0 port should be 1G, as its used as 1G SGMII connection. This change is necessary to get the MAC2 port (SGMII) working on this DB.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 arch/arm/dts/armada-7040-db.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/dts/armada-7040-db.dts +1 -1

index 776bc7831d..84e0dbdc3d 100644
@@ -159,7 +159,7 @@
 &cpm_comphy {
 	phy0 {
 		phy-type = <PHY_TYPE_SGMII2>;
-		phy-speed = <PHY_SPEED_3_125G>;
+		phy-speed = <PHY_SPEED_1_25G>;
 	};
 
 	phy1 {

Signature · 1 line

2.12.1

Stefan Roese

author

2017-03-23 16:02 UTC #53 lore raw

PATCH v2 45/45 arm64: mvebu: Enable CONFIG_PHY_MARVELL in Armada7k/8k-DB defconfig

In reply to Stefan Roese

The Marvell PHY support is needed espescially for the A7040-DB with the SGMII port (port 2). As without the marvell PHY driver configuration for SGMII, ethernet won't work.

Signed-off-by Stefan Roese <[email protected]>

Cc Stefan Chulski <[email protected]>

Cc Kostya Porotchkin <[email protected]>

Cc Nadav Haklai <[email protected]>

Acked-by Joe Hershberger <[email protected]>

---

Changes in v2:
- Added Acked-by from Joe

 configs/mvebu_db-88f7040_defconfig | 1 +
 configs/mvebu_db-88f8040_defconfig | 1 +
 2 files changed, 2 insertions(+)

configs/mvebu_db-88f7040_defconfig +1 -0

index fdafeb6607..797eabbfab 100644
@@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
 CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y

configs/mvebu_db-88f8040_defconfig +1 -0

index 9866e19778..046da09786 100644
@@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
 CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y

Signature · 1 line

2.12.1

Joe Hershberger

2017-03-25 21:42 UTC #54 lore raw

v2 cover Add PPv2.2 support to the mvpp2 ethernet driver and enable it for A7k/8k

In reply to Stefan Roese

Hi Stefan,

Quoted 10 lines · Stefan Roese

This patchset does the following things:
- It brings the latest Linux changes from the mvpp2 ethernet driver done by Thomas Petazzoni to the U-Boot version of this driver. This enables the usage of this driver on the new Marvell Armada 7k / 8k ARMv8 SoCs.
- This driver is enabled for the currently available Armada 7k / 8k boards and the necessary configuration is done to the config header.

Quoted 7 lines

v2 status:
The GoP / NetC patch has been split into multiple smaller patches for easier review. The code for untested / unsupported interfaces (like QSGMII, XAUI and RXAUI) has been removed for now.
Thanks,
Stefan

I think you should be good to go to pull this into your board tree.

Cheers,
-Joe

Stefan Roese

author

2017-03-27 12:02 UTC #55 lore raw

v2 cover Add PPv2.2 support to the mvpp2 ethernet driver and enable it for A7k/8k

Hi Joe,

Quoted 16 lines · Joe Hershberger

Quoted 15 lines · Stefan Roese
This patchset does the following things:
- It brings the latest Linux changes from the mvpp2 ethernet driver done by Thomas Petazzoni to the U-Boot version of this driver. This enables the usage of this driver on the new Marvell Armada 7k / 8k ARMv8 SoCs.
- This driver is enabled for the currently available Armada 7k / 8k boards and the necessary configuration is done to the config header.
v2 status:
The GoP / NetC patch has been split into multiple smaller patches for easier review. The code for untested / unsupported interfaces (like QSGMII, XAUI and RXAUI) has been removed for now.

Quoted 4 lines

Quoted 2 lines
Thanks,
Stefan
I think you should be good to go to pull this into your board tree.

Thanks Joe. I've just sent a v3 for the 2 GoP / NetC patches, with the mv_reset enum removed. If this is okay, I'll pull the complete patchset later this week via the mvebu tree.

Thanks,
Stefan

Stefan Roese

author

2017-03-29 09:24 UTC #56 lore raw

v2 cover Add PPv2.2 support to the mvpp2 ethernet driver and enable it for A7k/8k

In reply to Stefan Roese

Quoted 7 lines · Stefan Roese

This patchset does the following things:
- It brings the latest Linux changes from the mvpp2 ethernet driver done by Thomas Petazzoni to the U-Boot version of this driver. This enables the usage of this driver on the new Marvell Armada 7k / 8k ARMv8 SoCs.

Quoted 7 lines

- This driver is enabled for the currently available Armada 7k / 8k boards and the necessary configuration is done to the config header.
v2 status:
The GoP / NetC patch has been split into multiple smaller patches for easier review. The code for untested / unsupported interfaces (like QSGMII, XAUI and RXAUI) has been removed for now.

v3 now applied to u-boot-marvell/master.

Thanks,
Stefan