ARM: dts: alpine: fix PCIe node name
Subsystems (10)
Rob Herring
maintainerPATCH 1/15 ARM: dts: alpine: fix PCIe node name
PCIe bridges should have a node name of 'pcie'.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm/boot/dts/alpine.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/alpine.dtsi +1 -1
@@ -139,7 +139,7 @@ }; /* Internal PCIe Controller */ - pcie-internal at 0xfbc00000 { + pcie at fbc00000 { compatible = "pci-host-ecam-generic"; device_type = "pci"; #size-cells = <2>;
Signature · 1 line
2.10.1
Rob Herring
maintainerPATCH 2/15 ARM: dts: marvell: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
Documentation/devicetree/bindings/pci/mvebu-pci.txt | 2 +- arch/arm/boot/dts/armada-370.dtsi | 4 +++- arch/arm/boot/dts/armada-375.dtsi | 4 +++- arch/arm/boot/dts/armada-380.dtsi | 5 ++++- arch/arm/boot/dts/armada-385-db-ap.dts | 2 +- arch/arm/boot/dts/armada-385-linksys.dtsi | 2 +- arch/arm/boot/dts/armada-385-turris-omnia.dts | 2 +- arch/arm/boot/dts/armada-385.dtsi | 6 +++++- arch/arm/boot/dts/armada-388-clearfog.dts | 2 +- arch/arm/boot/dts/armada-388-clearfog.dtsi | 2 +- arch/arm/boot/dts/armada-388-db.dts | 2 +- arch/arm/boot/dts/armada-388-gp.dts | 2 +- arch/arm/boot/dts/armada-388-rd.dts | 2 +- arch/arm/boot/dts/armada-390-db.dts | 2 +- arch/arm/boot/dts/armada-395-gp.dts | 2 +- arch/arm/boot/dts/armada-398-db.dts | 2 +- arch/arm/boot/dts/armada-39x.dtsi | 6 +++++- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 3 ++- arch/arm/boot/dts/armada-xp-db.dts | 2 +- arch/arm/boot/dts/armada-xp-gp.dts | 2 +- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 7 ++++++- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 11 ++++++++++- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 14 ++++++++++++-- arch/arm/boot/dts/dove-d3plug.dts | 4 ++-- arch/arm/boot/dts/dove.dtsi | 8 +++++--- arch/arm/boot/dts/kirkwood-6192.dtsi | 3 ++- arch/arm/boot/dts/kirkwood-6281.dtsi | 3 ++- arch/arm/boot/dts/kirkwood-6282.dtsi | 4 +++- arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 3 ++- 29 files changed, 80 insertions(+), 33 deletions(-)
Documentation/devicetree/bindings/pci/mvebu-pci.txt +1 -1
@@ -286,7 +286,7 @@ pcie-controller { status = "disabled"; }; - pcie at 10,0 { + pcie at a,0 { device_type = "pci"; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; reg = <0x5000 0 0 0 0>;
arch/arm/boot/dts/armada-370.dtsi +3 -1
@@ -72,7 +72,7 @@ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; }; - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";
@@ -100,6 +100,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;
@@ -117,6 +118,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;
arch/arm/boot/dts/armada-375.dtsi +3 -1
@@ -582,7 +582,7 @@ }; }; - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";
@@ -610,6 +610,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;
@@ -627,6 +628,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;
arch/arm/boot/dts/armada-380.dtsi +4 -1
@@ -71,7 +71,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";
@@ -104,6 +104,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;
@@ -122,6 +123,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;
@@ -140,6 +142,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;
arch/arm/boot/dts/armada-385-db-ap.dts +1 -1
@@ -209,7 +209,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /*
arch/arm/boot/dts/armada-385-linksys.dtsi +1 -1
@@ -241,7 +241,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie at 1,0 {
arch/arm/boot/dts/armada-385-turris-omnia.dts +1 -1
@@ -96,7 +96,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie at 1,0 {
arch/arm/boot/dts/armada-385.dtsi +5 -1
@@ -76,7 +76,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";
@@ -115,6 +115,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;
@@ -133,6 +134,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;
@@ -151,6 +153,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;
@@ -172,6 +175,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>;
arch/arm/boot/dts/armada-388-clearfog.dts +1 -1
@@ -62,7 +62,7 @@ }; }; - pcie-controller { + pcie { pcie at 3,0 { /* Port 2, Lane 0. CON2, nearest CPU. */ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
arch/arm/boot/dts/armada-388-clearfog.dtsi +1 -1
@@ -104,7 +104,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * The two PCIe units are accessible through
arch/arm/boot/dts/armada-388-db.dts +1 -1
@@ -172,7 +172,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /* * The two PCIe units are accessible through
arch/arm/boot/dts/armada-388-gp.dts +1 -1
@@ -240,7 +240,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /* * One PCIe units is accessible through
arch/arm/boot/dts/armada-388-rd.dts +1 -1
@@ -117,7 +117,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * One PCIe units is accessible through
arch/arm/boot/dts/armada-390-db.dts +1 -1
@@ -123,7 +123,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* CON30 */
arch/arm/boot/dts/armada-395-gp.dts +1 -1
@@ -139,7 +139,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /*
arch/arm/boot/dts/armada-398-db.dts +1 -1
@@ -118,7 +118,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie at 1,0 {
arch/arm/boot/dts/armada-39x.dtsi +5 -1
@@ -442,7 +442,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";
@@ -481,6 +481,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;
@@ -499,6 +500,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;
@@ -517,6 +519,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;
@@ -538,6 +541,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>;
arch/arm/boot/dts/armada-xp-98dx3236.dtsi +2 -1
@@ -81,7 +81,7 @@ /* * 98DX3236 has 1 x1 PCIe unit Gen2.0 */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";
@@ -107,6 +107,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;
arch/arm/boot/dts/armada-xp-db.dts +1 -1
@@ -242,7 +242,7 @@ /* Port 2, Lane 0 */ status = "okay"; }; - pcie at 10,0 { + pcie at a,0 { /* Port 3, Lane 0 */ status = "okay"; };
arch/arm/boot/dts/armada-xp-gp.dts +1 -1
@@ -227,7 +227,7 @@ /* Port 2, Lane 0 */ status = "okay"; }; - pcie at 10,0 { + pcie at a,0 { /* Port 3, Lane 0 */ status = "okay"; };
arch/arm/boot/dts/armada-xp-mv78230.dtsi +6 -1
@@ -86,7 +86,7 @@ * configured as x4 or quad x1 lanes. One unit is * x1 only. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";
@@ -123,6 +123,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;
@@ -140,6 +141,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;
@@ -157,6 +159,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;
@@ -174,6 +177,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;
@@ -191,6 +195,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;
arch/arm/boot/dts/armada-xp-mv78260.dtsi +10 -1
@@ -87,7 +87,7 @@ * configured as x4 or quad x1 lanes. One unit is * x4 only. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";
@@ -138,6 +138,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;
@@ -155,6 +156,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;
@@ -172,6 +174,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;
@@ -189,6 +192,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;
@@ -206,6 +210,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;
@@ -223,6 +228,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>;
@@ -240,6 +246,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>;
@@ -257,6 +264,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>;
@@ -274,6 +282,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>;
arch/arm/boot/dts/armada-xp-mv78460.dtsi +12 -2
@@ -104,7 +104,7 @@ * configured as x4 or quad x1 lanes. Two units are * x4/x1. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";
@@ -159,6 +159,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;
@@ -176,6 +177,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;
@@ -193,6 +195,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;
@@ -210,6 +213,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;
@@ -227,6 +231,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;
@@ -244,6 +249,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>;
@@ -261,6 +267,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>;
@@ -278,6 +285,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>;
@@ -295,6 +303,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>;
@@ -303,7 +312,7 @@ status = "disabled"; }; - pcie10: pcie at 10,0 { + pcie10: pcie at a,0 { device_type = "pci"; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; reg = <0x5000 0 0 0 0>;
@@ -312,6 +321,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 0x81000000 0 0 0x81000000 0xa 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 103>; marvell,pcie-port = <3>;
arch/arm/boot/dts/dove-d3plug.dts +2 -2
@@ -88,7 +88,7 @@ &pcie { status = "okay"; /* Fresco Logic USB3.0 xHCI controller */ - pcie-port at 0 { + pcie at 1 { status = "okay"; reset-gpios = <&gpio0 26 1>; reset-delay-us = <20000>;
@@ -96,7 +96,7 @@ pinctrl-names = "default"; }; /* Mini-PCIe slot */ - pcie-port at 1 { + pcie at 2 { status = "okay"; reset-gpios = <&gpio0 25 1>; };
arch/arm/boot/dts/dove.dtsi +5 -3
@@ -89,7 +89,7 @@ MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ - pcie: pcie-controller { + pcie: pcie { compatible = "marvell,dove-pcie"; status = "disabled"; device_type = "pci";
@@ -106,7 +106,7 @@ 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ - pcie0: pcie-port at 0 { + pcie0: pcie at 1 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
@@ -118,13 +118,14 @@ #size-cells = <2>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 16>; }; - pcie1: pcie-port at 1 { + pcie1: pcie at 2 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
@@ -136,6 +137,7 @@ #size-cells = <2>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>;
arch/arm/boot/dts/kirkwood-6192.dtsi +2 -1
@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";
@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;
arch/arm/boot/dts/kirkwood-6281.dtsi +2 -1
@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";
@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;
arch/arm/boot/dts/kirkwood-6282.dtsi +3 -1
@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";
@@ -28,6 +28,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;
@@ -45,6 +46,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 10>; marvell,pcie-port = <1>;
arch/arm/boot/dts/kirkwood-98dx4122.dtsi +2 -1
@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";
@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;
Signature · 1 line
2.10.1
PATCH 2/15 ARM: dts: marvell: fix PCI bus dtc warnings
Hi Rob,
Quoted 1 line · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Could you rebase your patch on mvebu/dt or linux-next because it doesn't apply as is.
Thanks,
Gregory
Quoted 829 lines
Signed-off-by Rob Herring <[email protected]>Cc Bjorn Helgaas <[email protected]>Cc Jason Cooper <[email protected]>Cc Andrew Lunn <[email protected]>Cc Gregory Clement <[email protected]>Cc Sebastian Hesselbarth <[email protected]>---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.Documentation/devicetree/bindings/pci/mvebu-pci.txt | 2 +- arch/arm/boot/dts/armada-370.dtsi | 4 +++- arch/arm/boot/dts/armada-375.dtsi | 4 +++- arch/arm/boot/dts/armada-380.dtsi | 5 ++++- arch/arm/boot/dts/armada-385-db-ap.dts | 2 +- arch/arm/boot/dts/armada-385-linksys.dtsi | 2 +- arch/arm/boot/dts/armada-385-turris-omnia.dts | 2 +- arch/arm/boot/dts/armada-385.dtsi | 6 +++++- arch/arm/boot/dts/armada-388-clearfog.dts | 2 +- arch/arm/boot/dts/armada-388-clearfog.dtsi | 2 +- arch/arm/boot/dts/armada-388-db.dts | 2 +- arch/arm/boot/dts/armada-388-gp.dts | 2 +- arch/arm/boot/dts/armada-388-rd.dts | 2 +- arch/arm/boot/dts/armada-390-db.dts | 2 +- arch/arm/boot/dts/armada-395-gp.dts | 2 +- arch/arm/boot/dts/armada-398-db.dts | 2 +- arch/arm/boot/dts/armada-39x.dtsi | 6 +++++- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 3 ++- arch/arm/boot/dts/armada-xp-db.dts | 2 +- arch/arm/boot/dts/armada-xp-gp.dts | 2 +- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 7 ++++++- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 11 ++++++++++- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 14 ++++++++++++-- arch/arm/boot/dts/dove-d3plug.dts | 4 ++-- arch/arm/boot/dts/dove.dtsi | 8 +++++--- arch/arm/boot/dts/kirkwood-6192.dtsi | 3 ++- arch/arm/boot/dts/kirkwood-6281.dtsi | 3 ++- arch/arm/boot/dts/kirkwood-6282.dtsi | 4 +++- arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 3 ++- 29 files changed, 80 insertions(+), 33 deletions(-)Documentation/devicetree/bindings/pci/mvebu-pci.txt +1
-1@@ -286,7 +286,7 @@ pcie-controller { status = "disabled"; }; - pcie at 10,0 { + pcie at a,0 { device_type = "pci"; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; reg = <0x5000 0 0 0 0>;arch/arm/boot/dts/armada-370.dtsi +3
-1@@ -72,7 +72,7 @@ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; }; - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";@@ -100,6 +100,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;@@ -117,6 +118,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;arch/arm/boot/dts/armada-375.dtsi +3
-1@@ -582,7 +582,7 @@ }; }; - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";@@ -610,6 +610,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;@@ -627,6 +628,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;arch/arm/boot/dts/armada-380.dtsi +4
-1@@ -71,7 +71,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";@@ -104,6 +104,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;@@ -122,6 +123,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;@@ -140,6 +142,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;arch/arm/boot/dts/armada-385-db-ap.dts +1
-1@@ -209,7 +209,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /*arch/arm/boot/dts/armada-385-linksys.dtsi +1
-1@@ -241,7 +241,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie at 1,0 {arch/arm/boot/dts/armada-385-turris-omnia.dts +1
-1@@ -96,7 +96,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie at 1,0 {arch/arm/boot/dts/armada-385.dtsi +5
-1@@ -76,7 +76,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";@@ -115,6 +115,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;@@ -133,6 +134,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;@@ -151,6 +153,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;@@ -172,6 +175,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>;arch/arm/boot/dts/armada-388-clearfog.dts +1
-1@@ -62,7 +62,7 @@ }; }; - pcie-controller { + pcie { pcie at 3,0 { /* Port 2, Lane 0. CON2, nearest CPU. */ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;arch/arm/boot/dts/armada-388-clearfog.dtsi +1
-1@@ -104,7 +104,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * The two PCIe units are accessible througharch/arm/boot/dts/armada-388-db.dts +1
-1@@ -172,7 +172,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /* * The two PCIe units are accessible througharch/arm/boot/dts/armada-388-gp.dts +1
-1@@ -240,7 +240,7 @@ status = "okay"; }; - pcie-controller { + pcie { status = "okay"; /* * One PCIe units is accessible througharch/arm/boot/dts/armada-388-rd.dts +1
-1@@ -117,7 +117,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* * One PCIe units is accessible througharch/arm/boot/dts/armada-390-db.dts +1
-1@@ -123,7 +123,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /* CON30 */arch/arm/boot/dts/armada-395-gp.dts +1
-1@@ -139,7 +139,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; /*arch/arm/boot/dts/armada-398-db.dts +1
-1@@ -118,7 +118,7 @@ }; }; - pcie-controller { + pcie { status = "okay"; pcie at 1,0 {arch/arm/boot/dts/armada-39x.dtsi +5
-1@@ -442,7 +442,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci";@@ -481,6 +481,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>;@@ -499,6 +500,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>;@@ -517,6 +519,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>;@@ -538,6 +541,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>;arch/arm/boot/dts/armada-xp-98dx3236.dtsi +2
-1@@ -81,7 +81,7 @@ /* * 98DX3236 has 1 x1 PCIe unit Gen2.0 */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";@@ -107,6 +107,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;arch/arm/boot/dts/armada-xp-db.dts +1
-1@@ -242,7 +242,7 @@ /* Port 2, Lane 0 */ status = "okay"; }; - pcie at 10,0 { + pcie at a,0 { /* Port 3, Lane 0 */ status = "okay"; };arch/arm/boot/dts/armada-xp-gp.dts +1
-1@@ -227,7 +227,7 @@ /* Port 2, Lane 0 */ status = "okay"; }; - pcie at 10,0 { + pcie at a,0 { /* Port 3, Lane 0 */ status = "okay"; };arch/arm/boot/dts/armada-xp-mv78230.dtsi +6
-1@@ -86,7 +86,7 @@ * configured as x4 or quad x1 lanes. One unit is * x1 only. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";@@ -123,6 +123,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;@@ -140,6 +141,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;@@ -157,6 +159,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;@@ -174,6 +177,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;@@ -191,6 +195,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;arch/arm/boot/dts/armada-xp-mv78260.dtsi +10
-1@@ -87,7 +87,7 @@ * configured as x4 or quad x1 lanes. One unit is * x4 only. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";@@ -138,6 +138,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;@@ -155,6 +156,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;@@ -172,6 +174,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;@@ -189,6 +192,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;@@ -206,6 +210,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;@@ -223,6 +228,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>;@@ -240,6 +246,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>;@@ -257,6 +264,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>;@@ -274,6 +282,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>;arch/arm/boot/dts/armada-xp-mv78460.dtsi +12
-2@@ -104,7 +104,7 @@ * configured as x4 or quad x1 lanes. Two units are * x4/x1. */ - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci";@@ -159,6 +159,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 58>; marvell,pcie-port = <0>;@@ -176,6 +177,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>;@@ -193,6 +195,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 60>; marvell,pcie-port = <0>;@@ -210,6 +213,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 61>; marvell,pcie-port = <0>;@@ -227,6 +231,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 62>; marvell,pcie-port = <1>;@@ -244,6 +249,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 63>; marvell,pcie-port = <1>;@@ -261,6 +267,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 64>; marvell,pcie-port = <1>;@@ -278,6 +285,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 65>; marvell,pcie-port = <1>;@@ -295,6 +303,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 99>; marvell,pcie-port = <2>;@@ -303,7 +312,7 @@ status = "disabled"; }; - pcie10: pcie at 10,0 { + pcie10: pcie at a,0 { device_type = "pci"; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; reg = <0x5000 0 0 0 0>;@@ -312,6 +321,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 0x81000000 0 0 0x81000000 0xa 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 103>; marvell,pcie-port = <3>;arch/arm/boot/dts/dove-d3plug.dts +2
-2@@ -88,7 +88,7 @@ &pcie { status = "okay"; /* Fresco Logic USB3.0 xHCI controller */ - pcie-port at 0 { + pcie at 1 { status = "okay"; reset-gpios = <&gpio0 26 1>; reset-delay-us = <20000>;@@ -96,7 +96,7 @@ pinctrl-names = "default"; }; /* Mini-PCIe slot */ - pcie-port at 1 { + pcie at 2 { status = "okay"; reset-gpios = <&gpio0 25 1>; };arch/arm/boot/dts/dove.dtsi +5
-3@@ -89,7 +89,7 @@ MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ - pcie: pcie-controller { + pcie: pcie { compatible = "marvell,dove-pcie"; status = "disabled"; device_type = "pci";@@ -106,7 +106,7 @@ 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ - pcie0: pcie-port at 0 { + pcie0: pcie at 1 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;@@ -118,13 +118,14 @@ #size-cells = <2>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 16>; }; - pcie1: pcie-port at 1 { + pcie1: pcie at 2 { device_type = "pci"; status = "disabled"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;@@ -136,6 +137,7 @@ #size-cells = <2>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>;arch/arm/boot/dts/kirkwood-6192.dtsi +2
-1@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;arch/arm/boot/dts/kirkwood-6281.dtsi +2
-1@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;arch/arm/boot/dts/kirkwood-6282.dtsi +3
-1@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";@@ -28,6 +28,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;@@ -45,6 +46,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 10>; marvell,pcie-port = <1>;arch/arm/boot/dts/kirkwood-98dx4122.dtsi +2
-1@@ -1,6 +1,6 @@ / { mbus at f1000000 { - pciec: pcie-controller at 82000000 { + pciec: pcie at 82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci";@@ -24,6 +24,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 9>; marvell,pcie-port = <0>;Signature · 1 line
2.10.1
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Rob Herring
maintainerPATCH 3/15 ARM: dts: ti: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm/boot/dts/dra7.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/boot/dts/dra7.dtsi +2 -0
@@ -283,6 +283,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x20013000 0x13000 0 0xffed000>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; linux,pci-domain = <0>;
@@ -319,6 +320,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x30013000 0x13000 0 0xffed000>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; linux,pci-domain = <1>;
Signature · 1 line
2.10.1
Rob Herring
maintainerPATCH 4/15 ARM: dts: exynos: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm/boot/dts/exynos5440.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/boot/dts/exynos5440.dtsi +2 -0
@@ -306,6 +306,7 @@ ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 53>;
@@ -329,6 +330,7 @@ ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 56>;
Signature · 1 line
2.10.1
Krzysztof Kozlowski
maintainerPATCH 4/15 ARM: dts: exynos: fix PCI bus dtc warnings
Quoted 7 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Kukjin Kim <[email protected]>Cc Krzysztof Kozlowski <[email protected]>Cc Javier Martinez Canillas <[email protected]>Cc linux-samsung-soc at vger.kernel.org
Quoted 7 lines
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.arch/arm/boot/dts/exynos5440.dtsi | 2 ++ 1 file changed, 2 insertions(+)
Hi,
Unfortunately patch does not apply. There were some changes around PCIe this release so I think the best way would be to rebase on top of linux-next.
Best regards,
Krzysztof
Rob Herring
maintainerPATCH 5/15 ARM: dts: imx: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm/boot/dts/imx6qdl.dtsi | 3 ++- arch/arm/boot/dts/imx6qp.dtsi | 2 +- arch/arm/boot/dts/imx6sx.dtsi | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-)
arch/arm/boot/dts/imx6qdl.dtsi +2 -1
@@ -197,7 +197,7 @@ arm,shared-override; }; - pcie: pcie at 0x01000000 { + pcie: pcie at 1ffc000 { compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; reg = <0x01ffc000 0x04000>, <0x01f00000 0x80000>;
@@ -205,6 +205,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + bus-range = <0 0xff>; ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>;
arch/arm/boot/dts/imx6qp.dtsi +1 -1
@@ -82,7 +82,7 @@ "ldb_di0", "ldb_di1", "prg"; }; - pcie: pcie at 0x01000000 { + pcie: pcie at 1ffc000 { compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; };
arch/arm/boot/dts/imx6sx.dtsi +2 -1
@@ -1281,7 +1281,7 @@ }; }; - pcie: pcie at 0x08000000 { + pcie: pcie at 8ffc000 { compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; reg = <0x08ffc000 0x4000>; /* DBI */ #address-cells = <3>;
@@ -1293,6 +1293,7 @@ 0x81000000 0 0 0x08f80000 0 0x00010000 /* non-prefetchable memory */ 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; + bus-range = <0x00 0xff>; num-lanes = <1>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
Signature · 1 line
2.10.1
PATCH 5/15 ARM: dts: imx: fix PCI bus dtc warnings
Quoted 6 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Shawn Guo <[email protected]>Cc Sascha Hauer <[email protected]>Cc Fabio Estevam <[email protected]>
Applied with a couple of changes below.
Quoted 23 lines
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.arch/arm/boot/dts/imx6qdl.dtsi | 3 ++- arch/arm/boot/dts/imx6qp.dtsi | 2 +- arch/arm/boot/dts/imx6sx.dtsi | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-)arch/arm/boot/dts/imx6qdl.dtsi +1
-1@@ -197,7 +197,7 @@ arm,shared-override; }; - pcie: pcie at 0x01000000 { + pcie: pcie at 1ffc000 { compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; reg = <0x01ffc000 0x04000>, <0x01f00000 0x80000>;
arch/arm/boot/dts/imx6qdl.dtsi line 208
Quoted 4 lines
arch/arm/boot/dts/imx6qdl.dtsi +1
-0@@ -205,6 +205,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + bus-range = <0 0xff>;
For sake of consistency, I changed it to <0x00 0xff> like you did for imx6sx.dtsi.
arch/arm/boot/dts/imx6qp.dtsi line 85
Quoted 13 lines
arch/arm/boot/dts/imx6qdl.dtsi +0
-0ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>;arch/arm/boot/dts/imx6qp.dtsi +1
-1@@ -82,7 +82,7 @@ "ldb_di0", "ldb_di1", "prg"; }; - pcie: pcie at 0x01000000 { + pcie: pcie at 1ffc000 {
We had a patch on IMX tree changing this to use label for referencing the node, and hence this imx6qp.dtsi bit change can be saved.
Shawn
Quoted 27 lines
arch/arm/boot/dts/imx6qp.dtsi +0
-0compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; };arch/arm/boot/dts/imx6sx.dtsi +2
-1@@ -1281,7 +1281,7 @@ }; }; - pcie: pcie at 0x08000000 { + pcie: pcie at 8ffc000 { compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; reg = <0x08ffc000 0x4000>; /* DBI */ #address-cells = <3>;@@ -1293,6 +1293,7 @@ 0x81000000 0 0 0x08f80000 0 0x00010000 /* non-prefetchable memory */ 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; + bus-range = <0x00 0xff>; num-lanes = <1>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,Signature · 1 line
2.10.1
Rob Herring
maintainerPATCH 5/15 ARM: dts: imx: fix PCI bus dtc warnings
Quoted 9 lines · Shawn Guo
Quoted 6 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Shawn Guo <[email protected]>Cc Sascha Hauer <[email protected]>Cc Fabio Estevam <[email protected]>Applied with a couple of changes below.
Thanks. BTW, forget to mention there's still one i.MX warning I did not fix. It's with the "sky2 at 8" PCI device node. The unit address is completely wrong. The comment says bus #8 which doesn't seem right either. The unit address should be "<device num>[,<function]". There should be a reg property which also has the bus number.
Rob
PATCH 5/15 ARM: dts: imx: fix PCI bus dtc warnings
+Tim who is the owner of Gateworks Ventana boards.
Quoted 9 lines · Rob Herring
Quoted 8 lines · Shawn Guo
Quoted 6 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Shawn Guo <[email protected]>Cc Sascha Hauer <[email protected]>Cc Fabio Estevam <[email protected]>
Quoted 7 lines
Quoted 1 line
Applied with a couple of changes below.
Thanks. BTW, forget to mention there's still one i.MX warning I did not fix. It's with the "sky2 at 8" PCI device node. The unit address is completely wrong. The comment says bus #8 which doesn't seem right either. The unit address should be "<device num>[,<function]". There should be a reg property which also has the bus number.
@Tim, these DTC warnings come from Ventana boards. Can you take care of them?
Shawn
Rob Herring
maintainerPATCH 6/15 ARM: dts: r8a779x: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm/boot/dts/r8a7790.dtsi | 16 ++++++---------- arch/arm/boot/dts/r8a7791.dtsi | 16 ++++++---------- arch/arm/boot/dts/r8a7794.dtsi | 16 ++++++---------- 3 files changed, 18 insertions(+), 30 deletions(-)
arch/arm/boot/dts/r8a7790.dtsi +6 -10
@@ -1598,16 +1598,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { + usb at 1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; - usb at 0,2 { + usb at 2,0 { reg = <0x1000 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; };
@@ -1654,16 +1652,14 @@ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; + usb at 1,0 { + reg = <0x20800 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; - usb at 0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; + usb at 2,0 { + reg = <0x21000 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; };
arch/arm/boot/dts/r8a7791.dtsi +6 -10
@@ -1596,16 +1596,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { + usb at 1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; - usb at 0,2 { + usb at 2,0 { reg = <0x1000 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; };
@@ -1631,16 +1629,14 @@ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; + usb at 1,0 { + reg = <0x10800 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; - usb at 0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; + usb at 2,0 { + reg = <0x11000 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; };
arch/arm/boot/dts/r8a7794.dtsi +6 -10
@@ -817,16 +817,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { + usb at 1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; - usb at 0,2 { + usb at 2,0 { reg = <0x1000 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; };
@@ -852,16 +850,14 @@ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; + usb at 1,0 { + reg = <0x10800 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; - usb at 0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; + usb at 2,0 { + reg = <0x11000 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; };
Signature · 1 line
2.10.1
PATCH 6/15 ARM: dts: r8a779x: fix PCI bus dtc warnings
Hi Rob,
Quoted 1 line · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
It's always a good idea to put the warnings in the commit message:
arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 node name is not "pci" or "pcie" arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 missing ranges for PCI bridge (or not a bridge) arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 incorrect #address-cells for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 incorrect #size-cells for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 missing bus-range for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,2 node name is not "pci" or "pcie" arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,2 missing ranges for PCI bridge (or not a bridge) arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,2 incorrect #address-cells for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,2 incorrect #size-cells for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,2 missing bus-range for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,1 node name is not "pci" or "pcie" arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,1 missing ranges for PCI bridge (or not a bridge) arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,1 incorrect #address-cells for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,1 incorrect #size-cells for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,1 missing bus-range for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,2 node name is not "pci" or "pcie" arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,2 missing ranges for PCI bridge (or not a bridge) arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,2 incorrect #address-cells for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,2 incorrect #size-cells for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,2 missing bus-range for PCI bridge arch/arm/boot/dts/r8a7790-lager.dtb: Warning (unit_address_format):
Failed prerequisite 'pci_bridge' arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_reg): Failed prerequisite 'pci_bridge'arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_bus_num):
Failed prerequisite 'pci_bridge'
The above indeed go away with your patch, but I don't know why ;-)
Quoted 18 lines
Signed-off-by Rob Herring <[email protected]>Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc linux-renesas-soc at vger.kernel.org---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.arch/arm/boot/dts/r8a7790.dtsi | 16 ++++++---------- arch/arm/boot/dts/r8a7791.dtsi | 16 ++++++---------- arch/arm/boot/dts/r8a7794.dtsi | 16 ++++++---------- 3 files changed, 18 insertions(+), 30 deletions(-)arch/arm/boot/dts/r8a7790.dtsi +0
-0
arch/arm/boot/dts/r8a7790.dtsi line 1605
Quoted 10 lines
arch/arm/boot/dts/r8a7790.dtsi +1
-2@@ -1598,16 +1598,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { + usb at 1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; };
Both Documentation/devicetree/bindings/pci/pci.txt and ePAPR refer to
http://www.firmware.org/1275/bindings/pci/pci2_1.pdf
http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
which no longer exist.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Rob Herring
maintainerPATCH 6/15 ARM: dts: r8a779x: fix PCI bus dtc warnings
Quoted 6 lines · Geert Uytterhoeven
Hi Rob,
Quoted 1 line · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
It's always a good idea to put the warnings in the commit message:
Well, the warnings are a bit noisy in that they get repeated, can be misleading, change as I fix problems (device nodes are not checked if the bridge node fails), and most importantly I'm lazy having fixed these treewide. Sub-arch maintainers are welcome to make better patches. :)
Quoted 47 lines
arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 node name is not "pci" or "pcie"arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 missing ranges for PCI bridge (or not a bridge)arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 incorrect #address-cells for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 incorrect #size-cells for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 missing bus-range for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,2 node name is not "pci" or "pcie"arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,2 missing ranges for PCI bridge (or not a bridge)arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,2 incorrect #address-cells for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,2 incorrect #size-cells for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,2 missing bus-range for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,1 node name is not "pci" or "pcie"arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,1 missing ranges for PCI bridge (or not a bridge)arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,1 incorrect #address-cells for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,1 incorrect #size-cells for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,1 missing bus-range for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,2 node name is not "pci" or "pcie"arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,2 missing ranges for PCI bridge (or not a bridge)arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,2 incorrect #address-cells for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,2 incorrect #size-cells for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee0d0000/usb at 0,2 missing bus-range for PCI bridgearch/arm/boot/dts/r8a7790-lager.dtb: Warning (unit_address_format):
Failed prerequisite 'pci_bridge'arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_reg): Failed prerequisite 'pci_bridge'arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_bus_num):
Failed prerequisite 'pci_bridge'
Quoted 1 line
The above indeed go away with your patch, but I don't know why ;-)
Most of these are because 'device_type = "pci";' should only be on PCI bridges, not PCI devices.
Quoted 22 lines
Quoted 22 lines
Signed-off-by Rob Herring <[email protected]>Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc linux-renesas-soc at vger.kernel.org---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.arch/arm/boot/dts/r8a7790.dtsi | 16 ++++++---------- arch/arm/boot/dts/r8a7791.dtsi | 16 ++++++---------- arch/arm/boot/dts/r8a7794.dtsi | 16 ++++++---------- 3 files changed, 18 insertions(+), 30 deletions(-)arch/arm/boot/dts/r8a7790.dtsi +0
-0@@ -1598,16 +1598,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Quoted 12 lines
arch/arm/boot/dts/r8a7790.dtsi line 1605
Quoted 7 lines
arch/arm/boot/dts/r8a7790.dtsi +1
-2- usb at 0,1 { + usb at 1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; };Both
Documentation/devicetree/bindings/pci/pci.txtand ePAPR refer to
http://www.firmware.org/1275/bindings/pci/pci2_1.pdf
http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
which no longer exist.
Yeah, they are still out there. Just need to google "PCI supplement 1275". :)
I have the full archive saved off. I need to get them added to devicetree.org.
Rob
PATCH 6/15 ARM: dts: r8a779x: fix PCI bus dtc warnings
Hi Rob,
Quoted 15 lines · Rob Herring
Quoted 4 lines · Geert Uytterhoeven
Quoted 1 line · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
It's always a good idea to put the warnings in the commit message:
Well, the warnings are a bit noisy in that they get repeated, can be misleading, change as I fix problems (device nodes are not checked if the bridge node fails), and most importantly I'm lazy having fixed these treewide. Sub-arch maintainers are welcome to make better patches. :)
Quoted 2 lines
arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_bridge): Node /pci at ee090000/usb at 0,1 node name is not "pci" or "pcie"
[...]
Quoted 4 lines
Quoted 1 line
The above indeed go away with your patch, but I don't know why ;-)
Most of these are because '
device_type= "pci";' should only be on PCI bridges, not PCI devices.
Thanks, retrying...
arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_reg): Node /pci at ee090000/usb at 0,1 PCI unit address format error, expected "1,0" arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_reg): Node /pci at ee090000/usb at 0,2 PCI unit address format error, expected "2,0" arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_reg): Node /pci at ee0d0000/usb at 0,1 PCI unit address format error, expected "1,0" arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_reg): Node /pci at ee0d0000/usb at 0,2 PCI unit address format error, expected "2,0" arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_bus_num):
Node /pci at ee0d0000/usb at 0,1 PCI bus number 0 out of range, expected (2
- 2)arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_bus_num):
Node /pci at ee0d0000/usb at 0,2 PCI bus number 0 out of range, expected (2
- 2)
OK, without 'device_type = "pci"' it makes much more sense...
Quoted 8 lines
Quoted 4 lines
Both
Documentation/devicetree/bindings/pci/pci.txtand ePAPR refer to
http://www.firmware.org/1275/bindings/pci/pci2_1.pdf
http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
which no longer exist.Yeah, they are still out there. Just need to google "PCI supplement 1275". :)
I have the full archive saved off. I need to get them added to devicetree.org.
Having working links in the DT bindings would be great.
BTW, seems like I still have an offline copy of v2.0 of the PCI spec in PostScript format, from my CHRP days[*], when hard disks where smaller than CD-Rs ;-)
[*] I never managed to memorize the PCI DT bindings, though.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 6/15 ARM: dts: r8a779x: fix PCI bus dtc warnings
In reply to Rob HerringQuoted 9 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc linux-renesas-soc at vger.kernel.org---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
I would prefer to take these through my tree to reduce the chances of conflicts emerging later.
Geert, are you happy with this patch and its changelog as-is?
Quoted 141 lines
arch/arm/boot/dts/r8a7790.dtsi | 16 ++++++---------- arch/arm/boot/dts/r8a7791.dtsi | 16 ++++++---------- arch/arm/boot/dts/r8a7794.dtsi | 16 ++++++---------- 3 files changed, 18 insertions(+), 30 deletions(-)arch/arm/boot/dts/r8a7790.dtsi +6
-10@@ -1598,16 +1598,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { + usb at 1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; - usb at 0,2 { + usb at 2,0 { reg = <0x1000 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; };@@ -1654,16 +1652,14 @@ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; + usb at 1,0 { + reg = <0x20800 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; - usb at 0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; + usb at 2,0 { + reg = <0x21000 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; };arch/arm/boot/dts/r8a7791.dtsi +6
-10@@ -1596,16 +1596,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { + usb at 1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; - usb at 0,2 { + usb at 2,0 { reg = <0x1000 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; };@@ -1631,16 +1629,14 @@ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; + usb at 1,0 { + reg = <0x10800 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; - usb at 0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; + usb at 2,0 { + reg = <0x11000 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; };arch/arm/boot/dts/r8a7794.dtsi +6
-10@@ -817,16 +817,14 @@ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { + usb at 1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; }; - usb at 0,2 { + usb at 2,0 { reg = <0x1000 0 0 0 0>; - device_type = "pci"; phys = <&usb0 0>; phy-names = "usb"; };@@ -852,16 +850,14 @@ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - usb at 0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; + usb at 1,0 { + reg = <0x10800 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; }; - usb at 0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; + usb at 2,0 { + reg = <0x11000 0 0 0 0>; phys = <&usb2 0>; phy-names = "usb"; };Signature · 1 line
2.10.1
PATCH 6/15 ARM: dts: r8a779x: fix PCI bus dtc warnings
Hi Simon,
Quoted 11 lines · Simon Horman
Quoted 9 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Simon Horman <[email protected]>Cc Magnus Damm <[email protected]>Cc linux-renesas-soc at vger.kernel.org---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
Quoted 4 lines
I would prefer to take these through my tree to reduce the chances of conflicts emerging later.
Geert, are you happy with this patch and its changelog as-is?
I'd use something like:
---8<----------
The bogus 'device_type = "pci"' confuses dtc, causing lots of totally unrelated warnings. After fixing that, real warnings like
arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_reg):
Node /pci at ee090000/usb@0,1 PCI unit address format error, expected "1,0"
are left. Correct the unit-adresses and reg properties of the subnodes to fix these.
---------->8---
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Rob Herring
maintainerPATCH 7/15 ARM: dts: spear13xx: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm/boot/dts/spear1310.dtsi | 3 +++ arch/arm/boot/dts/spear1340.dtsi | 1 + 2 files changed, 4 insertions(+)
arch/arm/boot/dts/spear1310.dtsi +3 -0
@@ -98,6 +98,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; status = "disabled"; };
@@ -116,6 +117,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; status = "disabled"; };
@@ -134,6 +136,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; status = "disabled"; };
arch/arm/boot/dts/spear1340.dtsi +1 -0
@@ -63,6 +63,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + bus-range = <0x00 0xff>; status = "disabled"; };
Signature · 1 line
2.10.1
PATCH 7/15 ARM: dts: spear13xx: fix PCI bus dtc warnings
Quoted 5 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Viresh Kumar <[email protected]>Cc Shiraz Hashim <[email protected]>
Quoted 7 lines
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.arch/arm/boot/dts/spear1310.dtsi | 3 +++ arch/arm/boot/dts/spear1340.dtsi | 1 + 2 files changed, 4 insertions(+)
Signature · 1 line
viresh
Rob Herring
maintainerPATCH 8/15 ARM: dts: tegra: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124.dtsi | 4 +++- arch/arm/boot/dts/tegra20-harmony.dts | 2 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-tec.dts | 2 +- arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- arch/arm/boot/dts/tegra20.dtsi | 4 +++- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- arch/arm/boot/dts/tegra30.dtsi | 5 ++++- 14 files changed, 21 insertions(+), 14 deletions(-)
arch/arm/boot/dts/tegra124-apalis-eval.dts +1 -1
@@ -63,7 +63,7 @@ stdout-path = "serial0:115200n8"; }; - pcie-controller at 01003000 { + pcie at 1003000 { pci at 1,0 { status = "okay"; };
arch/arm/boot/dts/tegra124-apalis.dtsi +1 -1
@@ -54,7 +54,7 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; - pcie-controller at 01003000 { + pcie at 1003000 { status = "okay"; avddio-pex-supply = <&vdd_1v05>;
arch/arm/boot/dts/tegra124-jetson-tk1.dts +1 -1
@@ -27,7 +27,7 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; - pcie-controller at 01003000 { + pcie at 1003000 { status = "okay"; avddio-pex-supply = <&vdd_1v05_run>;
arch/arm/boot/dts/tegra124.dtsi +3 -1
@@ -14,7 +14,7 @@ #address-cells = <2>; #size-cells = <2>; - pcie-controller at 01003000 { + pcie at 1003000 { compatible = "nvidia,tegra124-pcie"; device_type = "pci"; reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@@ -54,6 +54,7 @@ device_type = "pci"; assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
@@ -67,6 +68,7 @@ device_type = "pci"; assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
arch/arm/boot/dts/tegra20-harmony.dts +1 -1
@@ -566,7 +566,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller at 80003000 { + pcie at 80003000 { status = "okay"; avdd-pex-supply = <&pci_vdd_reg>;
arch/arm/boot/dts/tegra20-tamonten.dtsi +1 -1
@@ -478,7 +478,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller at 80003000 { + pcie at 80003000 { avdd-pex-supply = <&pci_vdd_reg>; vdd-pex-supply = <&pci_vdd_reg>; avdd-pex-pll-supply = <&pci_vdd_reg>;
arch/arm/boot/dts/tegra20-tec.dts +1 -1
@@ -32,7 +32,7 @@ }; }; - pcie-controller at 80003000 { + pcie at 80003000 { status = "okay"; pci at 1,0 {
arch/arm/boot/dts/tegra20-trimslice.dts +1 -1
@@ -321,7 +321,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller at 80003000 { + pcie at 80003000 { status = "okay"; avdd-pex-supply = <&pci_vdd_reg>;
arch/arm/boot/dts/tegra20.dtsi +3 -1
@@ -586,7 +586,7 @@ reset-names = "fuse"; }; - pcie-controller at 80003000 { + pcie at 80003000 { compatible = "nvidia,tegra20-pcie"; device_type = "pci"; reg = <0x80003000 0x00000800 /* PADS registers */
@@ -625,6 +625,7 @@ device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
@@ -638,6 +639,7 @@ device_type = "pci"; assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
arch/arm/boot/dts/tegra30-apalis-eval.dts +1 -1
@@ -21,7 +21,7 @@ stdout-path = "serial0:115200n8"; }; - pcie-controller at 00003000 { + pcie at 3000 { status = "okay"; pci at 1,0 {
arch/arm/boot/dts/tegra30-apalis.dtsi +1 -1
@@ -9,7 +9,7 @@ model = "Toradex Apalis T30"; compatible = "toradex,apalis_t30", "nvidia,tegra30"; - pcie-controller at 00003000 { + pcie at 3000 { avdd-pexa-supply = <&vdd2_reg>; vdd-pexa-supply = <&vdd2_reg>; avdd-pexb-supply = <&vdd2_reg>;
arch/arm/boot/dts/tegra30-beaver.dts +1 -1
@@ -20,7 +20,7 @@ reg = <0x80000000 0x7ff00000>; }; - pcie-controller at 00003000 { + pcie at 3000 { status = "okay"; avdd-pexa-supply = <&ldo1_reg>;
arch/arm/boot/dts/tegra30-cardhu.dtsi +1 -1
@@ -43,7 +43,7 @@ reg = <0x80000000 0x40000000>; }; - pcie-controller at 00003000 { + pcie at 3000 { status = "okay"; /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
arch/arm/boot/dts/tegra30.dtsi +4 -1
@@ -10,7 +10,7 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&lic>; - pcie-controller at 00003000 { + pcie at 3000 { compatible = "nvidia,tegra30-pcie"; device_type = "pci"; reg = <0x00003000 0x00000800 /* PADS registers */
@@ -51,6 +51,7 @@ device_type = "pci"; assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
@@ -64,6 +65,7 @@ device_type = "pci"; assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
@@ -77,6 +79,7 @@ device_type = "pci"; assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; reg = <0x001800 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
Signature · 1 line
2.10.1
PATCH 8/15 ARM: dts: tegra: fix PCI bus dtc warnings
Quoted 11 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Stephen Warren <[email protected]>Cc Thierry Reding <[email protected]>Cc Alexandre Courbot <[email protected]>Cc linux-tegra at vger.kernel.org---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
Quoted 15 lines
arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124.dtsi | 4 +++- arch/arm/boot/dts/tegra20-harmony.dts | 2 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-tec.dts | 2 +- arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- arch/arm/boot/dts/tegra20.dtsi | 4 +++- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- arch/arm/boot/dts/tegra30.dtsi | 5 ++++- 14 files changed, 21 insertions(+), 14 deletions(-)
Doesn't look like ARM SoC took the lot, so I've applied this to the Tegra tree for v4.13.
Thanks,
Thierry
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Rob Herring
maintainerPATCH 9/15 ARM: dts: versatile: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm/boot/dts/versatile-pb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/versatile-pb.dts +1 -1
@@ -39,7 +39,7 @@ clock-names = "apb_pclk"; }; - pci-controller at 10001000 { + pci at 10001000 { compatible = "arm,versatile-pci"; device_type = "pci"; reg = <0x10001000 0x1000
Signature · 1 line
2.10.1
Rob Herring
maintainerPATCH 10/15 ARM: dts: bcm: fix msi-controller name and unit address
In reply to Rob HerringThe unit address for the msi controller is not valid as there is no reg property, so remove it. Also, msi-controller is the preferred node name.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm/boot/dts/bcm-cygnus.dtsi | 4 ++-- arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-)
arch/arm/boot/dts/bcm-cygnus.dtsi +2 -2
@@ -205,7 +205,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi at 18012000 { + msi0: msi-controller { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>;
@@ -240,7 +240,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi at 18013000 { + msi1: msi-controller { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>;
arch/arm/boot/dts/bcm-nsp.dtsi +3 -3
@@ -450,7 +450,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi at 18012000 { + msi0: msi-controller { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>;
@@ -486,7 +486,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi at 18013000 { + msi1: msi-controller { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>;
@@ -522,7 +522,7 @@ status = "disabled"; msi-parent = <&msi2>; - msi2: msi at 18014000 { + msi2: msi-controller { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>;
Signature · 1 line
2.10.1
PATCH 10/15 ARM: dts: bcm: fix msi-controller name and unit address
Hi Rob,
Quoted 61 lines · Rob Herring
The unit address for the msi controller is not valid as there is no reg property, so remove it. Also, msi-controller is the preferred node name.
Signed-off-by Rob Herring <[email protected]>Cc Ray Jui <[email protected]>Cc Scott Branden <[email protected]>Cc Jon Mason <[email protected]>Cc bcm-kernel-feedback-list at broadcom.com---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.arch/arm/boot/dts/bcm-cygnus.dtsi | 4 ++-- arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-)arch/arm/boot/dts/bcm-cygnus.dtsi +2
-2@@ -205,7 +205,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi at 18012000 { + msi0: msi-controller { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>;@@ -240,7 +240,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi at 18013000 { + msi1: msi-controller { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>;arch/arm/boot/dts/bcm-nsp.dtsi +2
-2@@ -450,7 +450,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi at 18012000 { + msi0: msi-controller { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>;@@ -486,7 +486,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi at 18013000 { + msi1: msi-controller { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>;
arch/arm/boot/dts/bcm-nsp.dtsi line 528
Quoted 8 lines
arch/arm/boot/dts/bcm-nsp.dtsi +1
-1@@ -522,7 +522,7 @@ status = "disabled"; msi-parent = <&msi2>; - msi2: msi at 18014000 { + msi2: msi-controller { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>;
Looks good and thanks!
Florian Fainelli
AppliedPATCH 10/15 ARM: dts: bcm: fix msi-controller name and unit address
In reply to Rob HerringQuoted 11 lines · Rob Herring
The unit address for the msi controller is not valid as there is no reg property, so remove it. Also, msi-controller is the preferred node name.
Signed-off-by Rob Herring <[email protected]>Cc Ray Jui <[email protected]>Cc Scott Branden <[email protected]>Cc Jon Mason <[email protected]>Cc bcm-kernel-feedback-list at broadcom.com---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
Applied, thanks Rob.
Signature · 1 line
Florian
Rob Herring
maintainerPATCH 11/15 arm64: dts: nvidia: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 +++- 3 files changed, 7 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/nvidia/tegra132.dtsi +3 -1
@@ -12,7 +12,7 @@ #address-cells = <2>; #size-cells = <2>; - pcie-controller at 01003000 { + pcie at 1003000 { compatible = "nvidia,tegra124-pcie"; device_type = "pci"; reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@@ -55,6 +55,7 @@ device_type = "pci"; assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
@@ -68,6 +69,7 @@ device_type = "pci"; assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +1 -1
@@ -7,7 +7,7 @@ model = "NVIDIA Jetson TX1 Developer Kit"; compatible = "nvidia,p2371-2180", "nvidia,tegra210"; - pcie-controller at 01003000 { + pcie at 1003000 { status = "okay"; avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
arch/arm64/boot/dts/nvidia/tegra210.dtsi +3 -1
@@ -11,7 +11,7 @@ #address-cells = <2>; #size-cells = <2>; - pcie-controller at 01003000 { + pcie at 1003000 { compatible = "nvidia,tegra210-pcie"; device_type = "pci"; reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@@ -51,6 +51,7 @@ device_type = "pci"; assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; reg = <0x000800 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
@@ -64,6 +65,7 @@ device_type = "pci"; assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; reg = <0x001000 0 0 0 0>; + bus-range = <0x00 0xff>; status = "disabled"; #address-cells = <3>;
Signature · 1 line
2.10.1
Thierry Reding
AppliedPATCH 11/15 arm64: dts: nvidia: fix PCI bus dtc warnings
Quoted 7 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Stephen Warren <[email protected]>Cc Thierry Reding <[email protected]>Cc Alexandre Courbot <[email protected]>Cc linux-tegra at vger.kernel.org
Quoted 8 lines
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 +++- 3 files changed, 7 insertions(+), 3 deletions(-)
Applied, thanks.
Thierry
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Rob Herring
maintainerPATCH 12/15 arm64: dts: apm: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 2 ++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 5 +++++ 2 files changed, 7 insertions(+)
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +2 -0
@@ -626,6 +626,7 @@ 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
@@ -651,6 +652,7 @@ 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
arch/arm64/boot/dts/apm/apm-storm.dtsi +5 -0
@@ -626,6 +626,7 @@ 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
@@ -651,6 +652,7 @@ 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
@@ -676,6 +678,7 @@ 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
@@ -701,6 +704,7 @@ 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
@@ -726,6 +730,7 @@ 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
Signature · 1 line
2.10.1
Rob Herring
maintainerPATCH 13/15 arm64: dts: juno: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/arm/juno-base.dtsi +1 -1
@@ -428,7 +428,7 @@ }; }; - pcie_ctlr: pcie-controller at 40000000 { + pcie_ctlr: pcie at 40000000 { compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; device_type = "pci"; reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
Signature · 1 line
2.10.1
Liviu Dudau
maintainerPATCH 13/15 arm64: dts: juno: fix PCI bus dtc warnings
Hi Rob,
Quoted 1 line · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Was not aware of the warnings and the commit message doesn't quote them, but the change looks trivial. So:
Thanks for fixing this!
Liviu
Quoted 26 lines
Signed-off-by Rob Herring <[email protected]>Cc Liviu Dudau <[email protected]>Cc Sudeep Holla <[email protected]>Cc Lorenzo Pieralisi <[email protected]>---
arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm64/boot/dts/arm/juno-base.dtsi +1
-1@@ -428,7 +428,7 @@ }; }; - pcie_ctlr: pcie-controller at 40000000 { + pcie_ctlr: pcie at 40000000 { compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; device_type = "pci"; reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */Signature · 1 line
2.10.1
Signature · 8 lines
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
?\_(?)_/?Rob Herring
maintainerPATCH 14/15 arm64: dts: broadcom: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm64/boot/dts/broadcom/vulcan.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/broadcom/vulcan.dtsi +1 -0
@@ -117,6 +117,7 @@ ranges = <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = /* addr pin ic icaddr icintr */
Signature · 1 line
2.10.1
PATCH 14/15 arm64: dts: broadcom: fix PCI bus dtc warnings
Hi Rob,
Quoted 17 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc "Jayachandran C." <[email protected]>Cc bcm-kernel-feedback-list at broadcom.com---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.arch/arm64/boot/dts/broadcom/vulcan.dtsi | 1 + 1 file changed, 1 insertion(+)arch/arm64/boot/dts/broadcom/vulcan.dtsi +0
-0
arch/arm64/boot/dts/broadcom/vulcan.dtsi line 123
Quoted 7 lines
arch/arm64/boot/dts/broadcom/vulcan.dtsi +1
-0@@ -117,6 +117,7 @@ ranges = <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = /* addr pin ic icaddr icintr */
There is a patch posted to move this from broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi
https://www.spinics.net/lists/arm-kernel/msg568464.html
That might go in thru the arm-soc tree, and there might be a conflict here.
JC.
Rob Herring
maintainerPATCH 15/15 arm64: dts: xilinx: fix PCI bus dtc warnings
In reply to Rob Herringdtc recently added PCI bus checks. Fix these warnings.
---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +1 -0
@@ -221,6 +221,7 @@ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
Signature · 1 line
2.10.1
Michal Simek
AppliedPATCH 15/15 arm64: dts: xilinx: fix PCI bus dtc warnings
Quoted 18 lines · Rob Herring
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by Rob Herring <[email protected]>Cc Michal Simek <[email protected]>Cc "S?ren Brinkmann" <[email protected]>---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+)arch/arm64/boot/dts/xilinx/zynqmp.dtsi +0
-0
arch/arm64/boot/dts/xilinx/zynqmp.dtsi line 227
Quoted 7 lines
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +1
-0@@ -221,6 +221,7 @@ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
Applied to zynqmp/dt branch.
Thanks,
Michal
PATCH 1/15 ARM: dts: alpine: fix PCIe node name
In reply to Rob HerringHi Rob,
Quoted 3 lines · Rob Herring
PCIe bridges should have a node name of 'pcie'.
Signed-off-by Rob Herring <[email protected]>
This can go through arm-soc directly. If not I'll take it. Thanks!
Antoine
Quoted 25 lines
Cc Tsahee Zidenberg <[email protected]>Cc Antoine Tenart <[email protected]>---
Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot.arch/arm/boot/dts/alpine.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm/boot/dts/alpine.dtsi +1
-1@@ -139,7 +139,7 @@ }; /* Internal PCIe Controller */ - pcie-internal at 0xfbc00000 { + pcie at fbc00000 { compatible = "pci-host-ecam-generic"; device_type = "pci"; #size-cells = <2>;Signature · 1 line
2.10.1
Signature · 10 lines
Antoine T?nart, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170322/01ad26da/attachment.sig>
PATCH 1/15 ARM: dts: alpine: fix PCIe node name
Quoted 11 lines · Antoine Tenart
Hi Rob,
Quoted 3 lines · Rob Herring
PCIe bridges should have a node name of 'pcie'.
Signed-off-by Rob Herring <[email protected]>Acked-by Antoine Tenart <[email protected]>This can go through arm-soc directly. If not I'll take it. Thanks!
I have a mild preference for this kind of patch to get picked up by platform maintainers.
Rob, once replies stop coming in, please send a pull request for anything that did not get picked up by anyone else.
Arnd
PATCH 1/15 ARM: dts: alpine: fix PCIe node name
Hi Arnd,
Quoted 7 lines · Arnd Bergmann
Quoted 5 lines · Antoine Tenart
Quoted 3 lines · Rob Herring
PCIe bridges should have a node name of 'pcie'.
Signed-off-by Rob Herring <[email protected]>
Quoted 7 lines
Quoted 4 lines
Acked-by Antoine Tenart <[email protected]>This can go through arm-soc directly. If not I'll take it. Thanks!
I have a mild preference for this kind of patch to get picked up by platform maintainers.
Sure. Applied to alpine/dt.
Thanks!
Antoine
Signature · 10 lines
Antoine T?nart, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170324/0e5f665a/attachment.sig>