pinctrl: sh-pfc: r8a7791: grand I2C rename
Subsystems (2)
PATCH 1/1 pinctrl: sh-pfc: r8a7791: grand I2C rename
The R8A7791 PFC driver was apparently based on the preliminary revisions of the user's manual, which called all the I2C signals {SCL|SDA}<n> and MOD_SEL register fields SEL_IIC<n> without making a difference between two types of the I2C controllers used. The recent manual calls the signals {I2C|IIC}<n>_{SCL|SDA> and the MOD_SEL fields SEL_{I2C|IIC}<n> finally making this difference. Follow the suit, also renaming the I2C{7|8} pin arrays and groups/functions (luckily, they haven't been used so far).
Signed-off-by Sergei Shtylyov <[email protected]>
---
This patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus 2 R8A7791 fixes posted yesterday.
drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 521 +++++++++++++++++------------------ 1 file changed, 264 insertions(+), 257 deletions(-)
drivers/pinctrl/sh-pfc/pfc-r8a7791.c +264 -257
@@ -119,22 +119,22 @@ enum {/* IPSR0 */ FN_D0 ,FN_D1 ,FN_D2 ,FN_D3 ,FN_D4 ,FN_D5 ,FN_D6 ,FN_D7 ,FN_D8 ,FN_D9 ,FN_D10 ,FN_D11 ,FN_D12 ,FN_D13 ,FN_D14 ,FN_D15 , -FN_A0 ,FN_ATAWR0_N_C ,FN_MSIOF0_SCK_B ,FN_SCL0_C ,FN_PWM2_B , +FN_A0 ,FN_ATAWR0_N_C ,FN_MSIOF0_SCK_B ,FN_I2C0_SCL_C ,FN_PWM2_B ,FN_A1 ,FN_MSIOF0_SYNC_B ,FN_A2 ,FN_MSIOF0_SS1_B ,FN_A3 ,FN_MSIOF0_SS2_B ,FN_A4 ,FN_MSIOF0_TXD_B ,FN_A5 ,FN_MSIOF0_RXD_B ,FN_A6 ,FN_MSIOF1_SCK ,/* IPSR1 */ -FN_A7 ,FN_MSIOF1_SYNC ,FN_A8 ,FN_MSIOF1_SS1 ,FN_SCL0 , -FN_A9 ,FN_MSIOF1_SS2 ,FN_SDA0 , +FN_A7 ,FN_MSIOF1_SYNC ,FN_A8 ,FN_MSIOF1_SS1 ,FN_I2C0_SCL , +FN_A9 ,FN_MSIOF1_SS2 ,FN_I2C0_SDA ,FN_A10 ,FN_MSIOF1_TXD ,FN_MSIOF1_TXD_D , -FN_A11 ,FN_MSIOF1_RXD ,FN_SCL3_D ,FN_MSIOF1_RXD_D , -FN_A12 ,FN_FMCLK ,FN_SDA3_D ,FN_MSIOF1_SCK_D , +FN_A11 ,FN_MSIOF1_RXD ,FN_I2C3_SCL_D ,FN_MSIOF1_RXD_D , +FN_A12 ,FN_FMCLK ,FN_I2C3_SDA_D ,FN_MSIOF1_SCK_D ,FN_A13 ,FN_ATAG0_N_C ,FN_BPFCLK ,FN_MSIOF1_SS1_D ,FN_A14 ,FN_ATADIR0_N_C ,FN_FMIN ,FN_FMIN_C ,FN_MSIOF1_SYNC_D ,FN_A15 ,FN_BPFCLK_C ,FN_A16 ,FN_DREQ2_B ,FN_FMCLK_C ,FN_SCIFA1_SCK_B , -FN_A17 ,FN_DACK2_B ,FN_SDA0_C , +FN_A17 ,FN_DACK2_B ,FN_I2C0_SDA_C ,FN_A18 ,FN_DREQ1 ,FN_SCIFA1_RXD_C ,FN_SCIFB1_RXD_C , /* IPSR2 */
@@ -145,8 +145,8 @@ enum {FN_A23 ,FN_IO2 ,FN_BPFCLK_B ,FN_RX0 ,FN_SCIFA0_RXD ,FN_A24 ,FN_DREQ2 ,FN_IO3 ,FN_TX1 ,FN_SCIFA1_TXD ,FN_A25 ,FN_DACK2 ,FN_SSL ,FN_DREQ1_C ,FN_RX1 ,FN_SCIFA1_RXD , -FN_CS0_N ,FN_ATAG0_N_B ,FN_SCL1 , -FN_CS1_N_A26 ,FN_ATADIR0_N_B ,FN_SDA1 , +FN_CS0_N ,FN_ATAG0_N_B ,FN_I2C1_SCL , +FN_CS1_N_A26 ,FN_ATADIR0_N_B ,FN_I2C1_SDA ,FN_EX_CS1_N ,FN_MSIOF2_SCK ,FN_EX_CS2_N ,FN_ATAWR0_N ,FN_MSIOF2_SYNC , FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
@@ -169,12 +169,13 @@ enum {FN_SSI_WS0129 ,FN_HTX0_C ,FN_HTX2_C ,FN_SCIFB0_TXD_C ,FN_SCIFB2_TXD_C ,/* IPSR4 */ -FN_SSI_SDATA0 ,FN_SCL0_B ,FN_SCL7_B ,FN_MSIOF2_SCK_C , -FN_SSI_SCK1 ,FN_SDA0_B ,FN_SDA7_B ,FN_MSIOF2_SYNC_C ,FN_GLO_I0_D , -FN_SSI_WS1 ,FN_SCL1_B ,FN_SCL8_B ,FN_MSIOF2_TXD_C ,FN_GLO_I1_D , -FN_SSI_SDATA1 ,FN_SDA1_B ,FN_SDA8_B ,FN_MSIOF2_RXD_C , -FN_SSI_SCK2 ,FN_SCL2 ,FN_GPS_CLK_B ,FN_GLO_Q0_D ,FN_HSCK1_E , -FN_SSI_WS2 ,FN_SDA2 ,FN_GPS_SIGN_B ,FN_RX2_E , +FN_SSI_SDATA0 ,FN_I2C0_SCL_B ,FN_IIC0_SCL_B ,FN_MSIOF2_SCK_C , +FN_SSI_SCK1 ,FN_I2C0_SDA_B ,FN_IIC0_SDA_B ,FN_MSIOF2_SYNC_C , +FN_GLO_I0_D , +FN_SSI_WS1 ,FN_I2C1_SCL_B ,FN_IIC1_SCL_B ,FN_MSIOF2_TXD_C ,FN_GLO_I1_D , +FN_SSI_SDATA1 ,FN_I2C1_SDA_B ,FN_IIC1_SDA_B ,FN_MSIOF2_RXD_C , +FN_SSI_SCK2 ,FN_I2C2_SCL ,FN_GPS_CLK_B ,FN_GLO_Q0_D ,FN_HSCK1_E , +FN_SSI_WS2 ,FN_I2C2_SDA ,FN_GPS_SIGN_B ,FN_RX2_E ,FN_GLO_Q1_D ,FN_HCTS1_N_E ,FN_SSI_SDATA2 ,FN_GPS_MAG_B ,FN_TX2_E ,FN_HRTS1_N_E , FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
@@ -210,10 +211,10 @@ enum {FN_IRQ0 ,FN_SCIFB1_RXD_D ,FN_INTC_IRQ0_N ,FN_IRQ1 ,FN_SCIFB1_SCK_C ,FN_INTC_IRQ1_N ,FN_IRQ2 ,FN_SCIFB1_TXD_D ,FN_INTC_IRQ2_N , -FN_IRQ3 ,FN_SCL4_C ,FN_MSIOF2_TXD_E ,FN_INTC_IRQ3_N , -FN_IRQ4 ,FN_HRX1_C ,FN_SDA4_C ,FN_MSIOF2_RXD_E ,FN_INTC_IRQ4_N , -FN_IRQ5 ,FN_HTX1_C ,FN_SCL1_E ,FN_MSIOF2_SCK_E , -FN_IRQ6 ,FN_HSCK1_C ,FN_MSIOF1_SS2_B ,FN_SDA1_E ,FN_MSIOF2_SYNC_E , +FN_IRQ3 ,FN_I2C4_SCL_C ,FN_MSIOF2_TXD_E ,FN_INTC_IRQ3_N , +FN_IRQ4 ,FN_HRX1_C ,FN_I2C4_SDA_C ,FN_MSIOF2_RXD_E ,FN_INTC_IRQ4_N , +FN_IRQ5 ,FN_HTX1_C ,FN_I2C1_SCL_E ,FN_MSIOF2_SCK_E , +FN_IRQ6 ,FN_HSCK1_C ,FN_MSIOF1_SS2_B ,FN_I2C1_SDA_E ,FN_MSIOF2_SYNC_E ,FN_IRQ7 ,FN_HCTS1_N_C ,FN_MSIOF1_TXD_B ,FN_GPS_CLK_C ,FN_GPS_CLK_D , FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
@@ -257,16 +258,16 @@ enum {FN_DU1_DB5 ,FN_LCDOUT21 ,FN_TX3 ,FN_SCIFA3_TXD ,FN_CAN1_TX ,/* IPSR9 */ -FN_DU1_DB6 ,FN_LCDOUT22 ,FN_SCL3_C ,FN_RX3 ,FN_SCIFA3_RXD , -FN_DU1_DB7 ,FN_LCDOUT23 ,FN_SDA3_C ,FN_SCIF3_SCK ,FN_SCIFA3_SCK , +FN_DU1_DB6 ,FN_LCDOUT22 ,FN_I2C3_SCL_C ,FN_RX3 ,FN_SCIFA3_RXD , +FN_DU1_DB7 ,FN_LCDOUT23 ,FN_I2C3_SDA_C ,FN_SCIF3_SCK ,FN_SCIFA3_SCK ,FN_DU1_DOTCLKIN ,FN_QSTVA_QVS ,FN_DU1_DOTCLKOUT0 ,FN_QCLK ,FN_DU1_DOTCLKOUT1 ,FN_QSTVB_QVE ,FN_CAN0_TX , -FN_TX3_B ,FN_SCL2_B ,FN_PWM4 , +FN_TX3_B ,FN_I2C2_SCL_B ,FN_PWM4 ,FN_DU1_EXHSYNC_DU1_HSYNC ,FN_QSTH_QHS ,FN_DU1_EXVSYNC_DU1_VSYNC ,FN_QSTB_QHE ,FN_DU1_EXODDF_DU1_ODDF_DISP_CDE ,FN_QCPV_QDE , -FN_CAN0_RX ,FN_RX3_B ,FN_SDA2_B , +FN_CAN0_RX ,FN_RX3_B ,FN_I2C2_SDA_B ,FN_DU1_DISP ,FN_QPOLA ,FN_DU1_CDE ,FN_QPOLB ,FN_PWM4_B , FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
@@ -274,15 +275,15 @@ enum {FN_VI0_HSYNC_N ,FN_TX5 ,FN_SCIFA5_TXD ,FN_TS_SDEN0_D ,FN_VI0_VSYNC_N ,FN_RX5 ,FN_SCIFA5_RXD ,FN_TS_SPSYNC0_D ,FN_VI0_DATA3_VI0_B3 ,FN_SCIF3_SCK_B ,FN_SCIFA3_SCK_B , -FN_VI0_G0 ,FN_SCL8 ,FN_STP_IVCXO27_0_C ,FN_SCL4 , +FN_VI0_G0 ,FN_IIC1_SCL ,FN_STP_IVCXO27_0_C ,FN_I2C4_SCL ,FN_HCTS2_N ,FN_SCIFB2_CTS_N ,FN_ATAWR1_N ,/* IPSR10 */ -FN_VI0_G1 ,FN_SDA8 ,FN_STP_ISCLK_0_C ,FN_SDA4 , +FN_VI0_G1 ,FN_IIC1_SDA ,FN_STP_ISCLK_0_C ,FN_I2C4_SDA ,FN_HRTS2_N ,FN_SCIFB2_RTS_N ,FN_ATADIR1_N , -FN_VI0_G2 ,FN_VI2_HSYNC_N ,FN_STP_ISD_0_C ,FN_SCL3_B , +FN_VI0_G2 ,FN_VI2_HSYNC_N ,FN_STP_ISD_0_C ,FN_I2C3_SCL_B ,FN_HSCK2 ,FN_SCIFB2_SCK ,FN_ATARD1_N , -FN_VI0_G3 ,FN_VI2_VSYNC_N ,FN_STP_ISEN_0_C ,FN_SDA3_B , +FN_VI0_G3 ,FN_VI2_VSYNC_N ,FN_STP_ISEN_0_C ,FN_I2C3_SDA_B ,FN_HRX2 ,FN_SCIFB2_RXD ,FN_ATACS01_N ,FN_VI0_G4 ,FN_VI2_CLKENB ,FN_STP_ISSYNC_0_C , FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
@@ -296,13 +297,13 @@ enum {FN_TS_SCK0_C ,FN_ATAG1_N ,FN_VI0_R2 ,FN_VI2_DATA3 ,FN_GLO_Q0_B ,FN_TS_SDEN0_C ,FN_VI0_R3 ,FN_VI2_DATA4 ,FN_GLO_Q1_B ,FN_TS_SPSYNC0_C , -FN_VI0_R4 ,FN_VI2_DATA5 ,FN_GLO_SCLK_B ,FN_TX0_C ,FN_SCL1_D , +FN_VI0_R4 ,FN_VI2_DATA5 ,FN_GLO_SCLK_B ,FN_TX0_C ,FN_I2C1_SCL_D ,/* IPSR11 */ -FN_VI0_R5 ,FN_VI2_DATA6 ,FN_GLO_SDATA_B ,FN_RX0_C ,FN_SDA1_D , -FN_VI0_R6 ,FN_VI2_DATA7 ,FN_GLO_SS_B ,FN_TX1_C ,FN_SCL4_B , +FN_VI0_R5 ,FN_VI2_DATA6 ,FN_GLO_SDATA_B ,FN_RX0_C ,FN_I2C1_SDA_D , +FN_VI0_R6 ,FN_VI2_DATA7 ,FN_GLO_SS_B ,FN_TX1_C ,FN_I2C4_SCL_B ,FN_VI0_R7 ,FN_GLO_RFON_B ,FN_RX1_C ,FN_CAN0_RX_E , -FN_SDA4_B ,FN_HRX1_D ,FN_SCIFB0_RXD_D , +FN_I2C4_SDA_B ,FN_HRX1_D ,FN_SCIFB0_RXD_D ,FN_VI1_HSYNC_N ,FN_AVB_RXD0 ,FN_TS_SDATA0_B ,FN_TX4_B ,FN_SCIFA4_TXD_B ,FN_VI1_VSYNC_N ,FN_AVB_RXD1 ,FN_TS_SCK0_B ,FN_RX4_B ,FN_SCIFA4_RXD_B , FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
@@ -312,15 +313,15 @@ enum {FN_VI1_DATA3 ,FN_AVB_RX_ER ,FN_VI1_DATA4 ,FN_AVB_MDIO ,FN_VI1_DATA5 ,FN_AVB_RX_DV ,FN_VI1_DATA6 ,FN_AVB_MAGIC ,FN_VI1_DATA7 ,FN_AVB_MDC , -FN_ETH_MDIO ,FN_AVB_RX_CLK ,FN_SCL2_C , -FN_ETH_CRS_DV ,FN_AVB_LINK ,FN_SDA2_C , +FN_ETH_MDIO ,FN_AVB_RX_CLK ,FN_I2C2_SCL_C , +FN_ETH_CRS_DV ,FN_AVB_LINK ,FN_I2C2_SDA_C ,/* IPSR12 */ -FN_ETH_RX_ER ,FN_AVB_CRS ,FN_SCL3 ,FN_SCL7 , -FN_ETH_RXD0 ,FN_AVB_PHY_INT ,FN_SDA3 ,FN_SDA7 , +FN_ETH_RX_ER ,FN_AVB_CRS ,FN_I2C3_SCL ,FN_IIC0_SCL , +FN_ETH_RXD0 ,FN_AVB_PHY_INT ,FN_I2C3_SDA ,FN_IIC0_SDA ,FN_ETH_RXD1 ,FN_AVB_GTXREFCLK ,FN_CAN0_TX_C , -FN_SCL2_D ,FN_MSIOF1_RXD_E , -FN_ETH_LINK ,FN_AVB_TXD0 ,FN_CAN0_RX_C ,FN_SDA2_D ,FN_MSIOF1_SCK_E , +FN_I2C2_SCL_D ,FN_MSIOF1_RXD_E , +FN_ETH_LINK ,FN_AVB_TXD0 ,FN_CAN0_RX_C ,FN_I2C2_SDA_D ,FN_MSIOF1_SCK_E ,FN_ETH_REFCLK ,FN_AVB_TXD1 ,FN_SCIFA3_RXD_B ,FN_CAN1_RX_C ,FN_MSIOF1_SYNC_E , FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
@@ -351,23 +352,23 @@ enum {FN_SD1_CMD ,FN_REMOCON_B ,FN_SD1_DATA0 ,FN_SPEEDIN_B ,FN_SD1_DATA1 ,FN_IETX_B ,FN_SD1_DATA2 ,FN_IECLK_B ,FN_SD1_DATA3 ,FN_IERX_B , -FN_SD1_CD ,FN_PWM0 ,FN_TPU_TO0 ,FN_SCL1_C , +FN_SD1_CD ,FN_PWM0 ,FN_TPU_TO0 ,FN_I2C1_SCL_C ,/* IPSR14 */ -FN_SD1_WP ,FN_PWM1_B ,FN_SDA1_C , +FN_SD1_WP ,FN_PWM1_B ,FN_I2C1_SDA_C ,FN_SD2_CLK ,FN_MMC_CLK ,FN_SD2_CMD ,FN_MMC_CMD ,FN_SD2_DATA0 ,FN_MMC_D0 ,FN_SD2_DATA1 ,FN_MMC_D1 ,FN_SD2_DATA2 ,FN_MMC_D2 ,FN_SD2_DATA3 ,FN_MMC_D3 , -FN_SD2_CD ,FN_MMC_D4 ,FN_SCL8_C ,FN_TX5_B ,FN_SCIFA5_TXD_C , -FN_SD2_WP ,FN_MMC_D5 ,FN_SDA8_C ,FN_RX5_B ,FN_SCIFA5_RXD_C , +FN_SD2_CD ,FN_MMC_D4 ,FN_IIC1_SCL_C ,FN_TX5_B ,FN_SCIFA5_TXD_C , +FN_SD2_WP ,FN_MMC_D5 ,FN_IIC1_SDA_C ,FN_RX5_B ,FN_SCIFA5_RXD_C ,FN_MSIOF0_SCK ,FN_RX2_C ,FN_ADIDATA ,FN_VI1_CLK_C ,FN_VI1_G0_B ,FN_MSIOF0_SYNC ,FN_TX2_C ,FN_ADICS_SAMP ,FN_VI1_CLKENB_C ,FN_VI1_G1_B ,FN_MSIOF0_TXD ,FN_ADICLK ,FN_VI1_FIELD_C ,FN_VI1_G2_B ,FN_MSIOF0_RXD ,FN_ADICHS0 ,FN_VI1_DATA0_C ,FN_VI1_G3_B ,FN_MSIOF0_SS1 ,FN_MMC_D6 ,FN_ADICHS1 ,FN_TX0_E , -FN_VI1_HSYNC_N_C ,FN_SCL7_C ,FN_VI1_G4_B , +FN_VI1_HSYNC_N_C ,FN_IIC0_SCL_C ,FN_VI1_G4_B ,FN_MSIOF0_SS2 ,FN_MMC_D7 ,FN_ADICHS2 ,FN_RX0_E , -FN_VI1_VSYNC_N_C ,FN_SDA7_C ,FN_VI1_G5_B , +FN_VI1_VSYNC_N_C ,FN_IIC0_SDA_C ,FN_VI1_G5_B ,/* IPSR15 */ FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
@@ -432,18 +433,18 @@ enum {/* MOD_SEL3 */ FN_SEL_HSCIF2_0 ,FN_SEL_HSCIF2_1 ,FN_SEL_HSCIF2_2 ,FN_SEL_HSCIF2_3 ,FN_SEL_CANCLK_0 ,FN_SEL_CANCLK_1 ,FN_SEL_CANCLK_2 ,FN_SEL_CANCLK_3 , -FN_SEL_IIC8_0 ,FN_SEL_IIC8_1 ,FN_SEL_IIC8_2 , -FN_SEL_IIC7_0 ,FN_SEL_IIC7_1 ,FN_SEL_IIC7_2 , -FN_SEL_IIC4_0 ,FN_SEL_IIC4_1 ,FN_SEL_IIC4_2 , -FN_SEL_IIC3_0 ,FN_SEL_IIC3_1 ,FN_SEL_IIC3_2 ,FN_SEL_IIC3_3 , +FN_SEL_IIC1_0 ,FN_SEL_IIC1_1 ,FN_SEL_IIC1_2 , +FN_SEL_IIC0_0 ,FN_SEL_IIC0_1 ,FN_SEL_IIC0_2 , +FN_SEL_I2C4_0 ,FN_SEL_I2C4_1 ,FN_SEL_I2C4_2 , +FN_SEL_I2C3_0 ,FN_SEL_I2C3_1 ,FN_SEL_I2C3_2 ,FN_SEL_I2C3_3 ,FN_SEL_SCIF3_0 ,FN_SEL_SCIF3_1 ,FN_SEL_SCIF3_2 ,FN_SEL_SCIF3_3 ,FN_SEL_IEB_0 ,FN_SEL_IEB_1 ,FN_SEL_IEB_2 ,FN_SEL_MMC_0 ,FN_SEL_MMC_1 ,FN_SEL_SCIF5_0 ,FN_SEL_SCIF5_1 , -FN_SEL_IIC2_0 ,FN_SEL_IIC2_1 ,FN_SEL_IIC2_2 ,FN_SEL_IIC2_3 , -FN_SEL_IIC1_0 ,FN_SEL_IIC1_1 ,FN_SEL_IIC1_2 ,FN_SEL_IIC1_3 , -FN_SEL_IIC1_4 , -FN_SEL_IIC0_0 ,FN_SEL_IIC0_1 ,FN_SEL_IIC0_2 , +FN_SEL_I2C2_0 ,FN_SEL_I2C2_1 ,FN_SEL_I2C2_2 ,FN_SEL_I2C2_3 , +FN_SEL_I2C1_0 ,FN_SEL_I2C1_1 ,FN_SEL_I2C1_2 ,FN_SEL_I2C1_3 , +FN_SEL_I2C1_4 , +FN_SEL_I2C0_0 ,FN_SEL_I2C0_1 ,FN_SEL_I2C0_2 ,/* MOD_SEL4 */ FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
@@ -481,22 +482,23 @@ enum {D0_MARK ,D1_MARK ,D2_MARK ,D3_MARK ,D4_MARK ,D5_MARK ,D6_MARK ,D7_MARK ,D8_MARK ,D9_MARK ,D10_MARK ,D11_MARK ,D12_MARK ,D13_MARK ,D14_MARK ,D15_MARK , -A0_MARK ,ATAWR0_N_C_MARK ,MSIOF0_SCK_B_MARK ,SCL0_C_MARK ,PWM2_B_MARK , +A0_MARK ,ATAWR0_N_C_MARK ,MSIOF0_SCK_B_MARK ,I2C0_SCL_C_MARK , +PWM2_B_MARK ,A1_MARK ,MSIOF0_SYNC_B_MARK ,A2_MARK ,MSIOF0_SS1_B_MARK ,A3_MARK ,MSIOF0_SS2_B_MARK ,A4_MARK ,MSIOF0_TXD_B_MARK ,A5_MARK ,MSIOF0_RXD_B_MARK ,A6_MARK ,MSIOF1_SCK_MARK ,/* IPSR1 */ -A7_MARK ,MSIOF1_SYNC_MARK ,A8_MARK ,MSIOF1_SS1_MARK ,SCL0_MARK , -A9_MARK ,MSIOF1_SS2_MARK ,SDA0_MARK , +A7_MARK ,MSIOF1_SYNC_MARK ,A8_MARK ,MSIOF1_SS1_MARK ,I2C0_SCL_MARK , +A9_MARK ,MSIOF1_SS2_MARK ,I2C0_SDA_MARK ,A10_MARK ,MSIOF1_TXD_MARK ,MSIOF1_TXD_D_MARK , -A11_MARK ,MSIOF1_RXD_MARK ,SCL3_D_MARK ,MSIOF1_RXD_D_MARK , -A12_MARK ,FMCLK_MARK ,SDA3_D_MARK ,MSIOF1_SCK_D_MARK , +A11_MARK ,MSIOF1_RXD_MARK ,I2C3_SCL_D_MARK ,MSIOF1_RXD_D_MARK , +A12_MARK ,FMCLK_MARK ,I2C3_SDA_D_MARK ,MSIOF1_SCK_D_MARK ,A13_MARK ,ATAG0_N_C_MARK ,BPFCLK_MARK ,MSIOF1_SS1_D_MARK ,A14_MARK ,ATADIR0_N_C_MARK ,FMIN_MARK ,FMIN_C_MARK ,MSIOF1_SYNC_D_MARK ,A15_MARK ,BPFCLK_C_MARK ,A16_MARK ,DREQ2_B_MARK ,FMCLK_C_MARK ,SCIFA1_SCK_B_MARK , -A17_MARK ,DACK2_B_MARK ,SDA0_C_MARK , +A17_MARK ,DACK2_B_MARK ,I2C0_SDA_C_MARK ,A18_MARK ,DREQ1_MARK ,SCIFA1_RXD_C_MARK ,SCIFB1_RXD_C_MARK , /* IPSR2 */
@@ -509,8 +511,8 @@ enum {A24_MARK ,DREQ2_MARK ,IO3_MARK ,TX1_MARK ,SCIFA1_TXD_MARK ,A25_MARK ,DACK2_MARK ,SSL_MARK ,DREQ1_C_MARK ,RX1_MARK ,SCIFA1_RXD_MARK , -CS0_N_MARK ,ATAG0_N_B_MARK ,SCL1_MARK , -CS1_N_A26_MARK ,ATADIR0_N_B_MARK ,SDA1_MARK , +CS0_N_MARK ,ATAG0_N_B_MARK ,I2C1_SCL_MARK , +CS1_N_A26_MARK ,ATADIR0_N_B_MARK ,I2C1_SDA_MARK ,EX_CS1_N_MARK ,MSIOF2_SCK_MARK ,EX_CS2_N_MARK ,ATAWR0_N_MARK ,MSIOF2_SYNC_MARK , EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
@@ -537,14 +539,15 @@ enum {SCIFB0_TXD_C_MARK ,SCIFB2_TXD_C_MARK ,/* IPSR4 */ -SSI_SDATA0_MARK ,SCL0_B_MARK ,SCL7_B_MARK ,MSIOF2_SCK_C_MARK , -SSI_SCK1_MARK ,SDA0_B_MARK ,SDA7_B_MARK , +SSI_SDATA0_MARK ,I2C0_SCL_B_MARK ,IIC0_SCL_B_MARK ,MSIOF2_SCK_C_MARK , +SSI_SCK1_MARK ,I2C0_SDA_B_MARK ,IIC0_SDA_B_MARK ,MSIOF2_SYNC_C_MARK ,GLO_I0_D_MARK , -SSI_WS1_MARK ,SCL1_B_MARK ,SCL8_B_MARK , +SSI_WS1_MARK ,I2C1_SCL_B_MARK ,IIC1_SCL_B_MARK ,MSIOF2_TXD_C_MARK ,GLO_I1_D_MARK , -SSI_SDATA1_MARK ,SDA1_B_MARK ,SDA8_B_MARK ,MSIOF2_RXD_C_MARK , -SSI_SCK2_MARK ,SCL2_MARK ,GPS_CLK_B_MARK ,GLO_Q0_D_MARK ,HSCK1_E_MARK , -SSI_WS2_MARK ,SDA2_MARK ,GPS_SIGN_B_MARK ,RX2_E_MARK , +SSI_SDATA1_MARK ,I2C1_SDA_B_MARK ,IIC1_SDA_B_MARK ,MSIOF2_RXD_C_MARK , +SSI_SCK2_MARK ,I2C2_SCL_MARK ,GPS_CLK_B_MARK ,GLO_Q0_D_MARK , +HSCK1_E_MARK , +SSI_WS2_MARK ,I2C2_SDA_MARK ,GPS_SIGN_B_MARK ,RX2_E_MARK ,GLO_Q1_D_MARK ,HCTS1_N_E_MARK ,SSI_SDATA2_MARK ,GPS_MAG_B_MARK ,TX2_E_MARK ,HRTS1_N_E_MARK , SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
@@ -580,12 +583,12 @@ enum {IRQ0_MARK ,SCIFB1_RXD_D_MARK ,INTC_IRQ0_N_MARK ,IRQ1_MARK ,SCIFB1_SCK_C_MARK ,INTC_IRQ1_N_MARK ,IRQ2_MARK ,SCIFB1_TXD_D_MARK ,INTC_IRQ2_N_MARK , -IRQ3_MARK ,SCL4_C_MARK ,MSIOF2_TXD_E_MARK ,INTC_IRQ3_N_MARK , -IRQ4_MARK ,HRX1_C_MARK ,SDA4_C_MARK , +IRQ3_MARK ,I2C4_SCL_C_MARK ,MSIOF2_TXD_E_MARK ,INTC_IRQ3_N_MARK , +IRQ4_MARK ,HRX1_C_MARK ,I2C4_SDA_C_MARK ,MSIOF2_RXD_E_MARK ,INTC_IRQ4_N_MARK , -IRQ5_MARK ,HTX1_C_MARK ,SCL1_E_MARK ,MSIOF2_SCK_E_MARK , +IRQ5_MARK ,HTX1_C_MARK ,I2C1_SCL_E_MARK ,MSIOF2_SCK_E_MARK ,IRQ6_MARK ,HSCK1_C_MARK ,MSIOF1_SS2_B_MARK , -SDA1_E_MARK ,MSIOF2_SYNC_E_MARK , +I2C1_SDA_E_MARK ,MSIOF2_SYNC_E_MARK ,IRQ7_MARK ,HCTS1_N_C_MARK ,MSIOF1_TXD_B_MARK ,GPS_CLK_C_MARK ,GPS_CLK_D_MARK , IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
@@ -632,17 +635,17 @@ enum {DU1_DB5_MARK ,LCDOUT21_MARK ,TX3_MARK ,SCIFA3_TXD_MARK ,CAN1_TX_MARK ,/* IPSR9 */ -DU1_DB6_MARK ,LCDOUT22_MARK ,SCL3_C_MARK ,RX3_MARK ,SCIFA3_RXD_MARK , -DU1_DB7_MARK ,LCDOUT23_MARK ,SDA3_C_MARK , +DU1_DB6_MARK ,LCDOUT22_MARK ,I2C3_SCL_C_MARK ,RX3_MARK ,SCIFA3_RXD_MARK , +DU1_DB7_MARK ,LCDOUT23_MARK ,I2C3_SDA_C_MARK ,SCIF3_SCK_MARK ,SCIFA3_SCK_MARK ,DU1_DOTCLKIN_MARK ,QSTVA_QVS_MARK ,DU1_DOTCLKOUT0_MARK ,QCLK_MARK ,DU1_DOTCLKOUT1_MARK ,QSTVB_QVE_MARK ,CAN0_TX_MARK , -TX3_B_MARK ,SCL2_B_MARK ,PWM4_MARK , +TX3_B_MARK ,I2C2_SCL_B_MARK ,PWM4_MARK ,DU1_EXHSYNC_DU1_HSYNC_MARK ,QSTH_QHS_MARK ,DU1_EXVSYNC_DU1_VSYNC_MARK ,QSTB_QHE_MARK ,DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK ,QCPV_QDE_MARK , -CAN0_RX_MARK ,RX3_B_MARK ,SDA2_B_MARK , +CAN0_RX_MARK ,RX3_B_MARK ,I2C2_SDA_B_MARK ,DU1_DISP_MARK ,QPOLA_MARK ,DU1_CDE_MARK ,QPOLB_MARK ,PWM4_B_MARK , VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
@@ -650,15 +653,15 @@ enum {VI0_HSYNC_N_MARK ,TX5_MARK ,SCIFA5_TXD_MARK ,TS_SDEN0_D_MARK ,VI0_VSYNC_N_MARK ,RX5_MARK ,SCIFA5_RXD_MARK ,TS_SPSYNC0_D_MARK ,VI0_DATA3_VI0_B3_MARK ,SCIF3_SCK_B_MARK ,SCIFA3_SCK_B_MARK , -VI0_G0_MARK ,SCL8_MARK ,STP_IVCXO27_0_C_MARK ,SCL4_MARK , +VI0_G0_MARK ,IIC1_SCL_MARK ,STP_IVCXO27_0_C_MARK ,I2C4_SCL_MARK ,HCTS2_N_MARK ,SCIFB2_CTS_N_MARK ,ATAWR1_N_MARK ,/* IPSR10 */ -VI0_G1_MARK ,SDA8_MARK ,STP_ISCLK_0_C_MARK ,SDA4_MARK , +VI0_G1_MARK ,IIC1_SDA_MARK ,STP_ISCLK_0_C_MARK ,I2C4_SDA_MARK ,HRTS2_N_MARK ,SCIFB2_RTS_N_MARK ,ATADIR1_N_MARK , -VI0_G2_MARK ,VI2_HSYNC_N_MARK ,STP_ISD_0_C_MARK ,SCL3_B_MARK , +VI0_G2_MARK ,VI2_HSYNC_N_MARK ,STP_ISD_0_C_MARK ,I2C3_SCL_B_MARK ,HSCK2_MARK ,SCIFB2_SCK_MARK ,ATARD1_N_MARK , -VI0_G3_MARK ,VI2_VSYNC_N_MARK ,STP_ISEN_0_C_MARK ,SDA3_B_MARK , +VI0_G3_MARK ,VI2_VSYNC_N_MARK ,STP_ISEN_0_C_MARK ,I2C3_SDA_B_MARK ,HRX2_MARK ,SCIFB2_RXD_MARK ,ATACS01_N_MARK ,VI0_G4_MARK ,VI2_CLKENB_MARK ,STP_ISSYNC_0_C_MARK , HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
@@ -672,13 +675,15 @@ enum {TS_SCK0_C_MARK ,ATAG1_N_MARK ,VI0_R2_MARK ,VI2_DATA3_MARK ,GLO_Q0_B_MARK ,TS_SDEN0_C_MARK ,VI0_R3_MARK ,VI2_DATA4_MARK ,GLO_Q1_B_MARK ,TS_SPSYNC0_C_MARK , -VI0_R4_MARK ,VI2_DATA5_MARK ,GLO_SCLK_B_MARK ,TX0_C_MARK ,SCL1_D_MARK , +VI0_R4_MARK ,VI2_DATA5_MARK ,GLO_SCLK_B_MARK ,TX0_C_MARK , +I2C1_SCL_D_MARK ,/* IPSR11 */ -VI0_R5_MARK ,VI2_DATA6_MARK ,GLO_SDATA_B_MARK ,RX0_C_MARK ,SDA1_D_MARK , -VI0_R6_MARK ,VI2_DATA7_MARK ,GLO_SS_B_MARK ,TX1_C_MARK ,SCL4_B_MARK , +VI0_R5_MARK ,VI2_DATA6_MARK ,GLO_SDATA_B_MARK ,RX0_C_MARK , +I2C1_SDA_D_MARK , +VI0_R6_MARK ,VI2_DATA7_MARK ,GLO_SS_B_MARK ,TX1_C_MARK ,I2C4_SCL_B_MARK ,VI0_R7_MARK ,GLO_RFON_B_MARK ,RX1_C_MARK ,CAN0_RX_E_MARK , -SDA4_B_MARK ,HRX1_D_MARK ,SCIFB0_RXD_D_MARK , +I2C4_SDA_B_MARK ,HRX1_D_MARK ,SCIFB0_RXD_D_MARK ,VI1_HSYNC_N_MARK ,AVB_RXD0_MARK ,TS_SDATA0_B_MARK ,TX4_B_MARK ,SCIFA4_TXD_B_MARK , VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
@@ -690,16 +695,16 @@ enum {VI1_DATA3_MARK ,AVB_RX_ER_MARK ,VI1_DATA4_MARK ,AVB_MDIO_MARK ,VI1_DATA5_MARK ,AVB_RX_DV_MARK ,VI1_DATA6_MARK ,AVB_MAGIC_MARK ,VI1_DATA7_MARK ,AVB_MDC_MARK , -ETH_MDIO_MARK ,AVB_RX_CLK_MARK ,SCL2_C_MARK , -ETH_CRS_DV_MARK ,AVB_LINK_MARK ,SDA2_C_MARK , +ETH_MDIO_MARK ,AVB_RX_CLK_MARK ,I2C2_SCL_C_MARK , +ETH_CRS_DV_MARK ,AVB_LINK_MARK ,I2C2_SDA_C_MARK ,/* IPSR12 */ -ETH_RX_ER_MARK ,AVB_CRS_MARK ,SCL3_MARK ,SCL7_MARK , -ETH_RXD0_MARK ,AVB_PHY_INT_MARK ,SDA3_MARK ,SDA7_MARK , +ETH_RX_ER_MARK ,AVB_CRS_MARK ,I2C3_SCL_MARK ,IIC0_SCL_MARK , +ETH_RXD0_MARK ,AVB_PHY_INT_MARK ,I2C3_SDA_MARK ,IIC0_SDA_MARK ,ETH_RXD1_MARK ,AVB_GTXREFCLK_MARK ,CAN0_TX_C_MARK , -SCL2_D_MARK ,MSIOF1_RXD_E_MARK , +I2C2_SCL_D_MARK ,MSIOF1_RXD_E_MARK ,ETH_LINK_MARK ,AVB_TXD0_MARK ,CAN0_RX_C_MARK , -SDA2_D_MARK ,MSIOF1_SCK_E_MARK , +I2C2_SDA_D_MARK ,MSIOF1_SCK_E_MARK ,ETH_REFCLK_MARK ,AVB_TXD1_MARK ,SCIFA3_RXD_B_MARK ,CAN1_RX_C_MARK ,MSIOF1_SYNC_E_MARK , ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
@@ -730,15 +735,17 @@ enum {SD1_CMD_MARK ,REMOCON_B_MARK ,SD1_DATA0_MARK ,SPEEDIN_B_MARK ,SD1_DATA1_MARK ,IETX_B_MARK ,SD1_DATA2_MARK ,IECLK_B_MARK ,SD1_DATA3_MARK ,IERX_B_MARK , -SD1_CD_MARK ,PWM0_MARK ,TPU_TO0_MARK ,SCL1_C_MARK , +SD1_CD_MARK ,PWM0_MARK ,TPU_TO0_MARK ,I2C1_SCL_C_MARK ,/* IPSR14 */ -SD1_WP_MARK ,PWM1_B_MARK ,SDA1_C_MARK , +SD1_WP_MARK ,PWM1_B_MARK ,I2C1_SDA_C_MARK ,SD2_CLK_MARK ,MMC_CLK_MARK ,SD2_CMD_MARK ,MMC_CMD_MARK ,SD2_DATA0_MARK ,MMC_D0_MARK ,SD2_DATA1_MARK ,MMC_D1_MARK ,SD2_DATA2_MARK ,MMC_D2_MARK ,SD2_DATA3_MARK ,MMC_D3_MARK , -SD2_CD_MARK ,MMC_D4_MARK ,SCL8_C_MARK ,TX5_B_MARK ,SCIFA5_TXD_C_MARK , -SD2_WP_MARK ,MMC_D5_MARK ,SDA8_C_MARK ,RX5_B_MARK ,SCIFA5_RXD_C_MARK , +SD2_CD_MARK ,MMC_D4_MARK ,IIC1_SCL_C_MARK ,TX5_B_MARK , +SCIFA5_TXD_C_MARK , +SD2_WP_MARK ,MMC_D5_MARK ,IIC1_SDA_C_MARK ,RX5_B_MARK , +SCIFA5_RXD_C_MARK ,MSIOF0_SCK_MARK ,RX2_C_MARK ,ADIDATA_MARK ,VI1_CLK_C_MARK ,VI1_G0_B_MARK , MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
@@ -746,9 +753,9 @@ enum {MSIOF0_TXD_MARK ,ADICLK_MARK ,VI1_FIELD_C_MARK ,VI1_G2_B_MARK ,MSIOF0_RXD_MARK ,ADICHS0_MARK ,VI1_DATA0_C_MARK ,VI1_G3_B_MARK ,MSIOF0_SS1_MARK ,MMC_D6_MARK ,ADICHS1_MARK ,TX0_E_MARK , -VI1_HSYNC_N_C_MARK ,SCL7_C_MARK ,VI1_G4_B_MARK , +VI1_HSYNC_N_C_MARK ,IIC0_SCL_C_MARK ,VI1_G4_B_MARK ,MSIOF0_SS2_MARK ,MMC_D7_MARK ,ADICHS2_MARK ,RX0_E_MARK , -VI1_VSYNC_N_C_MARK ,SDA7_C_MARK ,VI1_G5_B_MARK , +VI1_VSYNC_N_C_MARK ,IIC0_SDA_C_MARK ,VI1_G5_B_MARK ,/* IPSR15 */ SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
@@ -822,7 +829,7 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_GPSR (IP0_18_16 ,A0 ),PINMUX_IPSR_MSEL (IP0_18_16 ,ATAWR0_N_C ,SEL_LBS_2 ),PINMUX_IPSR_MSEL (IP0_18_16 ,MSIOF0_SCK_B ,SEL_SOF0_1 ), -PINMUX_IPSR_MSEL (IP0_18_16 ,SCL0_C ,SEL_IIC0_2 ), +PINMUX_IPSR_MSEL (IP0_18_16 ,I2C0_SCL_C ,SEL_I2C0_2 ),PINMUX_IPSR_GPSR (IP0_18_16 ,PWM2_B ),PINMUX_IPSR_GPSR (IP0_20_19 ,A1 ), PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
@@ -842,20 +849,20 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_MSEL (IP1_1_0 ,MSIOF1_SYNC ,SEL_SOF1_0 ),PINMUX_IPSR_GPSR (IP1_3_2 ,A8 ),PINMUX_IPSR_MSEL (IP1_3_2 ,MSIOF1_SS1 ,SEL_SOF1_0 ), -PINMUX_IPSR_MSEL (IP1_3_2 ,SCL0 ,SEL_IIC0_0 ), +PINMUX_IPSR_MSEL (IP1_3_2 ,I2C0_SCL ,SEL_I2C0_0 ),PINMUX_IPSR_GPSR (IP1_5_4 ,A9 ),PINMUX_IPSR_MSEL (IP1_5_4 ,MSIOF1_SS2 ,SEL_SOF1_0 ), -PINMUX_IPSR_MSEL (IP1_5_4 ,SDA0 ,SEL_IIC0_0 ), +PINMUX_IPSR_MSEL (IP1_5_4 ,I2C0_SDA ,SEL_I2C0_0 ),PINMUX_IPSR_GPSR (IP1_7_6 ,A10 ),PINMUX_IPSR_MSEL (IP1_7_6 ,MSIOF1_TXD ,SEL_SOF1_0 ),PINMUX_IPSR_MSEL (IP1_7_6 ,MSIOF1_TXD_D ,SEL_SOF1_3 ),PINMUX_IPSR_GPSR (IP1_10_8 ,A11 ),PINMUX_IPSR_MSEL (IP1_10_8 ,MSIOF1_RXD ,SEL_SOF1_0 ), -PINMUX_IPSR_MSEL (IP1_10_8 ,SCL3_D ,SEL_IIC3_3 ), +PINMUX_IPSR_MSEL (IP1_10_8 ,I2C3_SCL_D ,SEL_I2C3_3 ),PINMUX_IPSR_MSEL (IP1_10_8 ,MSIOF1_RXD_D ,SEL_SOF1_3 ),PINMUX_IPSR_GPSR (IP1_13_11 ,A12 ),PINMUX_IPSR_MSEL (IP1_13_11 ,FMCLK ,SEL_FM_0 ), -PINMUX_IPSR_MSEL (IP1_13_11 ,SDA3_D ,SEL_IIC3_3 ), +PINMUX_IPSR_MSEL (IP1_13_11 ,I2C3_SDA_D ,SEL_I2C3_3 ),PINMUX_IPSR_MSEL (IP1_13_11 ,MSIOF1_SCK_D ,SEL_SOF1_3 ),PINMUX_IPSR_GPSR (IP1_16_14 ,A13 ), PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
@@ -874,7 +881,7 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_MSEL (IP1_25_23 ,SCIFA1_SCK_B ,SEL_SCIFA1_1 ),PINMUX_IPSR_GPSR (IP1_28_26 ,A17 ),PINMUX_IPSR_MSEL (IP1_28_26 ,DACK2_B ,SEL_LBS_1 ), -PINMUX_IPSR_MSEL (IP1_28_26 ,SDA0_C ,SEL_IIC0_2 ), +PINMUX_IPSR_MSEL (IP1_28_26 ,I2C0_SDA_C ,SEL_I2C0_2 ),PINMUX_IPSR_GPSR (IP1_31_29 ,A18 ),PINMUX_IPSR_MSEL (IP1_31_29 ,DREQ1 ,SEL_LBS_0 ), PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
@@ -914,10 +921,10 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_MSEL (IP2_18_16 ,SCIFA1_RXD ,SEL_SCIFA1_0 ),PINMUX_IPSR_GPSR (IP2_20_19 ,CS0_N ),PINMUX_IPSR_MSEL (IP2_20_19 ,ATAG0_N_B ,SEL_LBS_1 ), -PINMUX_IPSR_MSEL (IP2_20_19 ,SCL1 ,SEL_IIC1_0 ), +PINMUX_IPSR_MSEL (IP2_20_19 ,I2C1_SCL ,SEL_I2C1_0 ),PINMUX_IPSR_GPSR (IP2_22_21 ,CS1_N_A26 ),PINMUX_IPSR_MSEL (IP2_22_21 ,ATADIR0_N_B ,SEL_LBS_1 ), -PINMUX_IPSR_MSEL (IP2_22_21 ,SDA1 ,SEL_IIC1_0 ), +PINMUX_IPSR_MSEL (IP2_22_21 ,I2C1_SDA ,SEL_I2C1_0 ),PINMUX_IPSR_GPSR (IP2_24_23 ,EX_CS1_N ),PINMUX_IPSR_MSEL (IP2_24_23 ,MSIOF2_SCK ,SEL_SOF2_0 ), PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
@@ -989,30 +996,30 @@ static const u16 pinmux_data[] = {/* IPSR4 */ PINMUX_IPSR_MSEL (IP4_1_0 ,SSI_SDATA0 ,SEL_SSI0_0 ), -PINMUX_IPSR_MSEL (IP4_1_0 ,SCL0_B ,SEL_IIC0_1 ), -PINMUX_IPSR_MSEL (IP4_1_0 ,SCL7_B ,SEL_IIC7_1 ), +PINMUX_IPSR_MSEL (IP4_1_0 ,I2C0_SCL_B ,SEL_I2C0_1 ), +PINMUX_IPSR_MSEL (IP4_1_0 ,IIC0_SCL_B ,SEL_IIC0_1 ),PINMUX_IPSR_MSEL (IP4_1_0 ,MSIOF2_SCK_C ,SEL_SOF2_2 ),PINMUX_IPSR_MSEL (IP4_4_2 ,SSI_SCK1 ,SEL_SSI1_0 ), -PINMUX_IPSR_MSEL (IP4_4_2 ,SDA0_B ,SEL_IIC0_1 ), -PINMUX_IPSR_MSEL (IP4_4_2 ,SDA7_B ,SEL_IIC7_1 ), +PINMUX_IPSR_MSEL (IP4_4_2 ,I2C0_SDA_B ,SEL_I2C0_1 ), +PINMUX_IPSR_MSEL (IP4_4_2 ,IIC0_SDA_B ,SEL_IIC0_1 ),PINMUX_IPSR_MSEL (IP4_4_2 ,MSIOF2_SYNC_C ,SEL_SOF2_2 ),PINMUX_IPSR_MSEL (IP4_4_2 ,GLO_I0_D ,SEL_GPS_3 ),PINMUX_IPSR_MSEL (IP4_7_5 ,SSI_WS1 ,SEL_SSI1_0 ), -PINMUX_IPSR_MSEL (IP4_7_5 ,SCL1_B ,SEL_IIC1_1 ), -PINMUX_IPSR_MSEL (IP4_7_5 ,SCL8_B ,SEL_IIC8_1 ), +PINMUX_IPSR_MSEL (IP4_7_5 ,I2C1_SCL_B ,SEL_I2C1_1 ), +PINMUX_IPSR_MSEL (IP4_7_5 ,IIC1_SCL_B ,SEL_IIC1_1 ),PINMUX_IPSR_MSEL (IP4_7_5 ,MSIOF2_TXD_C ,SEL_SOF2_2 ),PINMUX_IPSR_MSEL (IP4_7_5 ,GLO_I1_D ,SEL_GPS_3 ),PINMUX_IPSR_MSEL (IP4_9_8 ,SSI_SDATA1 ,SEL_SSI1_0 ), -PINMUX_IPSR_MSEL (IP4_9_8 ,SDA1_B ,SEL_IIC1_1 ), -PINMUX_IPSR_MSEL (IP4_9_8 ,SDA8_B ,SEL_IIC8_1 ), +PINMUX_IPSR_MSEL (IP4_9_8 ,I2C1_SDA_B ,SEL_I2C1_1 ), +PINMUX_IPSR_MSEL (IP4_9_8 ,IIC1_SDA_B ,SEL_IIC1_1 ),PINMUX_IPSR_MSEL (IP4_9_8 ,MSIOF2_RXD_C ,SEL_SOF2_2 ),PINMUX_IPSR_GPSR (IP4_12_10 ,SSI_SCK2 ), -PINMUX_IPSR_MSEL (IP4_12_10 ,SCL2 ,SEL_IIC2_0 ), +PINMUX_IPSR_MSEL (IP4_12_10 ,I2C2_SCL ,SEL_I2C2_0 ),PINMUX_IPSR_MSEL (IP4_12_10 ,GPS_CLK_B ,SEL_GPS_1 ),PINMUX_IPSR_MSEL (IP4_12_10 ,GLO_Q0_D ,SEL_GPS_3 ),PINMUX_IPSR_MSEL (IP4_12_10 ,HSCK1_E ,SEL_HSCIF1_4 ),PINMUX_IPSR_GPSR (IP4_15_13 ,SSI_WS2 ), -PINMUX_IPSR_MSEL (IP4_15_13 ,SDA2 ,SEL_IIC2_0 ), +PINMUX_IPSR_MSEL (IP4_15_13 ,I2C2_SDA ,SEL_I2C2_0 ),PINMUX_IPSR_MSEL (IP4_15_13 ,GPS_SIGN_B ,SEL_GPS_1 ),PINMUX_IPSR_MSEL (IP4_15_13 ,RX2_E ,SEL_SCIF2_4 ), PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
@@ -1115,22 +1122,22 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_MSEL (IP6_13_12 ,SCIFB1_TXD_D ,SEL_SCIFB1_3 ),PINMUX_IPSR_GPSR (IP6_13_12 ,INTC_IRQ2_N ),PINMUX_IPSR_GPSR (IP6_15_14 ,IRQ3 ), -PINMUX_IPSR_MSEL (IP6_15_14 ,SCL4_C ,SEL_IIC4_2 ), +PINMUX_IPSR_MSEL (IP6_15_14 ,I2C4_SCL_C ,SEL_I2C4_2 ),PINMUX_IPSR_MSEL (IP6_15_14 ,MSIOF2_TXD_E ,SEL_SOF2_4 ),PINMUX_IPSR_GPSR (IP6_15_14 ,INTC_IRQ4_N ),PINMUX_IPSR_GPSR (IP6_18_16 ,IRQ4 ),PINMUX_IPSR_MSEL (IP6_18_16 ,HRX1_C ,SEL_HSCIF1_2 ), -PINMUX_IPSR_MSEL (IP6_18_16 ,SDA4_C ,SEL_IIC4_2 ), +PINMUX_IPSR_MSEL (IP6_18_16 ,I2C4_SDA_C ,SEL_I2C4_2 ),PINMUX_IPSR_MSEL (IP6_18_16 ,MSIOF2_RXD_E ,SEL_SOF2_4 ),PINMUX_IPSR_GPSR (IP6_18_16 ,INTC_IRQ4_N ),PINMUX_IPSR_GPSR (IP6_20_19 ,IRQ5 ),PINMUX_IPSR_MSEL (IP6_20_19 ,HTX1_C ,SEL_HSCIF1_2 ), -PINMUX_IPSR_MSEL (IP6_20_19 ,SCL1_E ,SEL_IIC1_4 ), +PINMUX_IPSR_MSEL (IP6_20_19 ,I2C1_SCL_E ,SEL_I2C1_4 ),PINMUX_IPSR_MSEL (IP6_20_19 ,MSIOF2_SCK_E ,SEL_SOF2_4 ),PINMUX_IPSR_GPSR (IP6_23_21 ,IRQ6 ),PINMUX_IPSR_MSEL (IP6_23_21 ,HSCK1_C ,SEL_HSCIF1_2 ),PINMUX_IPSR_MSEL (IP6_23_21 ,MSIOF1_SS2_B ,SEL_SOF1_1 ), -PINMUX_IPSR_MSEL (IP6_23_21 ,SDA1_E ,SEL_IIC1_4 ), +PINMUX_IPSR_MSEL (IP6_23_21 ,I2C1_SDA_E ,SEL_I2C1_4 ),PINMUX_IPSR_MSEL (IP6_23_21 ,MSIOF2_SYNC_E ,SEL_SOF2_4 ),PINMUX_IPSR_GPSR (IP6_26_24 ,IRQ7 ), PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
@@ -1260,12 +1267,12 @@ static const u16 pinmux_data[] = {/* IPSR9 */ PINMUX_IPSR_GPSR (IP9_2_0 ,DU1_DB6 ),PINMUX_IPSR_GPSR (IP9_2_0 ,LCDOUT22 ), -PINMUX_IPSR_MSEL (IP9_2_0 ,SCL3_C ,SEL_IIC3_2 ), +PINMUX_IPSR_MSEL (IP9_2_0 ,I2C3_SCL_C ,SEL_I2C3_2 ),PINMUX_IPSR_MSEL (IP9_2_0 ,RX3 ,SEL_SCIF3_0 ),PINMUX_IPSR_MSEL (IP9_2_0 ,SCIFA3_RXD ,SEL_SCIFA3_0 ),PINMUX_IPSR_GPSR (IP9_5_3 ,DU1_DB7 ),PINMUX_IPSR_GPSR (IP9_5_3 ,LCDOUT23 ), -PINMUX_IPSR_MSEL (IP9_5_3 ,SDA3_C ,SEL_IIC3_2 ), +PINMUX_IPSR_MSEL (IP9_5_3 ,I2C3_SDA_C ,SEL_I2C3_2 ),PINMUX_IPSR_MSEL (IP9_5_3 ,SCIF3_SCK ,SEL_SCIF3_0 ),PINMUX_IPSR_MSEL (IP9_5_3 ,SCIFA3_SCK ,SEL_SCIFA3_0 ), PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
@@ -1276,7 +1283,7 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_GPSR (IP9_10_8 ,QSTVB_QVE ),PINMUX_IPSR_MSEL (IP9_10_8 ,CAN0_TX ,SEL_CAN0_0 ),PINMUX_IPSR_MSEL (IP9_10_8 ,TX3_B ,SEL_SCIF3_1 ), -PINMUX_IPSR_MSEL (IP9_10_8 ,SCL2_B ,SEL_IIC2_1 ), +PINMUX_IPSR_MSEL (IP9_10_8 ,I2C2_SCL_B ,SEL_I2C2_1 ),PINMUX_IPSR_GPSR (IP9_10_8 ,PWM4 ),PINMUX_IPSR_GPSR (IP9_11 ,DU1_EXHSYNC_DU1_HSYNC ), PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
@@ -1286,7 +1293,7 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_GPSR (IP9_15_13 ,QCPV_QDE ),PINMUX_IPSR_MSEL (IP9_15_13 ,CAN0_RX ,SEL_CAN0_0 ),PINMUX_IPSR_MSEL (IP9_15_13 ,RX3_B ,SEL_SCIF3_1 ), -PINMUX_IPSR_MSEL (IP9_15_13 ,SDA2_B ,SEL_IIC2_1 ), +PINMUX_IPSR_MSEL (IP9_15_13 ,I2C2_SDA_B ,SEL_I2C2_1 ),PINMUX_IPSR_GPSR (IP9_16 ,DU1_DISP ),PINMUX_IPSR_GPSR (IP9_16 ,QPOLA ), PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
@@ -1312,32 +1319,32 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_MSEL (IP9_28_27 ,SCIF3_SCK_B ,SEL_SCIF3_1 ),PINMUX_IPSR_MSEL (IP9_28_27 ,SCIFA3_SCK_B ,SEL_SCIFA3_1 ),PINMUX_IPSR_GPSR (IP9_31_29 ,VI0_G0 ), -PINMUX_IPSR_MSEL (IP9_31_29 ,SCL8 ,SEL_IIC8_0 ), +PINMUX_IPSR_MSEL (IP9_31_29 ,IIC1_SCL ,SEL_IIC1_0 ),PINMUX_IPSR_MSEL (IP9_31_29 ,STP_IVCXO27_0_C ,SEL_SSP_2 ), -PINMUX_IPSR_MSEL (IP9_31_29 ,SCL4 ,SEL_IIC4_0 ), +PINMUX_IPSR_MSEL (IP9_31_29 ,I2C4_SCL ,SEL_I2C4_0 ),PINMUX_IPSR_MSEL (IP9_31_29 ,HCTS2_N ,SEL_HSCIF2_0 ),PINMUX_IPSR_MSEL (IP9_31_29 ,SCIFB2_CTS_N ,SEL_SCIFB2_0 ),PINMUX_IPSR_GPSR (IP9_31_29 ,ATAWR1_N ),/* IPSR10 */ PINMUX_IPSR_GPSR (IP10_2_0 ,VI0_G1 ), -PINMUX_IPSR_MSEL (IP10_2_0 ,SDA8 ,SEL_IIC8_0 ), +PINMUX_IPSR_MSEL (IP10_2_0 ,IIC1_SDA ,SEL_IIC1_0 ),PINMUX_IPSR_MSEL (IP10_2_0 ,STP_ISCLK_0_C ,SEL_SSP_2 ), -PINMUX_IPSR_MSEL (IP10_2_0 ,SDA4 ,SEL_IIC4_0 ), +PINMUX_IPSR_MSEL (IP10_2_0 ,I2C4_SDA ,SEL_I2C4_0 ),PINMUX_IPSR_MSEL (IP10_2_0 ,HRTS2_N ,SEL_HSCIF2_0 ),PINMUX_IPSR_MSEL (IP10_2_0 ,SCIFB2_RTS_N ,SEL_SCIFB2_0 ),PINMUX_IPSR_GPSR (IP10_2_0 ,ATADIR1_N ),PINMUX_IPSR_GPSR (IP10_5_3 ,VI0_G2 ),PINMUX_IPSR_GPSR (IP10_5_3 ,VI2_HSYNC_N ),PINMUX_IPSR_MSEL (IP10_5_3 ,STP_ISD_0_C ,SEL_SSP_2 ), -PINMUX_IPSR_MSEL (IP10_5_3 ,SCL3_B ,SEL_IIC3_1 ), +PINMUX_IPSR_MSEL (IP10_5_3 ,I2C3_SCL_B ,SEL_I2C3_1 ),PINMUX_IPSR_MSEL (IP10_5_3 ,HSCK2 ,SEL_HSCIF2_0 ),PINMUX_IPSR_MSEL (IP10_5_3 ,SCIFB2_SCK ,SEL_SCIFB2_0 ),PINMUX_IPSR_GPSR (IP10_5_3 ,ATARD1_N ),PINMUX_IPSR_GPSR (IP10_8_6 ,VI0_G3 ),PINMUX_IPSR_GPSR (IP10_8_6 ,VI2_VSYNC_N ),PINMUX_IPSR_MSEL (IP10_8_6 ,STP_ISEN_0_C ,SEL_SSP_2 ), -PINMUX_IPSR_MSEL (IP10_8_6 ,SDA3_B ,SEL_IIC3_1 ), +PINMUX_IPSR_MSEL (IP10_8_6 ,I2C3_SDA_B ,SEL_I2C3_1 ),PINMUX_IPSR_MSEL (IP10_8_6 ,HRX2 ,SEL_HSCIF2_0 ),PINMUX_IPSR_MSEL (IP10_8_6 ,SCIFB2_RXD ,SEL_SCIFB2_0 ), PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
@@ -1382,24 +1389,24 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_GPSR (IP10_31_29 ,VI2_DATA5 ),PINMUX_IPSR_MSEL (IP10_31_29 ,GLO_SCLK_B ,SEL_GPS_1 ),PINMUX_IPSR_MSEL (IP10_31_29 ,TX0_C ,SEL_SCIF0_2 ), -PINMUX_IPSR_MSEL (IP10_31_29 ,SCL1_D ,SEL_IIC1_3 ), +PINMUX_IPSR_MSEL (IP10_31_29 ,I2C1_SCL_D ,SEL_I2C1_3 ),/* IPSR11 */ PINMUX_IPSR_GPSR (IP11_2_0 ,VI0_R5 ),PINMUX_IPSR_GPSR (IP11_2_0 ,VI2_DATA6 ),PINMUX_IPSR_MSEL (IP11_2_0 ,GLO_SDATA_B ,SEL_GPS_1 ),PINMUX_IPSR_MSEL (IP11_2_0 ,RX0_C ,SEL_SCIF0_2 ), -PINMUX_IPSR_MSEL (IP11_2_0 ,SDA1_D ,SEL_IIC1_3 ), +PINMUX_IPSR_MSEL (IP11_2_0 ,I2C1_SDA_D ,SEL_I2C1_3 ),PINMUX_IPSR_GPSR (IP11_5_3 ,VI0_R6 ),PINMUX_IPSR_GPSR (IP11_5_3 ,VI2_DATA7 ),PINMUX_IPSR_MSEL (IP11_5_3 ,GLO_SS_B ,SEL_GPS_1 ),PINMUX_IPSR_MSEL (IP11_5_3 ,TX1_C ,SEL_SCIF1_2 ), -PINMUX_IPSR_MSEL (IP11_5_3 ,SCL4_B ,SEL_IIC4_1 ), +PINMUX_IPSR_MSEL (IP11_5_3 ,I2C4_SCL_B ,SEL_I2C4_1 ),PINMUX_IPSR_GPSR (IP11_8_6 ,VI0_R7 ),PINMUX_IPSR_MSEL (IP11_8_6 ,GLO_RFON_B ,SEL_GPS_1 ),PINMUX_IPSR_MSEL (IP11_8_6 ,RX1_C ,SEL_SCIF1_2 ),PINMUX_IPSR_MSEL (IP11_8_6 ,CAN0_RX_E ,SEL_CAN0_4 ), -PINMUX_IPSR_MSEL (IP11_8_6 ,SDA4_B ,SEL_IIC4_1 ), +PINMUX_IPSR_MSEL (IP11_8_6 ,I2C4_SDA_B ,SEL_I2C4_1 ),PINMUX_IPSR_MSEL (IP11_8_6 ,HRX1_D ,SEL_HSCIF1_3 ),PINMUX_IPSR_MSEL (IP11_8_6 ,SCIFB0_RXD_D ,SEL_SCIFB_3 ), PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
@@ -1438,29 +1445,29 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_GPSR (IP11_27 ,AVB_MDC ),PINMUX_IPSR_GPSR (IP11_29_28 ,ETH_MDIO ),PINMUX_IPSR_GPSR (IP11_29_28 ,AVB_RX_CLK ), -PINMUX_IPSR_MSEL (IP11_29_28 ,SCL2_C ,SEL_IIC2_2 ), +PINMUX_IPSR_MSEL (IP11_29_28 ,I2C2_SCL_C ,SEL_I2C2_2 ),PINMUX_IPSR_GPSR (IP11_31_30 ,ETH_CRS_DV ),PINMUX_IPSR_GPSR (IP11_31_30 ,AVB_LINK ), -PINMUX_IPSR_MSEL (IP11_31_30 ,SDA2_C ,SEL_IIC2_2 ), +PINMUX_IPSR_MSEL (IP11_31_30 ,I2C2_SDA_C ,SEL_I2C2_2 ),/* IPSR12 */ PINMUX_IPSR_GPSR (IP12_1_0 ,ETH_RX_ER ),PINMUX_IPSR_GPSR (IP12_1_0 ,AVB_CRS ), -PINMUX_IPSR_MSEL (IP12_1_0 ,SCL3 ,SEL_IIC3_0 ), -PINMUX_IPSR_MSEL (IP12_1_0 ,SCL7 ,SEL_IIC7_0 ), +PINMUX_IPSR_MSEL (IP12_1_0 ,I2C3_SCL ,SEL_I2C3_0 ), +PINMUX_IPSR_MSEL (IP12_1_0 ,IIC0_SCL ,SEL_IIC0_0 ),PINMUX_IPSR_GPSR (IP12_3_2 ,ETH_RXD0 ),PINMUX_IPSR_GPSR (IP12_3_2 ,AVB_PHY_INT ), -PINMUX_IPSR_MSEL (IP12_3_2 ,SDA3 ,SEL_IIC3_0 ), -PINMUX_IPSR_MSEL (IP12_3_2 ,SDA7 ,SEL_IIC7_0 ), +PINMUX_IPSR_MSEL (IP12_3_2 ,I2C3_SDA ,SEL_I2C3_0 ), +PINMUX_IPSR_MSEL (IP12_3_2 ,IIC0_SDA ,SEL_IIC0_0 ),PINMUX_IPSR_GPSR (IP12_6_4 ,ETH_RXD1 ),PINMUX_IPSR_GPSR (IP12_6_4 ,AVB_GTXREFCLK ),PINMUX_IPSR_MSEL (IP12_6_4 ,CAN0_TX_C ,SEL_CAN0_2 ), -PINMUX_IPSR_MSEL (IP12_6_4 ,SCL2_D ,SEL_IIC2_3 ), +PINMUX_IPSR_MSEL (IP12_6_4 ,I2C2_SCL_D ,SEL_I2C2_3 ),PINMUX_IPSR_MSEL (IP12_6_4 ,MSIOF1_RXD_E ,SEL_SOF1_4 ),PINMUX_IPSR_GPSR (IP12_9_7 ,ETH_LINK ),PINMUX_IPSR_GPSR (IP12_9_7 ,AVB_TXD0 ),PINMUX_IPSR_MSEL (IP12_9_7 ,CAN0_RX_C ,SEL_CAN0_2 ), -PINMUX_IPSR_MSEL (IP12_9_7 ,SDA2_D ,SEL_IIC2_3 ), +PINMUX_IPSR_MSEL (IP12_9_7 ,I2C2_SDA_D ,SEL_I2C2_3 ),PINMUX_IPSR_MSEL (IP12_9_7 ,MSIOF1_SCK_E ,SEL_SOF1_4 ),PINMUX_IPSR_GPSR (IP12_12_10 ,ETH_REFCLK ), PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
@@ -1552,12 +1559,12 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_GPSR (IP13_30_28 ,SD1_CD ),PINMUX_IPSR_GPSR (IP13_30_28 ,PWM0 ),PINMUX_IPSR_GPSR (IP13_30_28 ,TPU_TO0 ), -PINMUX_IPSR_MSEL (IP13_30_28 ,SCL1_C ,SEL_IIC1_2 ), +PINMUX_IPSR_MSEL (IP13_30_28 ,I2C1_SCL_C ,SEL_I2C1_2 ),/* IPSR14 */ PINMUX_IPSR_GPSR (IP14_1_0 ,SD1_WP ),PINMUX_IPSR_GPSR (IP14_1_0 ,PWM1_B ), -PINMUX_IPSR_MSEL (IP14_1_0 ,SDA1_C ,SEL_IIC1_2 ), +PINMUX_IPSR_MSEL (IP14_1_0 ,I2C1_SDA_C ,SEL_I2C1_2 ),PINMUX_IPSR_GPSR (IP14_2 ,SD2_CLK ),PINMUX_IPSR_GPSR (IP14_2 ,MMC_CLK ), PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
@@ -1572,12 +1579,12 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_GPSR (IP14_7 ,MMC_D3 ),PINMUX_IPSR_GPSR (IP14_10_8 ,SD2_CD ),PINMUX_IPSR_GPSR (IP14_10_8 ,MMC_D4 ), -PINMUX_IPSR_MSEL (IP14_10_8 ,SCL8_C ,SEL_IIC8_2 ), +PINMUX_IPSR_MSEL (IP14_10_8 ,IIC1_SCL_C ,SEL_IIC1_2 ),PINMUX_IPSR_MSEL (IP14_10_8 ,TX5_B ,SEL_SCIF5_1 ),PINMUX_IPSR_MSEL (IP14_10_8 ,SCIFA5_TXD_C ,SEL_SCIFA5_2 ),PINMUX_IPSR_GPSR (IP14_13_11 ,SD2_WP ),PINMUX_IPSR_GPSR (IP14_13_11 ,MMC_D5 ), -PINMUX_IPSR_MSEL (IP14_13_11 ,SDA8_C ,SEL_IIC8_2 ), +PINMUX_IPSR_MSEL (IP14_13_11 ,IIC1_SDA_C ,SEL_IIC1_2 ),PINMUX_IPSR_MSEL (IP14_13_11 ,RX5_B ,SEL_SCIF5_1 ),PINMUX_IPSR_MSEL (IP14_13_11 ,SCIFA5_RXD_C ,SEL_SCIFA5_2 ), PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
@@ -1603,14 +1610,14 @@ static const u16 pinmux_data[] = {PINMUX_IPSR_MSEL (IP14_28_26 ,ADICHS1 ,SEL_RAD_0 ),PINMUX_IPSR_MSEL (IP14_28_26 ,TX0_E ,SEL_SCIF0_4 ),PINMUX_IPSR_MSEL (IP14_28_26 ,VI1_HSYNC_N_C ,SEL_VI1_2 ), -PINMUX_IPSR_MSEL (IP14_28_26 ,SCL7_C ,SEL_IIC7_2 ), +PINMUX_IPSR_MSEL (IP14_28_26 ,IIC0_SCL_C ,SEL_IIC0_2 ),PINMUX_IPSR_GPSR (IP14_28_26 ,VI1_G4_B ),PINMUX_IPSR_MSEL (IP14_31_29 ,MSIOF0_SS2 ,SEL_SOF0_0 ),PINMUX_IPSR_MSEL (IP14_31_29 ,MMC_D7 ,SEL_MMC_0 ),PINMUX_IPSR_MSEL (IP14_31_29 ,ADICHS2 ,SEL_RAD_0 ),PINMUX_IPSR_MSEL (IP14_31_29 ,RX0_E ,SEL_SCIF0_4 ),PINMUX_IPSR_MSEL (IP14_31_29 ,VI1_VSYNC_N_C ,SEL_VI1_2 ), -PINMUX_IPSR_MSEL (IP14_31_29 ,SDA7_C ,SEL_IIC7_2 ), +PINMUX_IPSR_MSEL (IP14_31_29 ,IIC0_SDA_C ,SEL_IIC0_2 ),PINMUX_IPSR_GPSR (IP14_31_29 ,VI1_G5_B ), /* IPSR15 */
@@ -2343,21 +2350,21 @@ static const unsigned int i2c0_pins[] = RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), };static const unsigned int i2c0_mux[] = { -SCL0_MARK ,SDA0_MARK , +I2C0_SCL_MARK ,I2C0_SDA_MARK , };static const unsigned int i2c0_b_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (2 ,2 ),RCAR_GP_PIN (2 ,3 ), };static const unsigned int i2c0_b_mux[] = { -SCL0_B_MARK ,SDA0_B_MARK , +I2C0_SCL_B_MARK ,I2C0_SDA_B_MARK , };static const unsigned int i2c0_c_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (0 ,16 ),RCAR_GP_PIN (1 ,1 ), };static const unsigned int i2c0_c_mux[] = { -SCL0_C_MARK ,SDA0_C_MARK , +I2C0_SCL_C_MARK ,I2C0_SDA_C_MARK , };/* - I2C1 ------------------------------------------------------------------- */ static const unsigned int i2c1_pins[] = {
@@ -2365,35 +2372,35 @@ static const unsigned int i2c1_pins[] = RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), };static const unsigned int i2c1_mux[] = { -SCL1_MARK ,SDA1_MARK , +I2C1_SCL_MARK ,I2C1_SDA_MARK , };static const unsigned int i2c1_b_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (2 ,4 ),RCAR_GP_PIN (2 ,5 ), };static const unsigned int i2c1_b_mux[] = { -SCL1_B_MARK ,SDA1_B_MARK , +I2C1_SCL_B_MARK ,I2C1_SDA_B_MARK , };static const unsigned int i2c1_c_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (6 ,14 ),RCAR_GP_PIN (6 ,15 ), };static const unsigned int i2c1_c_mux[] = { -SCL1_C_MARK ,SDA1_C_MARK , +I2C1_SCL_C_MARK ,I2C1_SDA_C_MARK , };static const unsigned int i2c1_d_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (4 ,25 ),RCAR_GP_PIN (4 ,26 ), };static const unsigned int i2c1_d_mux[] = { -SCL1_D_MARK ,SDA1_D_MARK , +I2C1_SCL_D_MARK ,I2C1_SDA_D_MARK , };static const unsigned int i2c1_e_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (7 ,15 ),RCAR_GP_PIN (7 ,16 ), };static const unsigned int i2c1_e_mux[] = { -SCL1_E_MARK ,SDA1_E_MARK , +I2C1_SCL_E_MARK ,I2C1_SDA_E_MARK , };/* - I2C2 ------------------------------------------------------------------- */ static const unsigned int i2c2_pins[] = {
@@ -2401,28 +2408,28 @@ static const unsigned int i2c2_pins[] = RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), };static const unsigned int i2c2_mux[] = { -SCL2_MARK ,SDA2_MARK , +I2C2_SCL_MARK ,I2C2_SDA_MARK , };static const unsigned int i2c2_b_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (3 ,26 ),RCAR_GP_PIN (3 ,29 ), };static const unsigned int i2c2_b_mux[] = { -SCL2_B_MARK ,SDA2_B_MARK , +I2C2_SCL_B_MARK ,I2C2_SDA_B_MARK , };static const unsigned int i2c2_c_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (5 ,13 ),RCAR_GP_PIN (5 ,14 ), };static const unsigned int i2c2_c_mux[] = { -SCL2_C_MARK ,SDA2_C_MARK , +I2C2_SCL_C_MARK ,I2C2_SDA_C_MARK , };static const unsigned int i2c2_d_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (5 ,17 ),RCAR_GP_PIN (5 ,18 ), };static const unsigned int i2c2_d_mux[] = { -SCL2_D_MARK ,SDA2_D_MARK , +I2C2_SCL_D_MARK ,I2C2_SDA_D_MARK , };/* - I2C3 ------------------------------------------------------------------- */ static const unsigned int i2c3_pins[] = {
@@ -2430,28 +2437,28 @@ static const unsigned int i2c3_pins[] = RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), };static const unsigned int i2c3_mux[] = { -SCL3_MARK ,SDA3_MARK , +I2C3_SCL_MARK ,I2C3_SDA_MARK , };static const unsigned int i2c3_b_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (4 ,15 ),RCAR_GP_PIN (4 ,16 ), };static const unsigned int i2c3_b_mux[] = { -SCL3_B_MARK ,SDA3_B_MARK , +I2C3_SCL_B_MARK ,I2C3_SDA_B_MARK , };static const unsigned int i2c3_c_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (3 ,22 ),RCAR_GP_PIN (3 ,23 ), };static const unsigned int i2c3_c_mux[] = { -SCL3_C_MARK ,SDA3_C_MARK , +I2C3_SCL_C_MARK ,I2C3_SDA_C_MARK , };static const unsigned int i2c3_d_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (0 ,27 ),RCAR_GP_PIN (0 ,28 ), };static const unsigned int i2c3_d_mux[] = { -SCL3_D_MARK ,SDA3_D_MARK , +I2C3_SCL_D_MARK ,I2C3_SDA_D_MARK , };/* - I2C4 ------------------------------------------------------------------- */ static const unsigned int i2c4_pins[] = {
@@ -2459,65 +2466,65 @@ static const unsigned int i2c4_pins[] = RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), };static const unsigned int i2c4_mux[] = { -SCL4_MARK ,SDA4_MARK , +I2C4_SCL_MARK ,I2C4_SDA_MARK , };static const unsigned int i2c4_b_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (4 ,27 ),RCAR_GP_PIN (4 ,28 ), };static const unsigned int i2c4_b_mux[] = { -SCL4_B_MARK ,SDA4_B_MARK , +I2C4_SCL_B_MARK ,I2C4_SDA_B_MARK , };static const unsigned int i2c4_c_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (7 ,13 ),RCAR_GP_PIN (7 ,14 ), };static const unsigned int i2c4_c_mux[] = { -SCL4_C_MARK ,SDA4_C_MARK , +I2C4_SCL_C_MARK ,I2C4_SDA_C_MARK , }; -/* - I2C7 ------------------------------------------------------------------- */ -static const unsigned int i2c7_pins[] = { +/* - IIC0 ------------------------------------------------------------------- */ +static const unsigned int iic0_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (5 ,15 ),RCAR_GP_PIN (5 ,16 ), }; -static const unsigned int i2c7_mux[] = { -SCL7_MARK ,SDA7_MARK , +static const unsigned int iic0_mux[] = { +IIC0_SCL_MARK ,IIC0_SDA_MARK , }; -static const unsigned int i2c7_b_pins[] = { +static const unsigned int iic0_b_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (2 ,2 ),RCAR_GP_PIN (2 ,3 ), }; -static const unsigned int i2c7_b_mux[] = { -SCL7_B_MARK ,SDA7_B_MARK , +static const unsigned int iic0_b_mux[] = { +IIC0_SCL_B_MARK ,IIC0_SDA_B_MARK , }; -static const unsigned int i2c7_c_pins[] = { +static const unsigned int iic0_c_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (6 ,28 ),RCAR_GP_PIN (6 ,29 ), }; -static const unsigned int i2c7_c_mux[] = { -SCL7_C_MARK ,SDA7_C_MARK , +static const unsigned int iic0_c_mux[] = { +IIC0_SCL_C_MARK ,IIC0_SDA_C_MARK , }; -/* - I2C8 ------------------------------------------------------------------- */ -static const unsigned int i2c8_pins[] = { +/* - IIC1 ------------------------------------------------------------------- */ +static const unsigned int iic1_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (4 ,13 ),RCAR_GP_PIN (4 ,14 ), }; -static const unsigned int i2c8_mux[] = { -SCL8_MARK ,SDA8_MARK , +static const unsigned int iic1_mux[] = { +IIC1_SCL_MARK ,IIC1_SDA_MARK , }; -static const unsigned int i2c8_b_pins[] = { +static const unsigned int iic1_b_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (2 ,4 ),RCAR_GP_PIN (2 ,5 ), }; -static const unsigned int i2c8_b_mux[] = { -SCL8_B_MARK ,SDA8_B_MARK , +static const unsigned int iic1_b_mux[] = { +IIC1_SCL_B_MARK ,IIC1_SDA_B_MARK , }; -static const unsigned int i2c8_c_pins[] = { +static const unsigned int iic1_c_pins[] = {/* SCL, SDA */ RCAR_GP_PIN (6 ,22 ),RCAR_GP_PIN (6 ,23 ), }; -static const unsigned int i2c8_c_mux[] = { -SCL8_C_MARK ,SDA8_C_MARK , +static const unsigned int iic1_c_mux[] = { +IIC1_SCL_C_MARK ,IIC1_SDA_C_MARK , };/* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = {
@@ -4507,12 +4514,12 @@ static const struct sh_pfc_pin_group pinSH_PFC_PIN_GROUP (i2c4),SH_PFC_PIN_GROUP (i2c4_b),SH_PFC_PIN_GROUP (i2c4_c), -SH_PFC_PIN_GROUP (i2c7), -SH_PFC_PIN_GROUP (i2c7_b), -SH_PFC_PIN_GROUP (i2c7_c), -SH_PFC_PIN_GROUP (i2c8), -SH_PFC_PIN_GROUP (i2c8_b), -SH_PFC_PIN_GROUP (i2c8_c), +SH_PFC_PIN_GROUP (iic0), +SH_PFC_PIN_GROUP (iic0_b), +SH_PFC_PIN_GROUP (iic0_c), +SH_PFC_PIN_GROUP (iic1), +SH_PFC_PIN_GROUP (iic1_b), +SH_PFC_PIN_GROUP (iic1_c),SH_PFC_PIN_GROUP (intc_irq0),SH_PFC_PIN_GROUP (intc_irq1), SH_PFC_PIN_GROUP(intc_irq2),
@@ -4914,16 +4921,16 @@ static const char * const i2c4_groups[] "i2c4_c", }; -static const char *const i2c7_groups[] = { -"i2c7" , -"i2c7_b" , -"i2c7_c" , +static const char *const iic0_groups[] = { +"iic0" , +"iic0_b" , +"iic0_c" , }; -static const char *const i2c8_groups[] = { -"i2c8" , -"i2c8_b" , -"i2c8_c" , +static const char *const iic1_groups[] = { +"iic1" , +"iic1_b" , +"iic1_c" , };static const char *const intc_groups[] = {
@@ -5298,8 +5305,8 @@ static const struct sh_pfc_function pinmSH_PFC_FUNCTION (i2c2),SH_PFC_FUNCTION (i2c3),SH_PFC_FUNCTION (i2c4), -SH_PFC_FUNCTION (i2c7), -SH_PFC_FUNCTION (i2c8), +SH_PFC_FUNCTION (iic0), +SH_PFC_FUNCTION (iic1),SH_PFC_FUNCTION (intc),SH_PFC_FUNCTION (mlb), SH_PFC_FUNCTION(mmc),
@@ -5638,7 +5645,7 @@ static const struct pinmux_cfg_reg pinmuFN_A1 ,FN_MSIOF0_SYNC_B ,0 ,0 ,/* IP0_18_16 [3] */ -FN_A0 ,FN_ATAWR0_N_C ,FN_MSIOF0_SCK_B ,FN_SCL0_C ,FN_PWM2_B , +FN_A0 ,FN_ATAWR0_N_C ,FN_MSIOF0_SCK_B ,FN_I2C0_SCL_C ,FN_PWM2_B ,0 ,0 ,0 ,/* IP0_15 [1] */ FN_D15, 0,
@@ -5679,7 +5686,7 @@ static const struct pinmux_cfg_reg pinmuFN_A18 ,FN_DREQ1 ,FN_SCIFA1_RXD_C ,0 ,FN_SCIFB1_RXD_C ,0 ,0 ,0 ,/* IP1_28_26 [3] */ -FN_A17 ,FN_DACK2_B ,0 ,FN_SDA0_C , +FN_A17 ,FN_DACK2_B ,0 ,FN_I2C0_SDA_C ,0 ,0 ,0 ,0 ,/* IP1_25_23 [3] */ FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
@@ -5694,17 +5701,17 @@ static const struct pinmux_cfg_reg pinmuFN_A13 ,FN_ATAG0_N_C ,FN_BPFCLK ,FN_MSIOF1_SS1_D ,0 ,0 ,0 ,0 ,/* IP1_13_11 [3] */ -FN_A12 ,FN_FMCLK ,FN_SDA3_D ,FN_MSIOF1_SCK_D , +FN_A12 ,FN_FMCLK ,FN_I2C3_SDA_D ,FN_MSIOF1_SCK_D ,0 ,0 ,0 ,0 ,/* IP1_10_8 [3] */ -FN_A11 ,FN_MSIOF1_RXD ,FN_SCL3_D ,FN_MSIOF1_RXD_D , +FN_A11 ,FN_MSIOF1_RXD ,FN_I2C3_SCL_D ,FN_MSIOF1_RXD_D ,0 ,0 ,0 ,0 ,/* IP1_7_6 [2] */ FN_A10 ,FN_MSIOF1_TXD ,0 ,FN_MSIOF1_TXD_D ,/* IP1_5_4 [2] */ -FN_A9 ,FN_MSIOF1_SS2 ,FN_SDA0 ,0 , +FN_A9 ,FN_MSIOF1_SS2 ,FN_I2C0_SDA ,0 ,/* IP1_3_2 [2] */ -FN_A8 ,FN_MSIOF1_SS1 ,FN_SCL0 ,0 , +FN_A8 ,FN_MSIOF1_SS1 ,FN_I2C0_SCL ,0 ,/* IP1_1_0 [2] */ FN_A7 ,FN_MSIOF1_SYNC , 0, 0, }
@@ -5722,9 +5729,9 @@ static const struct pinmux_cfg_reg pinmu/* IP2_24_23 [2] */ FN_EX_CS1_N ,FN_MSIOF2_SCK ,0 ,0 ,/* IP2_22_21 [2] */ -FN_CS1_N_A26 ,FN_ATADIR0_N_B ,FN_SDA1 ,0 , +FN_CS1_N_A26 ,FN_ATADIR0_N_B ,FN_I2C1_SDA ,0 ,/* IP2_20_19 [2] */ -FN_CS0_N ,FN_ATAG0_N_B ,FN_SCL1 ,0 , +FN_CS0_N ,FN_ATAG0_N_B ,FN_I2C1_SCL ,0 ,/* IP2_18_16 [3] */ FN_A25 ,FN_DACK2 ,FN_SSL ,FN_DREQ1_C ,FN_RX1 ,FN_SCIFA1_RXD , 0, 0,
@@ -5807,23 +5814,23 @@ static const struct pinmux_cfg_reg pinmuFN_SSI_SDATA2 ,FN_GPS_MAG_B ,FN_TX2_E ,FN_HRTS1_N_E ,0 ,0 ,0 ,0 ,/* IP4_15_13 [3] */ -FN_SSI_WS2 ,FN_SDA2 ,FN_GPS_SIGN_B ,FN_RX2_E , +FN_SSI_WS2 ,FN_I2C2_SDA ,FN_GPS_SIGN_B ,FN_RX2_E ,FN_GLO_Q1_D ,FN_HCTS1_N_E ,0 ,0 ,/* IP4_12_10 [3] */ -FN_SSI_SCK2 ,FN_SCL2 ,FN_GPS_CLK_B ,FN_GLO_Q0_D ,FN_HSCK1_E , +FN_SSI_SCK2 ,FN_I2C2_SCL ,FN_GPS_CLK_B ,FN_GLO_Q0_D ,FN_HSCK1_E ,0 ,0 ,0 ,/* IP4_9_8 [2] */ -FN_SSI_SDATA1 ,FN_SDA1_B ,FN_SDA8_B ,FN_MSIOF2_RXD_C , +FN_SSI_SDATA1 ,FN_I2C1_SDA_B ,FN_IIC1_SDA_B ,FN_MSIOF2_RXD_C ,/* IP4_7_5 [3] */ -FN_SSI_WS1 ,FN_SCL1_B ,FN_SCL8_B ,FN_MSIOF2_TXD_C ,FN_GLO_I1_D , -0 ,0 ,0 , +FN_SSI_WS1 ,FN_I2C1_SCL_B ,FN_IIC1_SCL_B ,FN_MSIOF2_TXD_C , +FN_GLO_I1_D ,0 ,0 ,0 ,/* IP4_4_2 [3] */ -FN_SSI_SCK1 ,FN_SDA0_B ,FN_SDA7_B , +FN_SSI_SCK1 ,FN_I2C0_SDA_B ,FN_IIC0_SDA_B ,FN_MSIOF2_SYNC_C ,FN_GLO_I0_D ,0 ,0 ,0 ,/* IP4_1_0 [2] */ - FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, } + FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, } }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
@@ -5877,15 +5884,15 @@ static const struct pinmux_cfg_reg pinmu0 ,0 ,0 ,/* IP6_23_21 [3] */ FN_IRQ6 ,FN_HSCK1_C ,FN_MSIOF1_SS2_B , -FN_SDA1_E ,FN_MSIOF2_SYNC_E , +FN_I2C1_SDA_E ,FN_MSIOF2_SYNC_E ,0 ,0 ,0 ,/* IP6_20_19 [2] */ -FN_IRQ5 ,FN_HTX1_C ,FN_SCL1_E ,FN_MSIOF2_SCK_E , +FN_IRQ5 ,FN_HTX1_C ,FN_I2C1_SCL_E ,FN_MSIOF2_SCK_E ,/* IP6_18_16 [3] */ -FN_IRQ4 ,FN_HRX1_C ,FN_SDA4_C ,FN_MSIOF2_RXD_E ,FN_INTC_IRQ4_N , -0 ,0 ,0 , +FN_IRQ4 ,FN_HRX1_C ,FN_I2C4_SDA_C ,FN_MSIOF2_RXD_E , +FN_INTC_IRQ4_N ,0 ,0 ,0 ,/* IP6_15_14 [2] */ -FN_IRQ3 ,FN_SCL4_C ,FN_MSIOF2_TXD_E ,FN_INTC_IRQ3_N , +FN_IRQ3 ,FN_I2C4_SCL_C ,FN_MSIOF2_TXD_E ,FN_INTC_IRQ3_N ,/* IP6_13_12 [2] */ FN_IRQ2 ,FN_SCIFB1_TXD_D ,FN_INTC_IRQ2_N ,0 , /* IP6_11_10 [2] */
@@ -5990,7 +5997,7 @@ static const struct pinmux_cfg_reg pinmu {PINMUX_CFG_REG_VAR ("IPSR9" ,0xE6060044 ,32 , 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {/* IP9_31_29 [3] */ -FN_VI0_G0 ,FN_SCL8 ,FN_STP_IVCXO27_0_C ,FN_SCL4 , +FN_VI0_G0 ,FN_IIC1_SCL ,FN_STP_IVCXO27_0_C ,FN_I2C4_SCL ,FN_HCTS2_N ,FN_SCIFB2_CTS_N ,FN_ATAWR1_N ,0 ,/* IP9_28_27 [2] */ FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
@@ -6008,7 +6015,7 @@ static const struct pinmux_cfg_reg pinmuFN_DU1_DISP ,FN_QPOLA ,/* IP9_15_13 [3] */ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE ,FN_QCPV_QDE , -FN_CAN0_RX ,FN_RX3_B ,FN_SDA2_B , +FN_CAN0_RX ,FN_RX3_B ,FN_I2C2_SDA_B ,0 ,0 ,0 ,/* IP9_12 [1] */ FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
@@ -6016,24 +6023,24 @@ static const struct pinmux_cfg_reg pinmuFN_DU1_EXHSYNC_DU1_HSYNC ,FN_QSTH_QHS ,/* IP9_10_8 [3] */ FN_DU1_DOTCLKOUT1 ,FN_QSTVB_QVE ,FN_CAN0_TX , -FN_TX3_B ,FN_SCL2_B ,FN_PWM4 , +FN_TX3_B ,FN_I2C2_SCL_B ,FN_PWM4 ,0 ,0 ,/* IP9_7 [1] */ FN_DU1_DOTCLKOUT0 ,FN_QCLK ,/* IP9_6 [1] */ FN_DU1_DOTCLKIN ,FN_QSTVA_QVS ,/* IP9_5_3 [3] */ -FN_DU1_DB7 ,FN_LCDOUT23 ,FN_SDA3_C , +FN_DU1_DB7 ,FN_LCDOUT23 ,FN_I2C3_SDA_C ,FN_SCIF3_SCK ,FN_SCIFA3_SCK ,0 ,0 ,0 ,/* IP9_2_0 [3] */ -FN_DU1_DB6 ,FN_LCDOUT22 ,FN_SCL3_C ,FN_RX3 ,FN_SCIFA3_RXD , +FN_DU1_DB6 ,FN_LCDOUT22 ,FN_I2C3_SCL_C ,FN_RX3 ,FN_SCIFA3_RXD , 0, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {/* IP10_31_29 [3] */ -FN_VI0_R4 ,FN_VI2_DATA5 ,FN_GLO_SCLK_B ,FN_TX0_C ,FN_SCL1_D , +FN_VI0_R4 ,FN_VI2_DATA5 ,FN_GLO_SCLK_B ,FN_TX0_C ,FN_I2C1_SCL_D ,0 ,0 ,0 ,/* IP10_28_27 [2] */ FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
@@ -6058,22 +6065,22 @@ static const struct pinmux_cfg_reg pinmuFN_HTX2 ,FN_SCIFB2_TXD ,FN_SCIFB0_SCK_D ,0 ,0 ,/* IP10_8_6 [3] */ -FN_VI0_G3 ,FN_VI2_VSYNC_N ,FN_STP_ISEN_0_C ,FN_SDA3_B , +FN_VI0_G3 ,FN_VI2_VSYNC_N ,FN_STP_ISEN_0_C ,FN_I2C3_SDA_B ,FN_HRX2 ,FN_SCIFB2_RXD ,FN_ATACS01_N ,0 ,/* IP10_5_3 [3] */ -FN_VI0_G2 ,FN_VI2_HSYNC_N ,FN_STP_ISD_0_C ,FN_SCL3_B , +FN_VI0_G2 ,FN_VI2_HSYNC_N ,FN_STP_ISD_0_C ,FN_I2C3_SCL_B ,FN_HSCK2 ,FN_SCIFB2_SCK ,FN_ATARD1_N ,0 ,/* IP10_2_0 [3] */ -FN_VI0_G1 ,FN_SDA8 ,FN_STP_ISCLK_0_C ,FN_SDA4 , +FN_VI0_G1 ,FN_IIC1_SDA ,FN_STP_ISCLK_0_C ,FN_I2C4_SDA , FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, } }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 3, 3, 3, 3, 3) {/* IP11_31_30 [2] */ -FN_ETH_CRS_DV ,FN_AVB_LINK ,FN_SDA2_C ,0 , +FN_ETH_CRS_DV ,FN_AVB_LINK ,FN_I2C2_SDA_C ,0 ,/* IP11_29_28 [2] */ -FN_ETH_MDIO ,FN_AVB_RX_CLK ,FN_SCL2_C ,0 , +FN_ETH_MDIO ,FN_AVB_RX_CLK ,FN_I2C2_SCL_C ,0 ,/* IP11_27 [1] */ FN_VI1_DATA7 ,FN_AVB_MDC , /* IP11_26 [1] */
@@ -6106,13 +6113,13 @@ static const struct pinmux_cfg_reg pinmu0 ,0 ,0 ,/* IP11_8_6 [3] */ FN_VI0_R7 ,FN_GLO_RFON_B ,FN_RX1_C ,FN_CAN0_RX_E , -FN_SDA4_B ,FN_HRX1_D ,FN_SCIFB0_RXD_D ,0 , +FN_I2C4_SDA_B ,FN_HRX1_D ,FN_SCIFB0_RXD_D ,0 ,/* IP11_5_3 [3] */ -FN_VI0_R6 ,FN_VI2_DATA7 ,FN_GLO_SS_B ,FN_TX1_C ,FN_SCL4_B , +FN_VI0_R6 ,FN_VI2_DATA7 ,FN_GLO_SS_B ,FN_TX1_C ,FN_I2C4_SCL_B ,0 ,0 ,0 ,/* IP11_2_0 [3] */ -FN_VI0_R5 ,FN_VI2_DATA6 ,FN_GLO_SDATA_B ,FN_RX0_C ,FN_SDA1_D , - 0, 0, 0, } +FN_VI0_R5 ,FN_VI2_DATA6 ,FN_GLO_SDATA_B ,FN_RX0_C , + FN_I2C1_SDA_D, 0, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
@@ -6144,16 +6151,16 @@ static const struct pinmux_cfg_reg pinmu0 ,0 ,0 ,/* IP12_9_7 [3] */ FN_ETH_LINK ,FN_AVB_TXD0 ,FN_CAN0_RX_C , -FN_SDA2_D ,FN_MSIOF1_SCK_E , +FN_I2C2_SDA_D ,FN_MSIOF1_SCK_E ,0 ,0 ,0 ,/* IP12_6_4 [3] */ FN_ETH_RXD1 ,FN_AVB_GTXREFCLK ,FN_CAN0_TX_C , -FN_SCL2_D ,FN_MSIOF1_RXD_E , +FN_I2C2_SCL_D ,FN_MSIOF1_RXD_E ,0 ,0 ,0 ,/* IP12_3_2 [2] */ -FN_ETH_RXD0 ,FN_AVB_PHY_INT ,FN_SDA3 ,FN_SDA7 , +FN_ETH_RXD0 ,FN_AVB_PHY_INT ,FN_I2C3_SDA ,FN_IIC0_SDA ,/* IP12_1_0 [2] */ - FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, } + FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, } }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
@@ -6161,7 +6168,7 @@ static const struct pinmux_cfg_reg pinmu/* IP13_31 [1] */ 0 ,0 ,/* IP13_30_28 [3] */ -FN_SD1_CD ,FN_PWM0 ,FN_TPU_TO0 ,FN_SCL1_C , +FN_SD1_CD ,FN_PWM0 ,FN_TPU_TO0 ,FN_I2C1_SCL_C ,0 ,0 ,0 ,0 ,/* IP13_27 [1] */ FN_SD1_DATA3, FN_IERX_B,
@@ -6210,10 +6217,10 @@ static const struct pinmux_cfg_reg pinmu 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {/* IP14_31_29 [3] */ FN_MSIOF0_SS2 ,FN_MMC_D7 ,FN_ADICHS2 ,FN_RX0_E , -FN_VI1_VSYNC_N_C ,FN_SDA7_C ,FN_VI1_G5_B ,0 , +FN_VI1_VSYNC_N_C ,FN_IIC0_SDA_C ,FN_VI1_G5_B ,0 ,/* IP14_28_26 [3] */ FN_MSIOF0_SS1 ,FN_MMC_D6 ,FN_ADICHS1 ,FN_TX0_E , -FN_VI1_HSYNC_N_C ,FN_SCL7_C ,FN_VI1_G4_B ,0 , +FN_VI1_HSYNC_N_C ,FN_IIC0_SCL_C ,FN_VI1_G4_B ,0 ,/* IP14_25_23 [3] */ FN_MSIOF0_RXD ,FN_ADICHS0 ,0 ,FN_VI1_DATA0_C ,FN_VI1_G3_B , 0, 0, 0,
@@ -6229,10 +6236,10 @@ static const struct pinmux_cfg_reg pinmuFN_VI1_CLK_C ,FN_VI1_G0_B ,0 ,0 ,/* IP14_13_11 [3] */ -FN_SD2_WP ,FN_MMC_D5 ,FN_SDA8_C ,FN_RX5_B ,FN_SCIFA5_RXD_C , +FN_SD2_WP ,FN_MMC_D5 ,FN_IIC1_SDA_C ,FN_RX5_B ,FN_SCIFA5_RXD_C ,0 ,0 ,0 ,/* IP14_10_8 [3] */ -FN_SD2_CD ,FN_MMC_D4 ,FN_SCL8_C ,FN_TX5_B ,FN_SCIFA5_TXD_C , +FN_SD2_CD ,FN_MMC_D4 ,FN_IIC1_SCL_C ,FN_TX5_B ,FN_SCIFA5_TXD_C ,0 ,0 ,0 ,/* IP14_7 [1] */ FN_SD2_DATA3, FN_MMC_D3,
@@ -6247,7 +6254,7 @@ static const struct pinmux_cfg_reg pinmu/* IP14_2 [1] */ FN_SD2_CLK ,FN_MMC_CLK ,/* IP14_1_0 [2] */ - FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, } + FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, } }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
@@ -6424,14 +6431,14 @@ static const struct pinmux_cfg_reg pinmu/* SEL_CANCLK [2] */ FN_SEL_CANCLK_0 ,FN_SEL_CANCLK_1 ,FN_SEL_CANCLK_2 ,FN_SEL_CANCLK_3 , -/* SEL_IIC8 [2] */ -FN_SEL_IIC8_0 ,FN_SEL_IIC8_1 ,FN_SEL_IIC8_2 ,0 , -/* SEL_IIC7 [2] */ -FN_SEL_IIC7_0 ,FN_SEL_IIC7_1 ,FN_SEL_IIC7_2 ,0 , -/* SEL_IIC4 [2] */ -FN_SEL_IIC4_0 ,FN_SEL_IIC4_1 ,FN_SEL_IIC4_2 ,0 , -/* SEL_IIC3 [2] */ -FN_SEL_IIC3_0 ,FN_SEL_IIC3_1 ,FN_SEL_IIC3_2 ,FN_SEL_IIC3_3 , +/* SEL_IIC1 [2] */ +FN_SEL_IIC1_0 ,FN_SEL_IIC1_1 ,FN_SEL_IIC1_2 ,0 , +/* SEL_IIC0 [2] */ +FN_SEL_IIC0_0 ,FN_SEL_IIC0_1 ,FN_SEL_IIC0_2 ,0 , +/* SEL_I2C4 [2] */ +FN_SEL_I2C4_0 ,FN_SEL_I2C4_1 ,FN_SEL_I2C4_2 ,0 , +/* SEL_I2C3 [2] */ +FN_SEL_I2C3_0 ,FN_SEL_I2C3_1 ,FN_SEL_I2C3_2 ,FN_SEL_I2C3_3 ,/* SEL_SCIF3 [2] */ FN_SEL_SCIF3_0 ,FN_SEL_SCIF3_1 ,FN_SEL_SCIF3_2 ,FN_SEL_SCIF3_3 , /* SEL_IEB [2] */
@@ -6442,14 +6449,14 @@ static const struct pinmux_cfg_reg pinmuFN_SEL_SCIF5_0 ,FN_SEL_SCIF5_1 ,/* RESERVED [2] */ 0 ,0 ,0 ,0 , -/* SEL_IIC2 [2] */ -FN_SEL_IIC2_0 ,FN_SEL_IIC2_1 ,FN_SEL_IIC2_2 ,FN_SEL_IIC2_3 , -/* SEL_IIC1 [3] */ -FN_SEL_IIC1_0 ,FN_SEL_IIC1_1 ,FN_SEL_IIC1_2 ,FN_SEL_IIC1_3 , -FN_SEL_IIC1_4 , +/* SEL_I2C2 [2] */ +FN_SEL_I2C2_0 ,FN_SEL_I2C2_1 ,FN_SEL_I2C2_2 ,FN_SEL_I2C2_3 , +/* SEL_I2C1 [3] */ +FN_SEL_I2C1_0 ,FN_SEL_I2C1_1 ,FN_SEL_I2C1_2 ,FN_SEL_I2C1_3 , +FN_SEL_I2C1_4 ,0 ,0 ,0 , -/* SEL_IIC0 [2] */ -FN_SEL_IIC0_0 ,FN_SEL_IIC0_1 ,FN_SEL_IIC0_2 ,0 , +/* SEL_I2C0 [2] */ +FN_SEL_I2C0_0 ,FN_SEL_I2C0_1 ,FN_SEL_I2C0_2 ,0 ,/* RESERVED [2] */ 0 ,0 ,0 ,0 , /* RESERVED [2] */
Oops, sorry for the dupe -- I was checking something...