Skip to contentSkip to conversation

soc: imx: gpc: add defines for domain index

PATCH New Lucas Stach 2 participants 4 messages Apr 5, 2017 – Apr 7, 2017

Subsystems (2)
Device tree bindings Arm i.MX and Layerscape
lore
Share & tools
lore

Lucas Stach

author
#0 lore raw

PATCH v2 1/3 soc: imx: gpc: add defines for domain index

Makes referencing a specfic domain in the driver code less error prone.

Signed-off-by Lucas Stach <[email protected]>

---
v2: new patch

---
 drivers/soc/imx/gpc.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)
drivers/soc/imx/gpc.c +8 -4
index 4294287e5f6c..d4ebb325b558 100644
@@ -235,6 +235,10 @@ static struct platform_driver imx_pgc_power_domain_driver = {
 };
 builtin_platform_driver(imx_pgc_power_domain_driver)
 
+#define GPC_PGC_DOMAIN_ARM	0
+#define GPC_PGC_DOMAIN_PU	1
+#define GPC_PGC_DOMAIN_DISPLAY	2
+
 static struct genpd_power_state imx6_pm_domain_pu_state = {
 	.power_off_latency_ns = 25000,
 	.power_on_latency_ns = 2000000,

@@ -340,7 +344,7 @@ static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap,
 genpd_err:
 	for (i = 0; i < num_domains; i++)
 		pm_genpd_remove(&imx_gpc_domains[i].base);
-	imx_pgc_put_clocks(&imx_gpc_domains[1]);
+	imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
 clk_err:
 	return ret;
 }

@@ -441,12 +445,12 @@ static int imx_gpc_remove(struct platform_device *pdev)
 	if (!of_get_child_by_name(pdev->dev.of_node, "pgc")) {
 		of_genpd_del_provider(pdev->dev.of_node);
 
-		ret = pm_genpd_remove(&imx_gpc_domains[1].base);
+		ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
 		if (ret)
 			return ret;
-		imx_pgc_put_clocks(&imx_gpc_domains[1]);
+		imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
 
-		ret = pm_genpd_remove(&imx_gpc_domains[0].base);
+		ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base);
 		if (ret)
 			return ret;
 	}
Signature · 1 line
2.11.0
author
#1 lore raw

PATCH v2 2/3 dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible

While the GPC on i.MX6QP is mostly comptible to the i.MX6Q one, the QuadPlus requires special workarounds for hardware erratum ERR009619.

Signed-off-by Lucas Stach <[email protected]>
Acked-by Rob Herring <[email protected]>
---
 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/power/fsl,imx-gpc.txt +4 -1
index 416e12c6755a..181d2cc6f054 100644
@@ -5,7 +5,10 @@ The i.MX6 General Power Control (GPC) block contains DVFS load tracking
 counters and Power Gating Control (PGC).
 
 Required properties:
-- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
+- compatible: Should be one of the following:
+  - fsl,imx6q-gpc
+  - fsl,imx6qp-gpc
+  - fsl,imx6sl-gpc
 - reg: should be register base and length as documented in the
   datasheet
 - interrupts: Should contain one interrupt specifier for the GPC interrupt
Signature · 1 line
2.11.0
author
#2 lore raw

PATCH v2 3/3 soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver

In reply to Lucas Stach

On i.MX6QP, due to hardware erratum ERR009619, the PRE clocks may be stalled during the power up sequencing of the PU power domain. As this may lead to a complete loss of display output, the recommended workaround is to keep the PU domain enabled during normal system operation.

Implement this by rejecting the domain power down request on the affected SoC.

Signed-off-by Lucas Stach <[email protected]>

---
v2:
- use domain index define
- switch to domain flags
- switch to positive logic

---
 drivers/soc/imx/gpc.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
drivers/soc/imx/gpc.c +20 -0
index d4ebb325b558..47e7aa963dbb 100644
@@ -36,6 +36,8 @@
 
 #define GPC_CLK_MAX		6
 
+#define PGC_DOMAIN_FLAG_NO_PD		BIT(0)
+
 struct imx_pm_domain {
 	struct generic_pm_domain base;
 	struct regmap *regmap;

@@ -45,6 +47,7 @@ struct imx_pm_domain {
 	unsigned int reg_offs;
 	signed char cntr_pdn_bit;
 	unsigned int ipg_rate_mhz;
+	unsigned int flags;
 };
 
 static inline struct imx_pm_domain *

@@ -59,6 +62,9 @@ static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
 	int iso, iso2sw;
 	u32 val;
 
+	if (pd->flags & PGC_DOMAIN_FLAG_NO_PD)
+		return -EBUSY;
+
 	/* Read ISO and ISO2SW power down delays */
 	regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
 	iso = val & 0x3f;

@@ -272,18 +278,27 @@ static struct imx_pm_domain imx_gpc_domains[] = {
 
 struct imx_gpc_dt_data {
 	int num_domains;
+	bool err009619_present;
 };
 
 static const struct imx_gpc_dt_data imx6q_dt_data = {
 	.num_domains = 2,
+	.err009619_present = false,
+};
+
+static const struct imx_gpc_dt_data imx6qp_dt_data = {
+	.num_domains = 2,
+	.err009619_present = true,
 };
 
 static const struct imx_gpc_dt_data imx6sl_dt_data = {
 	.num_domains = 3,
+	.err009619_present = false,
 };
 
 static const struct of_device_id imx_gpc_dt_ids[] = {
 	{ .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
+	{ .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
 	{ .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
 	{ }
 };

@@ -381,6 +396,11 @@ static int imx_gpc_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	/* Disable PU power down in normal operation if ERR009619 is present */
+	if (of_id_data->err009619_present)
+		imx_gpc_domains[GPC_PGC_DOMAIN_PU].flags |=
+				PGC_DOMAIN_FLAG_NO_PD;
+
 	if (!pgc_node) {
 		ret = imx_gpc_old_dt_init(&pdev->dev, regmap,
 					  of_id_data->num_domains);
Signature · 1 line
2.11.0