4.9.22-stable review
Subsystems (2)
Greg Kroah-Hartman
maintainercover 4.9.22-stable review
This is the start of the stable review cycle for the 4.9.22 release. There are 152 patches in this series, all will be posted as a response to this one. If anyone has any issues with these being applied, please let me know.
Responses should be made by Wed Apr 12 16:41:34 UTC 2017. Anything received after that time might be too late.
The whole patch series can be found in one patch at:
kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.9.22-rc1.gz
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-4.9.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <[email protected]>
Linux 4.9.22-rc1
Matjaz Hegedic <[email protected]>
x86/reboot/quirks: Fix typo in ASUS EeeBook X205TA reboot quirk
Tobias Jakobi <[email protected]>
usb-storage: Add ignore-residue quirk for Initio INIC-3619
Matjaz Hegedic <[email protected]>
x86/reboot/quirks: Add ASUS EeeBook X205TA/W reboot quirk
Matjaz Hegedic <[email protected]>
x86/reboot/quirks: Add ASUS EeeBook X205TA reboot quirk
Len Brown <[email protected]>
tools/power turbostat: dump Atom P-states correctly
Len Brown <[email protected]>
tools/power turbostat: decode Baytrail CC6 and MC6 demotion configuration
João Paulo Rechi Vita <[email protected]>
platform/x86: asus-wmi: Detect quirk_no_rfkill from the DSDT
Kai-Chuan Hsieh <[email protected]>
platform/x86: asus-wmi: Set specified XUSB2PR value for X550LB
Krzysztof Kozlowski <[email protected]>
watchdog: s3c2410: Fix infinite interrupt in soft mode
Sinan Kaya <[email protected]>
PCI: Add ACS quirk for Qualcomm QDF2400 and QDF2432
Andy Shevchenko <[email protected]>
PCI: Sort the list of devices with D3 delay quirk by ID
yangbo lu <[email protected]>
mmc: sdhci-of-esdhc: remove default broken-cd for ARM
Dongdong Liu <[email protected]>
PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports
Jon Mason <[email protected]>
PCI: Add Broadcom Northstar2 PAXC quirk for device class and MPSS
Will Deacon <[email protected]>
ARM: smccc: Update HVC comment to describe new quirk parameter
Baoyou Xie <[email protected]>
drm/msm/adreno: move function declarations to header file
Andy Gross <[email protected]>
firmware: qcom: scm: Fix interrupted SCM calls
Andy Gross <[email protected]>
arm: kernel: Add SMC structure parameter
Ping Cheng <[email protected]>
HID: wacom: don't apply generic settings to old devices
Mylène Josserand <[email protected]>
ASoC: sun4i-i2s: Add quirks to handle a31 compatible
Alexandre Bailon <[email protected]>
usb: musb: da8xx: Fix host mode suspend
Zhang Rui <[email protected]>
ACPI: save NVS memory for Lenovo G50-45
Pierre-Louis Bossart <[email protected]>
ASoC: Intel: cht_bsw_rt5645: add Baytrail MCLK support
Pierre-Louis Bossart <[email protected]>
ASoC: Intel: cht_bsw_rt5645: harden ACPI device detection
Pierre-Louis Bossart <[email protected]>
ASoC: Intel: Baytrail: add quirk for Lenovo Thinkpad 10
Pierre-Louis Bossart <[email protected]>
ASoC: codecs: rt5670: add quirk for Lenovo Thinkpad 10
Takashi Iwai <[email protected]>
ASoC: rt5670: Add missing 10EC5072 ACPI ID
Lv Zheng <[email protected]>
ACPI / button: Change default behavior to lid_init_state=open
Bartosz Golaszewski <[email protected]>
sata: ahci-da850: implement a workaround for the softreset quirk
Sean Young <[email protected]>
rx51: broken build
Dan Carpenter <[email protected]>
PCI: xgene: Fix double free on init error
Alex Williamson <[email protected]>
PCI: Add ACS quirk for Intel Union Point
Patrice Chotard <[email protected]>
ARM: dts: STiH407-family: set snps,dis_u3_susphy_quirk
Daniel Vetter <[email protected]>
drm/mga: remove device_is_agp callback
Felipe Balbi <[email protected]>
usb: dwc3: host: pass quirk-broken-port-ped property for known broken revisions
Felipe Balbi <[email protected]>
usb: host: xhci-plat: enable BROKEN_PED quirk if platform requested
Felipe Balbi <[email protected]>
usb: xhci: add quirk flag for broken PED bits
Kevin Hilman <[email protected]>
ARM: davinci: add skeleton for pdata-quirks
Kevin Hilman <[email protected]>
ARM: davinci: PM: support da8xx DT platforms
Lendacky, Thomas <[email protected]>
amd-xgbe: Prepare for working with more than one type of phy
Geert Uytterhoeven <[email protected]>
Input: gpio_keys - add support for GPIO descriptors
Vignesh R <[email protected]>
serial: 8250_omap: Add OMAP_DMA_TX_KICK quirk for AM437x
Stephen Boyd <[email protected]>
usb: chipidea: msm: Rely on core to override AHBBURST
Tony Lindgren <[email protected]>
ARM: OMAP2+: Fix init for multiple quirks for the same SoC
[email protected] <[email protected]>
scsi: ufs: issue link starup 2 times if device isn't active
Zang Leigang <[email protected]>
scsi: ufs: introduce a new ufshcd_statea UFSHCD_STATE_EH_SCHEDULED
youling257 <[email protected]>
ASoC: Intel: bytcr_rt5640: quirks for Insyde devices
Paulo Zanoni <[email protected]>
drm/i915: actually drive the BDW reserved IDs
Paulo Zanoni <[email protected]>
drm/i915: more .is_mobile cleanups for BDW
Paulo Zanoni <[email protected]>
drm/i915: fix INTEL_BDW_IDS definition
Jani Nikula <[email protected]>
drm/edid: constify edid quirk list
Marcel Hasler <[email protected]>
HID: usbhid: Add quirk for Mayflash/Dragonrise DolphinBar.
Alex Wood <[email protected]>
HID: usbhid: Add quirk for the Futaba TOSD-5711BB VFD
Lv Zheng <[email protected]>
ACPI / sysfs: Provide quirk mechanism to prevent GPE flooding
Keith Busch <[email protected]>
nvme: simplify stripe quirk
Yuta Kobayashi <[email protected]>
HID: multitouch: enable the Surface 4 Type Cover Pro (JP) to report multitouch data
Daniel Keller <[email protected]>
HID: microsoft: Add Surface 4 type cover pro 4 not JP versions
Brendan McGrath <[email protected]>
HID: asus: Fix keyboard support
Brendan McGrath <[email protected]>
HID: asus: Add i2c touchpad support
Lee, Chun-Yi <[email protected]>
platform/x86: acer-wmi: Only supports AMW0_GUID1 on acer family
Nobutaka Okabe <[email protected]>
ALSA: usb-audio: Add native DSD support for TEAC 501/503 DAC
Bjorn Helgaas <[email protected]>
PCI: Expand "VPD access disabled" quirk message
Alberto Aguirre <[email protected]>
ALSA: usb-audio: add implicit fb quirk for Axe-Fx II
Subhash Jadavani <[email protected]>
scsi: ufs: add quirk to increase host PA_SaveConfigTime
Bjorn Helgaas <[email protected]>
PCI: Explain ARM64 ACPI/MCFG quirk Kconfig and build strategy
Duc Dang <[email protected]>
PCI: Add MCFG quirks for X-Gene host controller
Tomasz Nowicki <[email protected]>
PCI: Add MCFG quirks for Cavium ThunderX pass1.x host controller
Tomasz Nowicki <[email protected]>
PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller
Bjorn Helgaas <[email protected]>
PCI: thunder-pem: Factor out resource lookup
Dongdong Liu <[email protected]>
PCI: Add MCFG quirks for HiSilicon Hip05/06/07 host controllers
Christopher Covington <[email protected]>
PCI: Add MCFG quirks for Qualcomm QDF2432 host controller
Tomasz Nowicki <[email protected]>
PCI/ACPI: Check for platform-specific MCFG quirks
Tomasz Nowicki <[email protected]>
PCI/ACPI: Extend pci_mcfg_lookup() to return ECAM config accessors
Bjorn Helgaas <[email protected]>
arm64: PCI: Search ACPI namespace to ensure ECAM space is reserved
Bjorn Helgaas <[email protected]>
arm64: PCI: Add local struct device pointers
Tomasz Nowicki <[email protected]>
arm64: PCI: Manage controller-specific data on per-controller basis
Andy Shevchenko <[email protected]>
x86/intel_idle: Add CPU model 0x4a (Atom Z34xx series)
Chuck Lever <[email protected]>
svcauth_gss: Close connection when dropping an incoming message
Subhash Jadavani <[email protected]>
scsi: ufs: ensure that host pa_tactivate is higher than device
Ritesh Harjani <[email protected]>
mmc: sdhci-msm: Enable few quirks
Benjamin Tissoires <[email protected]>
HID: multitouch: do not retrieve all reports for all devices
Benjamin Tissoires <[email protected]>
HID: multitouch: enable the Surface 3 Type Cover to report multitouch data
Benjamin Tissoires <[email protected]>
HID: sensor-hub: add quirk for Microchip MM7150
Benjamin Tissoires <[email protected]>
HID: sensor-hub add quirk for Microsoft Surface 3
Kiwoong Kim <[email protected]>
scsi: ufs: introduce UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk
Brian Norris <[email protected]>
clocksource/drivers/arm_arch_timer: Don't assume clock runs in suspend
Bjorn Helgaas <[email protected]>
net/mlx4_core: Use device ID defines
John Garry <[email protected]>
arm64: dts: hisi: fix hip06 sas am-max-trans quirk
Pierre-Louis Bossart <[email protected]>
ASoC: Intel: bytct_rt5640: change default capture settings
Janusz Dziedzic <[email protected]>
usb: dwc3: gadget: delay unmap of bounced requests
HungNien Chen <[email protected]>
HID: i2c-hid: add a simple quirk to fix device defects
Marcel Hasler <[email protected]>
HID: usbhid: Add quirks for Mayflash/Dragonrise GameCube and PS3 adapters
Vladimir Zapolskiy <[email protected]>
clk: lpc32xx: add a quirk for PWM and MS clock dividers
Chen-Yu Tsai <[email protected]>
drm/sun4i: Add compatible string for A31/A31s TCON (timing controller)
Chen-Yu Tsai <[email protected]>
drm/sun4i: Add compatible strings for A31/A31s display pipelines
Chen-Yu Tsai <[email protected]>
drm/sun4i: tcon: Move SoC specific quirks to a DT matched data structure
Jason A. Donenfeld <[email protected]>
random: use chacha20 for get_random_int/long
Chris Salls <[email protected]>
mm/mempolicy.c: fix error handling in set_mempolicy and mbind.
Johan Hovold <[email protected]>
Documentation: stable-kernel-rules: fix stable-tag format
Huacai Chen <[email protected]>
MIPS: c-r4k: Fix Loongson-3's vcache/scache waysize calculation
Huacai Chen <[email protected]>
MIPS: Flush wrong invalid FTLB entry for huge page
Huacai Chen <[email protected]>
MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2
Huacai Chen <[email protected]>
MIPS: Check TLB before handle_ri_rdhwr() for Loongson-3
Hauke Mehrtens <[email protected]>
MIPS: Lantiq: fix missing xbar kernel panic
Paul Burton <[email protected]>
MIPS: End spinlocks with .insn
John Crispin <[email protected]>
MIPS: ralink: Fix typos in rt3883 pinctrl
James Hogan <[email protected]>
MIPS: Force o32 fp64 support on 32bit MIPS64r6 kernels
Heiko Carstens <[email protected]>
s390/uaccess: get_user() should zero on failure (again)
Marcelo Henrique Cerri <[email protected]>
s390/decompressor: fix initrd corruption caused by bss clear
Max Filippov <[email protected]>
xtensa: make __pa work with uncached KSEG addresses
Tobias Klauser <[email protected]>
nios2: reserve boot memory for device tree
Dmitry Bilunov <[email protected]>
dm raid: fix NULL pointer dereference for raid1 without bitmap
Michael Ellerman <[email protected]>
powerpc/crypto/crc32c-vpmsum: Fix missing preempt_disable()
Paul Mackerras <[email protected]>
powerpc: Don't try to fix up misaligned load-with-reservation instructions
Oliver O'Halloran <[email protected]>
powerpc/64: Fix flush_(d|i)cache_range() called from modules
Frederic Barrat <[email protected]>
powerpc/mm: Add missing global TLB invalidate if cxl is active
Benjamin Herrenschmidt <[email protected]>
powerpc: Disable HFSCR[TM] if TM is not supported
James Hogan <[email protected]>
metag/usercopy: Add missing fixups
James Hogan <[email protected]>
metag/usercopy: Fix src fixup in from user rapf loops
James Hogan <[email protected]>
metag/usercopy: Set flags before ADDZ
James Hogan <[email protected]>
metag/usercopy: Zero rest of buffer from copy_from_user
James Hogan <[email protected]>
metag/usercopy: Add early abort to copy_to_user
James Hogan <[email protected]>
metag/usercopy: Fix alignment error checking
James Hogan <[email protected]>
metag/usercopy: Drop unused macros
Arend Van Spriel <[email protected]>
brcmfmac: use local iftype avoiding use-after-free of virtual interface
Johannes Berg <[email protected]>
mac80211: unconditionally start new netdev queues with iTXQ support
Wei Yongjun <[email protected]>
ring-buffer: Fix return value check in test_ringbuffer()
Calvin Owens <[email protected]>
xfs: Honor FALLOC_FL_KEEP_SIZE when punching ends of files
Martin Brandenburg <[email protected]>
orangefs: move features validation to fix filesystem hang
Arnd Bergmann <[email protected]>
Kbuild: use cc-disable-warning consistently for maybe-uninitialized
Dmitry Torokhov <[email protected]>
ACPI / gpio: do not fall back to parsing _CRS when we get a deferral
Sami Tolvanen <[email protected]>
dm verity fec: fix bufio leaks
Sami Tolvanen <[email protected]>
dm verity fec: limit error correction recursion
[email protected] <[email protected]>
ptrace: fix PTRACE_LISTEN race corrupting task->state
Alexander Polakov <[email protected]>
mm/page_alloc.c: fix print order in show_free_areas()
Jan-Marek Glogowski <[email protected]>
Reset TreeId to zero on SMB2 TREE_CONNECT
Arend Van Spriel <[email protected]>
cfg80211: check rdev resume callback only for registered wiphy
Victor Kamensky <[email protected]>
arm64: mm: unaligned access by user-land should be received as SIGBUS
Quentin Schulz <[email protected]>
iio: bmg160: reset chip when probing
Suzuki K Poulose <[email protected]>
kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd
Marc Zyngier <[email protected]>
arm/arm64: KVM: Take mmap_sem in kvm_arch_prepare_memory_region
Marc Zyngier <[email protected]>
arm/arm64: KVM: Take mmap_sem in stage2_unmap_vm
Shuxiao Zhang <[email protected]>
staging: android: ashmem: lseek failed due to no FMODE_LSEEK.
NeilBrown <[email protected]>
sysfs: be careful of error returns from ops->show()
Li Qiang <[email protected]>
drm/vmwgfx: fix integer overflow in vmw_surface_define_ioctl()
Thomas Hellstrom <[email protected]>
drm/vmwgfx: Remove getparam error message
Thomas Hellstrom <[email protected]>
drm/ttm, drm/vmwgfx: Relax permission checking when opening surfaces
Murray McAllister <[email protected]>
drm/vmwgfx: avoid calling vzalloc with a 0 size in vmw_get_cap_3d_ioctl()
Murray McAllister <[email protected]>
drm/vmwgfx: NULL pointer dereference in vmw_surface_define_ioctl()
Thomas Hellstrom <[email protected]>
drm/vmwgfx: Type-check lookups of fence objects
Sudip Mukherjee <[email protected]>
ppdev: fix registering same device name
Sudip Mukherjee <[email protected]>
ppdev: check before attaching port
-------------
Diffstat:
.../devicetree/bindings/arm/arch_timer.txt | 5 + .../bindings/display/sunxi/sun4i-drm.txt | 8 +- Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 + .../devicetree/bindings/watchdog/samsung-wdt.txt | 9 +- Documentation/kernel-parameters.txt | 10 + Documentation/stable_kernel_rules.txt | 2 +- Makefile | 6 +- arch/arm/boot/dts/stih407-family.dtsi | 1 + arch/arm/kernel/armksyms.c | 4 +- arch/arm/kernel/smccc-call.S | 14 +- arch/arm/kvm/mmu.c | 23 +- arch/arm/mach-davinci/Makefile | 2 +- arch/arm/mach-davinci/da8xx-dt.c | 2 + arch/arm/mach-davinci/include/mach/common.h | 2 + arch/arm/mach-davinci/pdata-quirks.c | 39 + arch/arm/mach-omap2/pdata-quirks.c | 3 +- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- arch/arm64/kernel/arm64ksyms.c | 4 +- arch/arm64/kernel/asm-offsets.c | 7 +- arch/arm64/kernel/pci.c | 53 +- arch/arm64/kernel/smccc-call.S | 23 +- arch/arm64/mm/fault.c | 42 +- arch/metag/include/asm/uaccess.h | 15 +- arch/metag/lib/usercopy.c | 312 +++----- arch/mips/Kconfig | 2 +- arch/mips/include/asm/spinlock.h | 8 +- arch/mips/kernel/cpu-probe.c | 2 +- arch/mips/kernel/genex.S | 4 +- arch/mips/kernel/traps.c | 17 +- arch/mips/lantiq/xway/sysctrl.c | 2 +- arch/mips/mm/c-r4k.c | 2 + arch/mips/mm/tlbex.c | 25 +- arch/mips/ralink/rt3883.c | 4 +- arch/nios2/kernel/prom.c | 7 + arch/nios2/kernel/setup.c | 3 + arch/powerpc/crypto/crc32c-vpmsum_glue.c | 3 + arch/powerpc/kernel/align.c | 27 +- arch/powerpc/kernel/misc_64.S | 4 +- arch/powerpc/kernel/setup_64.c | 9 + arch/powerpc/mm/hash_native_64.c | 7 +- arch/s390/boot/compressed/misc.c | 35 +- arch/s390/include/asm/uaccess.h | 2 +- arch/x86/kernel/reboot.c | 16 + arch/xtensa/include/asm/page.h | 13 + drivers/acpi/button.c | 2 +- drivers/acpi/internal.h | 1 + drivers/acpi/pci_mcfg.c | 190 ++++- drivers/acpi/scan.c | 1 + drivers/acpi/sleep.c | 19 + drivers/acpi/sysfs.c | 56 ++ drivers/ata/ahci_da850.c | 33 +- drivers/char/ppdev.c | 33 +- drivers/char/random.c | 84 ++- drivers/clk/nxp/clk-lpc32xx.c | 32 +- drivers/clocksource/arm_arch_timer.c | 9 +- drivers/firmware/qcom_scm-64.c | 13 +- drivers/gpio/gpiolib-acpi.c | 4 +- drivers/gpu/drm/drm_edid.c | 6 +- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/mga/mga_dma.c | 20 +- drivers/gpu/drm/mga/mga_drv.c | 37 - drivers/gpu/drm/msm/adreno/adreno_device.c | 3 - drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 + drivers/gpu/drm/sun4i/sun4i_backend.c | 1 + drivers/gpu/drm/sun4i/sun4i_drv.c | 5 + drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +- drivers/gpu/drm/sun4i/sun4i_tcon.h | 11 +- drivers/gpu/drm/ttm/ttm_object.c | 10 +- drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 79 +- drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c | 4 +- drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 4 +- drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 31 +- drivers/hid/Kconfig | 2 +- drivers/hid/hid-asus.c | 304 +++++++- drivers/hid/hid-core.c | 9 +- drivers/hid/hid-ids.h | 19 +- drivers/hid/hid-microsoft.c | 4 +- drivers/hid/hid-multitouch.c | 80 +- drivers/hid/hid-sensor-hub.c | 6 + drivers/hid/i2c-hid/i2c-hid.c | 57 ++ drivers/hid/usbhid/hid-quirks.c | 8 +- drivers/hid/wacom_wac.c | 3 + drivers/idle/intel_idle.c | 49 ++ drivers/iio/gyro/bmg160_core.c | 12 + drivers/input/keyboard/gpio_keys.c | 37 +- drivers/md/dm-raid.c | 2 +- drivers/md/dm-verity-fec.c | 18 +- drivers/md/dm-verity-fec.h | 4 + drivers/mmc/host/sdhci-msm.c | 4 +- drivers/mmc/host/sdhci-of-esdhc.c | 18 +- drivers/net/ethernet/amd/xgbe/Makefile | 3 +- drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 58 +- drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 6 +- drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c | 19 +- drivers/net/ethernet/amd/xgbe/xgbe-main.c | 214 ++---- drivers/net/ethernet/amd/xgbe/xgbe-mdio.c | 549 +++++--------- drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c | 821 +++++++++++++++++++++ drivers/net/ethernet/amd/xgbe/xgbe.h | 130 ++-- drivers/net/ethernet/mellanox/mlx4/main.c | 84 ++- .../net/wireless/broadcom/brcm80211/brcmfmac/p2p.c | 8 +- drivers/nvme/host/core.c | 17 +- drivers/nvme/host/nvme.h | 1 - drivers/pci/ecam.c | 12 + drivers/pci/host/Kconfig | 10 +- drivers/pci/host/Makefile | 19 +- drivers/pci/host/pci-thunder-ecam.c | 9 +- drivers/pci/host/pci-thunder-pem.c | 94 ++- drivers/pci/host/pci-xgene.c | 123 ++- drivers/pci/host/pcie-hisi.c | 101 +++ drivers/pci/quirks.c | 101 ++- drivers/platform/x86/acer-wmi.c | 56 ++ drivers/platform/x86/asus-nb-wmi.c | 13 + drivers/platform/x86/asus-wmi.c | 52 +- drivers/platform/x86/asus-wmi.h | 1 + drivers/scsi/ufs/ufs-qcom.c | 30 + drivers/scsi/ufs/ufs-qcom.h | 1 + drivers/scsi/ufs/ufs_quirks.h | 35 +- drivers/scsi/ufs/ufshcd.c | 154 +++- drivers/scsi/ufs/ufshcd.h | 15 + drivers/scsi/ufs/unipro.h | 4 + drivers/staging/android/ashmem.c | 1 + drivers/tty/serial/8250/8250_omap.c | 9 +- drivers/usb/chipidea/ci_hdrc_msm.c | 4 +- drivers/usb/dwc3/gadget.c | 21 +- drivers/usb/dwc3/host.c | 21 +- drivers/usb/host/xhci-hub.c | 6 + drivers/usb/host/xhci-plat.c | 3 + drivers/usb/host/xhci.h | 3 + drivers/usb/musb/da8xx.c | 2 +- drivers/usb/storage/unusual_devs.h | 14 + drivers/watchdog/s3c2410_wdt.c | 21 +- fs/cifs/smb2pdu.c | 4 + fs/orangefs/super.c | 9 +- fs/sysfs/file.c | 6 +- fs/xfs/xfs_bmap_util.c | 10 +- include/drm/i915_pciids.h | 11 +- include/drm/ttm/ttm_object.h | 5 +- include/linux/arm-smccc.h | 52 +- include/linux/pci-acpi.h | 4 +- include/linux/pci-ecam.h | 9 + include/linux/pci_ids.h | 2 + include/linux/random.h | 1 - init/main.c | 1 - kernel/ptrace.c | 14 +- kernel/trace/ring_buffer.c | 8 +- mm/mempolicy.c | 20 +- mm/page_alloc.c | 2 +- net/mac80211/iface.c | 3 +- net/sunrpc/auth_gss/svcauth_gss.c | 2 +- net/sunrpc/svc.c | 14 +- net/wireless/sysfs.c | 10 +- sound/soc/codecs/rt5670.c | 2 + sound/soc/intel/atom/sst/sst_acpi.c | 37 +- sound/soc/intel/boards/bytcr_rt5640.c | 21 +- sound/soc/intel/boards/cht_bsw_rt5645.c | 98 ++- sound/soc/sunxi/sun4i-i2s.c | 57 +- sound/usb/pcm.c | 10 + sound/usb/quirks.c | 38 + tools/power/x86/turbostat/turbostat.c | 103 +++ 159 files changed, 4059 insertions(+), 1491 deletions(-)
Greg Kroah-Hartman
maintainerPATCH 1/152 ppdev: check before attaching port
4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sudip Mukherjee <[email protected]>
commit dd5c472a60e43549d789a17a8444513eec64bd7e upstream.
After parport starts using the device model, all pardevice drivers should decide in their match_port callback function if they want to attach with that particulatr port. ppdev has been converted to use the new parport device-model code but pp_attach() tried to attach with all the ports.
Create a new array of pointer and use that to remember the ports we have attached. And use that information to skip attaching ports which we have already attached.
--- drivers/char/ppdev.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-)
drivers/char/ppdev.c +21 -2
@@ -86,6 +86,9 @@ struct pp_struct {long default_inactivity; }; +/* should we use PARDEVICE_MAX here? */ +static struct device *devices[PARPORT_MAX ]; +/* pp_struct.flags bitfields */ #define PP_CLAIMED (1<<0)#define PP_EXCL (1<<1)
@@ -789,13 +792,29 @@ static const struct file_operations pp_fstatic void pp_attach (struct parport *port) { -device_create (ppdev_class, port->dev,MKDEV (PP_MAJOR , port->number), -NULL ,"parport%d" , port->number); +struct device *ret; + +if (devices[port->number]) +return ; + + ret =device_create (ppdev_class, port->dev, +MKDEV (PP_MAJOR , port->number),NULL , +"parport%d" , port->number); +if (IS_ERR (ret)) { +pr_err ("Failed to create device parport%d\n" , + port->number); +return ; + } + devices[port->number] = ret; }static void pp_detach (struct parport *port) { +if (!devices[port->number]) +return ; +device_destroy (ppdev_class,MKDEV (PP_MAJOR , port->number)); + devices[port->number] =NULL ; }static int pp_probe (struct pardevice *par_dev)
Greg Kroah-Hartman
maintainerPATCH 2/152 ppdev: fix registering same device name
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sudip Mukherjee <[email protected]>
commit 9a69645dde1188723d80745c1bc6ee9af2cbe2a7 upstream.
Usually every parallel port will have a single pardev registered with it. But ppdev driver is an exception. This userspace parallel port driver allows to create multiple parrallel port devices for a single parallel port. And as a result we were having a big warning like:
"sysfs: cannot create duplicate filename '/devices/parport0/ppdev0.0'". And with that many parallel port printers stopped working.
We have been using the minor number as the id field while registering a parralel port device with a parralel port. But when there are multiple parrallel port device for one single parallel port, they all tried to register with the same name like 'pardev0.0' and everything started failing.
Use an incremented index as the id instead of the minor number.
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1414656
Bugzilla: https://bugs.archlinux.org/task/52322
--- drivers/char/ppdev.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
drivers/char/ppdev.c +9 -1
@@ -84,11 +84,14 @@ struct pp_struct {struct ieee1284_info state;struct ieee1284_info saved_state;long default_inactivity; +int index; };/* should we use PARDEVICE_MAX here? */ static struct device *devices[PARPORT_MAX ]; +static DEFINE_IDA (ida_index); +/* pp_struct.flags bitfields */ #define PP_CLAIMED (1<<0)#define PP_EXCL (1<<1)
@@ -290,6 +293,7 @@ static int register_device(int minor, ststruct pardevice *pdev =NULL ;char *name;struct pardev_cb ppdev_cb; +int index; name =kasprintf (GFP_KERNEL ,CHRDEV "%x" , minor);if (name ==NULL )
@@ -302,20 +306,23 @@ static int register_device(int minor, streturn -ENXIO ; } + index =ida_simple_get (&ida_index,0 ,0 ,GFP_KERNEL );memset (&ppdev_cb,0 ,sizeof (ppdev_cb)); ppdev_cb.irq_func = pp_irq; ppdev_cb.flags = (pp->flags &PP_EXCL ) ?PARPORT_FLAG_EXCL :0 ; ppdev_cb.private = pp; - pdev =parport_register_dev_model (port, name, &ppdev_cb, minor); + pdev =parport_register_dev_model (port, name, &ppdev_cb, index);parport_put_port (port);if (!pdev) {printk (KERN_WARNING "%s: failed to register device!\n" , name); +ida_simple_remove (&ida_index, index);kfree (name);return -ENXIO ; } pp->pdev = pdev; + pp->index = index;dev_dbg (&pdev->dev,"registered pardevice\n" );return 0 ; }
@@ -752,6 +759,7 @@ static int pp_release(struct inode *inodif (pp->pdev) {parport_unregister_device (pp->pdev); +ida_simple_remove (&ida_index, pp->index); pp->pdev =NULL ;pr_debug (CHRDEV "%x: unregistered pardevice\n" , minor); }
Greg Kroah-Hartman
maintainerPATCH 3/152 drm/vmwgfx: Type-check lookups of fence objects
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Thomas Hellstrom <[email protected]>
commit f7652afa8eadb416b23eb57dec6f158529942041 upstream.
A malicious caller could otherwise hand over handles to other objects causing all sorts of interesting problems.
Testing done: Ran a Fedora 25 desktop using both Xorg and gnome-shell/Wayland.
--- drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 75 ++++++++++++++++++++++------------ 1 file changed, 49 insertions(+), 26 deletions(-)
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c +49 -26
@@ -538,7 +538,7 @@ int vmw_fence_create(struct vmw_fence_ma struct vmw_fence_obj **p_fence) {struct vmw_fence_obj *fence; -int ret; +int ret; fence =kzalloc (sizeof (*fence),GFP_KERNEL );if (unlikely (fence ==NULL ))
@@ -701,6 +701,41 @@ void vmw_fence_fifo_up(struct vmw_fence_ } +/** +* vmw_fence_obj_lookup - Look up a user-space fence object +* +* @tfile: A struct ttm_object_file identifying the caller. +* @handle: A handle identifying the fence object. +* @return: A struct vmw_user_fence base ttm object on success or +* an error pointer on failure. +* +* The fence object is looked up and type-checked. The caller needs +* to have opened the fence object first, but since that happens on +* creation and fence objects aren't shareable, that's not an +* issue currently. +*/ +static struct ttm_base_object * +vmw_fence_obj_lookup (struct ttm_object_file *tfile,u32 handle) +{ +struct ttm_base_object *base =ttm_base_object_lookup (tfile, handle); + +if (!base) { +pr_err ("Invalid fence object handle 0x%08lx.\n" , + (unsigned long )handle); +return ERR_PTR (-EINVAL ); + } + +if (base->refcount_release != vmw_user_fence_base_release) { +pr_err ("Invalid fence object handle 0x%08lx.\n" , + (unsigned long )handle); +ttm_base_object_unref (&base); +return ERR_PTR (-EINVAL ); + } + +return base; +} + +int vmw_fence_obj_wait_ioctl (struct drm_device *dev,void *data,struct drm_file *file_priv) {
@@ -726,13 +761,9 @@ int vmw_fence_obj_wait_ioctl(struct drm_ arg->kernel_cookie = jiffies + wait_timeout; } - base =ttm_base_object_lookup (tfile, arg->handle); -if (unlikely (base ==NULL )) { -printk (KERN_ERR "Wait invalid fence object handle " -"0x%08lx.\n" , - (unsigned long )arg->handle); -return -EINVAL ; - } + base =vmw_fence_obj_lookup (tfile, arg->handle); +if (IS_ERR (base)) +return PTR_ERR (base); fence = &(container_of(base, struct vmw_user_fence, base)->fence);
@@ -771,13 +802,9 @@ int vmw_fence_obj_signaled_ioctl(structstruct ttm_object_file *tfile =vmw_fpriv (file_priv)->tfile;struct vmw_private *dev_priv =vmw_priv (dev); - base =ttm_base_object_lookup (tfile, arg->handle); -if (unlikely (base ==NULL )) { -printk (KERN_ERR "Fence signaled invalid fence object handle " -"0x%08lx.\n" , - (unsigned long )arg->handle); -return -EINVAL ; - } + base =vmw_fence_obj_lookup (tfile, arg->handle); +if (IS_ERR (base)) +return PTR_ERR (base); fence = &(container_of(base, struct vmw_user_fence, base)->fence); fman =fman_from_fence (fence);
@@ -1024,6 +1051,7 @@ int vmw_fence_event_ioctl(struct drm_dev (struct drm_vmw_fence_event_arg *) data;struct vmw_fence_obj *fence =NULL ;struct vmw_fpriv *vmw_fp =vmw_fpriv (file_priv); +struct ttm_object_file *tfile = vmw_fp->tfile;struct drm_vmw_fence_rep __user *user_fence_rep = (struct drm_vmw_fence_rep __user *)(unsigned long ) arg->fence_rep;
@@ -1037,15 +1065,11 @@ int vmw_fence_event_ioctl(struct drm_dev*/ if (arg->handle) {struct ttm_base_object *base = -ttm_base_object_lookup_for_ref (dev_priv->tdev, - arg->handle); +vmw_fence_obj_lookup (tfile, arg->handle); + +if (IS_ERR (base)) +return PTR_ERR (base); -if (unlikely (base ==NULL )) { -DRM_ERROR ("Fence event invalid fence object handle " -"0x%08lx.\n" , - (unsigned long )arg->handle); -return -EINVAL ; - } fence = &(container_of(base, struct vmw_user_fence, base)->fence); (void )vmw_fence_obj_reference (fence);
@@ -1053,7 +1077,7 @@ int vmw_fence_event_ioctl(struct drm_devif (user_fence_rep !=NULL ) {bool existed; - ret =ttm_ref_object_add (vmw_fp->tfile, base, + ret =ttm_ref_object_add (tfile, base,TTM_REF_USAGE , &existed);if (unlikely (ret !=0 )) { DRM_ERROR("Failed to reference a fence "
@@ -1097,8 +1121,7 @@ int vmw_fence_event_ioctl(struct drm_devreturn 0 ; out_no_create:if (user_fence_rep !=NULL ) -ttm_ref_object_base_unref (vmw_fpriv (file_priv)->tfile, - handle,TTM_REF_USAGE ); +ttm_ref_object_base_unref (tfile, handle,TTM_REF_USAGE ); out_no_ref_obj:vmw_fence_obj_unreference (&fence);return ret;
Greg Kroah-Hartman
maintainerPATCH 4/152 drm/vmwgfx: NULL pointer dereference in vmw_surface_define_ioctl()
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Murray McAllister <[email protected]>
commit 36274ab8c596f1240c606bb514da329add2a1bcd upstream.
Before memory allocations vmw_surface_define_ioctl() checks the upper-bounds of a user-supplied size, but does not check if the supplied size is 0.
Add check to avoid NULL pointer dereferences.
--- drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c +2 -2
@@ -716,8 +716,8 @@ int vmw_surface_define_ioctl(struct drm_for (i =0 ; i <DRM_VMW_MAX_SURFACE_FACES ; ++i) num_sizes += req->mip_levels[i]; -if (num_sizes >DRM_VMW_MAX_SURFACE_FACES * -DRM_VMW_MAX_MIP_LEVELS ) +if (num_sizes >DRM_VMW_MAX_SURFACE_FACES *DRM_VMW_MAX_MIP_LEVELS || + num_sizes ==0 )return -EINVAL ; size = vmw_user_surface_size + 128 +
Greg Kroah-Hartman
maintainerPATCH 5/152 drm/vmwgfx: avoid calling vzalloc with a 0 size in vmw_get_cap_3d_ioctl()
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Murray McAllister <[email protected]>
commit 63774069d9527a1aeaa4aa20e929ef5e8e9ecc38 upstream.
In vmw_get_cap_3d_ioctl(), a user can supply 0 for a size that is used in vzalloc(). This eventually calls dump_stack() (in warn_alloc()), which can leak useful addresses to dmesg.
Add check to avoid a size of 0.
--- drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c +1 -1
@@ -186,7 +186,7 @@ int vmw_get_cap_3d_ioctl(struct drm_devibool gb_objects = !!(dev_priv->capabilities &SVGA_CAP_GBOBJECTS );struct vmw_fpriv *vmw_fp =vmw_fpriv (file_priv); -if (unlikely (arg->pad64 !=0 )) { +if (unlikely (arg->pad64 !=0 || arg->max_size ==0 )) {DRM_ERROR ("Illegal GET_3D_CAP argument.\n" );return -EINVAL ; }
Greg Kroah-Hartman
maintainerPATCH 6/152 drm/ttm, drm/vmwgfx: Relax permission checking when opening surfaces
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Thomas Hellstrom <[email protected]>
commit fe25deb7737ce6c0879ccf79c99fa1221d428bf2 upstream.
Previously, when a surface was opened using a legacy (non prime) handle, it was verified to have been created by a client in the same master realm. Relax this so that opening is also allowed recursively if the client already has the surface open.
This works around a regression in svga mesa where opening of a shared surface is used recursively to obtain surface information.
--- drivers/gpu/drm/ttm/ttm_object.c | 10 +++++++--- drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 6 ++---- drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 4 ++-- drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 22 +++++++++------------- include/drm/ttm/ttm_object.h | 5 ++++- 5 files changed, 24 insertions(+), 23 deletions(-)
drivers/gpu/drm/ttm/ttm_object.c +7 -3
@@ -179,7 +179,7 @@ int ttm_base_object_init(struct ttm_objeif (unlikely (ret !=0 )) goto out_err0; - ret =ttm_ref_object_add (tfile, base,TTM_REF_USAGE ,NULL ); + ret =ttm_ref_object_add (tfile, base,TTM_REF_USAGE ,NULL , false);if (unlikely (ret !=0 )) goto out_err1;
@@ -318,7 +318,8 @@ EXPORT_SYMBOL(ttm_ref_object_exists);int ttm_ref_object_add (struct ttm_object_file *tfile,struct ttm_base_object *base, -enum ttm_ref_type ref_type,bool *existed) +enum ttm_ref_type ref_type,bool *existed, +bool require_existed) {struct drm_open_hash *ht = &tfile->ref_hash[ref_type];struct ttm_ref_object *ref;
@@ -345,6 +346,9 @@ int ttm_ref_object_add(struct ttm_object }rcu_read_unlock (); +if (require_existed) +return -EPERM ; + ret =ttm_mem_global_alloc (mem_glob,sizeof (*ref), false, false);if (unlikely (ret !=0 ))
@@ -635,7 +639,7 @@ int ttm_prime_fd_to_handle(struct ttm_ob prime = (struct ttm_prime_object *) dma_buf->priv; base = &prime->base; *handle = base->hash.key; - ret =ttm_ref_object_add (tfile, base,TTM_REF_USAGE ,NULL ); + ret =ttm_ref_object_add (tfile, base,TTM_REF_USAGE ,NULL , false);dma_buf_put (dma_buf);
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c +2 -4
@@ -1075,10 +1075,8 @@ int vmw_fence_event_ioctl(struct drm_dev (void )vmw_fence_obj_reference (fence);if (user_fence_rep !=NULL ) { -bool existed; - - ret =ttm_ref_object_add (tfile, base, -TTM_REF_USAGE , &existed); + ret =ttm_ref_object_add (vmw_fp->tfile, base, +TTM_REF_USAGE ,NULL , false);if (unlikely (ret !=0 )) {DRM_ERROR ("Failed to reference a fence " "object.\n" );
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c +2 -2
@@ -589,7 +589,7 @@ static int vmw_user_dmabuf_synccpu_grab(return ret; ret =ttm_ref_object_add (tfile, &user_bo->prime.base, -TTM_REF_SYNCCPU_WRITE , &existed); +TTM_REF_SYNCCPU_WRITE , &existed, false);if (ret !=0 || existed)ttm_bo_synccpu_write_release (&user_bo->dma.base);
@@ -773,7 +773,7 @@ int vmw_user_dmabuf_reference(struct ttm *handle = user_bo->prime.base.hash.key;return ttm_ref_object_add (tfile, &user_bo->prime.base, -TTM_REF_USAGE ,NULL ); +TTM_REF_USAGE ,NULL , false); }/*
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c +9 -13
@@ -891,17 +891,16 @@ vmw_surface_handle_reference(struct vmw_uint32_t handle;struct ttm_base_object *base;int ret; +bool require_exist = false;if (handle_type ==DRM_VMW_HANDLE_PRIME ) { ret =ttm_prime_fd_to_handle (tfile, u_handle, &handle);if (unlikely (ret !=0 ))return ret; }else { -if (unlikely (drm_is_render_client (file_priv))) { -DRM_ERROR ("Render client refused legacy " -"surface reference.\n" ); -return -EACCES ; - } +if (unlikely (drm_is_render_client (file_priv))) + require_exist = true; +if (ACCESS_ONCE (vmw_fpriv (file_priv)->locked_master)) {DRM_ERROR ("Locked master refused legacy " "surface reference.\n" );
@@ -929,17 +928,14 @@ vmw_surface_handle_reference(struct vmw_/* * Make sure the surface creator has the same -* authenticating master. +* authenticating master, or is already registered with us. */ if (drm_is_primary_client (file_priv) && - user_srf->master != file_priv->master) { -DRM_ERROR ("Trying to reference surface outside of" -" master domain.\n" ); - ret = -EACCES ; - goto out_bad_resource; - } + user_srf->master != file_priv->master) + require_exist = true; - ret =ttm_ref_object_add (tfile, base,TTM_REF_USAGE ,NULL ); + ret =ttm_ref_object_add (tfile, base,TTM_REF_USAGE ,NULL , + require_exist);if (unlikely (ret !=0 )) {DRM_ERROR ("Could not add a reference to a surface.\n" ); goto out_bad_resource;
include/drm/ttm/ttm_object.h +4 -1
@@ -229,6 +229,8 @@ extern void ttm_base_object_unref(struct* @ref_type: The type of reference. * @existed: Upon completion, indicates that an identical reference object * already existed, and the refcount was upped on that object instead. +* @require_existed: Fail with -EPERM if an identical ref object didn't +* already exist. * * Checks that the base object is shareable and adds a ref object to it. *
@@ -243,7 +245,8 @@ extern void ttm_base_object_unref(struct*/ extern int ttm_ref_object_add (struct ttm_object_file *tfile,struct ttm_base_object *base, -enum ttm_ref_type ref_type,bool *existed); +enum ttm_ref_type ref_type,bool *existed, +bool require_existed);extern bool ttm_ref_object_exists (struct ttm_object_file *tfile,struct ttm_base_object *base);
Greg Kroah-Hartman
maintainerPATCH 7/152 drm/vmwgfx: Remove getparam error message
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Thomas Hellstrom <[email protected]>
commit 53e16798b0864464c5444a204e1bb93ae246c429 upstream.
The mesa winsys sometimes uses unimplemented parameter requests to check for features. Remove the error message to avoid bloating the kernel log.
--- drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c | 2 -- 1 file changed, 2 deletions(-)
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c +0 -2
@@ -114,8 +114,6 @@ int vmw_getparam_ioctl(struct drm_device param->value = dev_priv->has_dx;break ;default : -DRM_ERROR ("Illegal vmwgfx get param request: %d\n" , - param->param);return -EINVAL ; }
Greg Kroah-Hartman
maintainerPATCH 8/152 drm/vmwgfx: fix integer overflow in vmw_surface_define_ioctl()
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Li Qiang <[email protected]>
commit e7e11f99564222d82f0ce84bd521e57d78a6b678 upstream.
In vmw_surface_define_ioctl(), the 'num_sizes' is the sum of the 'req->mip_levels' array. This array can be assigned any value from the user space. As both the 'num_sizes' and the array is uint32_t, it is easy to make 'num_sizes' overflow. The later 'mip_levels' is used as the loop count. This can lead an oob write. Add the check of 'req->mip_levels' to avoid this.
--- drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c +4 -1
@@ -713,8 +713,11 @@ int vmw_surface_define_ioctl(struct drm_128 ; num_sizes =0 ; -for (i =0 ; i <DRM_VMW_MAX_SURFACE_FACES ; ++i) +for (i =0 ; i <DRM_VMW_MAX_SURFACE_FACES ; ++i) { +if (req->mip_levels[i] >DRM_VMW_MAX_MIP_LEVELS ) +return -EINVAL ; num_sizes += req->mip_levels[i]; + }if (num_sizes >DRM_VMW_MAX_SURFACE_FACES *DRM_VMW_MAX_MIP_LEVELS || num_sizes ==0 )
Greg Kroah-Hartman
maintainerPATCH 9/152 sysfs: be careful of error returns from ops->show()
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: NeilBrown <[email protected]>
commit c8a139d001a1aab1ea8734db14b22dac9dd143b6 upstream.
ops->show() can return a negative error code.
Commit 65da3484d9be ("sysfs: correctly handle short reads on PREALLOC attrs.") (in v4.4) caused this to be stored in an unsigned 'size_t' variable, so errors would look like large numbers.
As a result, if an error is returned, sysfs_kf_read() will return the value of 'count', typically 4096.
Commit 17d0774f8068 ("sysfs: correctly handle read offset on PREALLOC attrs") (in v4.8) extended this error to use the unsigned large 'len' as a size for memmove().
Consequently, if ->show returns an error, then the first read() on the sysfs file will return 4096 and could return uninitialized memory to user-space.
If the application performs a subsequent read, this will trigger a memmove() with extremely large count, and is likely to crash the machine is bizarre ways.
This bug can currently only be triggered by reading from an md sysfs attribute declared with __ATTR_PREALLOC() during the brief period between when mddev_put() deletes an mddev from the ->all_mddevs list, and when mddev_delayed_delete() - which is scheduled on a workqueue - completes.
Before this, an error won't be returned by the ->show() After this, the ->show() won't be called.
I can reproduce it reliably only by putting delay like
usleep_range(500000,700000);
early in mddev_delayed_delete(). Then after creating an
md device md0 run
echo clear > /sys/block/md0/md/array_state; cat /sys/block/md0/md/array_state
The bug can be triggered without the usleep.
--- fs/sysfs/file.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
fs/sysfs/file.c +4 -2
@@ -108,7 +108,7 @@ static ssize_t sysfs_kf_read(struct kern {const struct sysfs_ops *ops =sysfs_file_ops (of->kn);struct kobject *kobj = of->kn->parent->priv; -size_t len; +ssize_t len;/* * If buf != of->prealloc_buf, we don't know how
@@ -117,13 +117,15 @@ static ssize_t sysfs_kf_read(struct kernif (WARN_ON_ONCE (buf != of->prealloc_buf))return 0 ; len = ops->show (kobj, of->kn->priv, buf); +if (len <0 ) +return len;if (pos) {if (len <= pos)return 0 ; len -= pos;memmove (buf, buf + pos, len); } -return min (count, len); +return min_t (ssize_t, count, len); }/* kernfs write callback for regular sysfs files */
Greg Kroah-Hartman
maintainerPATCH 10/152 staging: android: ashmem: lseek failed due to no FMODE_LSEEK.
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Shuxiao Zhang <[email protected]>
commit 97fbfef6bd597888485b653175fb846c6998b60c upstream.
vfs_llseek will check whether the file mode has FMODE_LSEEK, no return failure. But ashmem can be lseek, so add FMODE_LSEEK to ashmem file.
Comment From Greg Hackmann:
ashmem_llseek() passes the llseek() call through to the backing shmem file. 91360b02ab48 ("ashmem: use vfs_llseek()") changed this from directly calling the file's llseek() op into a VFS layer call. This also adds a check for the FMODE_LSEEK bit, so without that bit ashmem_llseek() now always fails with -ESPIPE.
--- drivers/staging/android/ashmem.c | 1 + 1 file changed, 1 insertion(+)
drivers/staging/android/ashmem.c +1 -0
@@ -405,6 +405,7 @@ static int ashmem_mmap(struct file *file ret =PTR_ERR (vmfile); goto out; } + vmfile->f_mode |=FMODE_LSEEK ; asma->file = vmfile; }get_file (asma->file);
Greg Kroah-Hartman
maintainerPATCH 11/152 arm/arm64: KVM: Take mmap_sem in stage2_unmap_vm
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Marc Zyngier <[email protected]>
commit 90f6e150e44a0dc3883110eeb3ab35d1be42b6bb upstream.
We don't hold the mmap_sem while searching for the VMAs when we try to unmap each memslot for a VM. Fix this properly to avoid unexpected results.
--- arch/arm/kvm/mmu.c | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/kvm/mmu.c +2 -0
@@ -803,6 +803,7 @@ void stage2_unmap_vm(struct kvm *kvm)int idx; idx =srcu_read_lock (&kvm->srcu); +down_read (¤t->mm->mmap_sem);spin_lock (&kvm->mmu_lock); slots =kvm_memslots (kvm);
@@ -810,6 +811,7 @@ void stage2_unmap_vm(struct kvm *kvm)stage2_unmap_memslot (kvm, memslot);spin_unlock (&kvm->mmu_lock); +up_read (¤t->mm->mmap_sem);srcu_read_unlock (&kvm->srcu, idx); }
Greg Kroah-Hartman
maintainerPATCH 12/152 arm/arm64: KVM: Take mmap_sem in kvm_arch_prepare_memory_region
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Marc Zyngier <[email protected]>
commit 72f310481a08db821b614e7b5d00febcc9064b36 upstream.
We don't hold the mmap_sem while searching for VMAs (via find_vma), in kvm_arch_prepare_memory_region, which can end up in expected failures.
--- arch/arm/kvm/mmu.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
arch/arm/kvm/mmu.c +8 -3
@@ -1806,6 +1806,7 @@ int kvm_arch_prepare_memory_region(struc (KVM_PHYS_SIZE >> PAGE_SHIFT))return -EFAULT ; +down_read (¤t->mm->mmap_sem);/* * A memory region could potentially cover multiple VMAs, and any holes * between them, so iterate over all of them to find out if we can map
@@ -1849,8 +1850,10 @@ int kvm_arch_prepare_memory_region(struc pa += vm_start - vma->vm_start;/* IO region dirty page logging not allowed */ -if (memslot->flags &KVM_MEM_LOG_DIRTY_PAGES ) -return -EINVAL ; +if (memslot->flags &KVM_MEM_LOG_DIRTY_PAGES ) { + ret = -EINVAL ; + goto out; + } ret = kvm_phys_addr_ioremap(kvm, gpa, pa, vm_end - vm_start,
@@ -1862,7 +1865,7 @@ int kvm_arch_prepare_memory_region(struc }while (hva < reg_end);if (change ==KVM_MR_FLAGS_ONLY ) -return ret; + goto out;spin_lock (&kvm->mmu_lock);if (ret)
@@ -1870,6 +1873,8 @@ int kvm_arch_prepare_memory_region(strucelse stage2_flush_memslot (kvm, memslot);spin_unlock (&kvm->mmu_lock); +out: +up_read (¤t->mm->mmap_sem);return ret; }
Greg Kroah-Hartman
maintainerPATCH 13/152 kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Suzuki K Poulose <[email protected]>
commit 8b3405e345b5a098101b0c31b264c812bba045d9 upstream.
In kvm_free_stage2_pgd() we don't hold the kvm->mmu_lock while calling unmap_stage2_range() on the entire memory range for the guest. This could cause problems with other callers (e.g, munmap on a memslot) trying to unmap a range. And since we have to unmap the entire Guest memory range holding a spinlock, make sure we yield the lock if necessary, after we unmap each PUD range.
--- arch/arm/kvm/mmu.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/kvm/mmu.c +10 -0
@@ -292,11 +292,18 @@ static void unmap_stage2_range(struct kvphys_addr_t addr = start, end = start + size;phys_addr_t next; +assert_spin_locked (&kvm->mmu_lock); pgd = kvm->arch.pgd +stage2_pgd_index (addr);do { next =stage2_pgd_addr_end (addr, end);if (!stage2_pgd_none (*pgd))unmap_stage2_puds (kvm, pgd, addr, next); +/* +* If the range is too large, release the kvm->mmu_lock +* to prevent starvation and lockup detector warnings. +*/ +if (next != end) +cond_resched_lock (&kvm->mmu_lock); }while (pgd++, addr = next, addr != end); }
@@ -831,7 +838,10 @@ void kvm_free_stage2_pgd(struct kvm *kvmif (kvm->arch.pgd ==NULL )return ; +spin_lock (&kvm->mmu_lock);unmap_stage2_range (kvm,0 ,KVM_PHYS_SIZE ); +spin_unlock (&kvm->mmu_lock); +/* Free the HW pgd, one page at a time */ free_pages_exact (kvm->arch.pgd,S2_PGD_SIZE ); kvm->arch.pgd =NULL ;
Greg Kroah-Hartman
maintainerPATCH 14/152 iio: bmg160: reset chip when probing
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Quentin Schulz <[email protected]>
commit 4bdc9029685ac03be50b320b29691766d2326c2b upstream.
The gyroscope chip might need to be reset to be used.
Without the chip being reset, the driver stopped at the first regmap_read (to get the CHIP_ID) and failed to probe.
The datasheet of the gyroscope says that a minimum wait of 30ms after the reset has to be done.
This patch has been checked on a BMX055 and the datasheet of the BMG160 and the BMI055 give the same reset register and bits.
--- drivers/iio/gyro/bmg160_core.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
drivers/iio/gyro/bmg160_core.c +12 -0
@@ -27,6 +27,7 @@#include <linux/iio/trigger_consumer.h> #include <linux/iio/triggered_buffer.h> #include <linux/regmap.h> +#include <linux/delay.h> #include "bmg160.h" #define BMG160_IRQ_NAME "bmg160_event"
@@ -52,6 +53,9 @@#define BMG160_DEF_BW 100#define BMG160_REG_PMU_BW_RES BIT(7) +#define BMG160_GYRO_REG_RESET 0x14 +#define BMG160_GYRO_RESET_VAL 0xb6 +#define BMG160_REG_INT_MAP_0 0x17#define BMG160_INT_MAP_0_BIT_ANY BIT(1)
@@ -236,6 +240,14 @@ static int bmg160_chip_init(struct bmg16int ret;unsigned int val; +/* +* Reset chip to get it in a known good state. A delay of 30ms after +* reset is required according to the datasheet. +*/ +regmap_write (data->regmap,BMG160_GYRO_REG_RESET , +BMG160_GYRO_RESET_VAL ); +usleep_range (30000 ,30700 ); + ret =regmap_read (data->regmap,BMG160_REG_CHIP_ID , &val);if (ret <0 ) {dev_err (dev,"Error reading reg_chip_id\n" );
Greg Kroah-Hartman
maintainerPATCH 15/152 arm64: mm: unaligned access by user-land should be received as SIGBUS
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Victor Kamensky <[email protected]>
commit 09a6adf53d42ca3088fa3fb41f40b768efc711ed upstream.
After 52d7523 (arm64: mm: allow the kernel to handle alignment faults on user accesses) commit user-land accesses that produce unaligned exceptions like in case of aarch32 ldm/stm/ldrd/strd instructions operating on unaligned memory received by user-land as SIGSEGV. It is wrong, it should be reported as SIGBUS as it was before 52d7523 commit.
Changed do_bad_area function to take signal and code parameters out of esr value using fault_info table, so in case of do_alignment_fault fault user-land will receive SIGBUS. Wrapped access to fault_info table into esr_to_fault_info function.
--- arch/arm64/mm/fault.c | 42 ++++++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 18 deletions(-)
arch/arm64/mm/fault.c +24 -18
@@ -41,7 +41,20 @@#include <asm/pgtable.h> #include <asm/tlbflush.h> -static const char *fault_name (unsigned int esr); +struct fault_info { +int (*fn)(unsigned long addr,unsigned int esr, +struct pt_regs *regs); +int sig; +int code; +const char *name; +}; + +static const struct fault_info fault_info[]; + +static inline const struct fault_info *esr_to_fault_info (unsigned int esr) +{ +return fault_info + (esr &63 ); +}#ifdef CONFIG_KPROBES static inline int notify_page_fault (struct pt_regs *regs,unsigned int esr)
@@ -196,10 +209,12 @@ static void __do_user_fault(struct task_ struct pt_regs *regs) {struct siginfo si; +const struct fault_info *inf;if (unhandled_signal (tsk, sig) &&show_unhandled_signals_ratelimited ()) { + inf =esr_to_fault_info (esr);pr_info ("%s[%d]: unhandled %s (%d) at 0x%08lx, esr 0x%03x\n" , - tsk->comm,task_pid_nr (tsk),fault_name (esr), sig, + tsk->comm,task_pid_nr (tsk), inf->name, sig, addr, esr);show_pte (tsk->mm, addr);show_regs (regs);
@@ -218,14 +233,16 @@ static void do_bad_area(unsigned long ad {struct task_struct *tsk = current;struct mm_struct *mm = tsk->active_mm; +const struct fault_info *inf;/* * If we are in kernel mode at this point, we have no context to * handle this fault with. */ -if (user_mode (regs)) -__do_user_fault (tsk, addr, esr,SIGSEGV ,SEGV_MAPERR , regs); -else +if (user_mode (regs)) { + inf =esr_to_fault_info (esr); +__do_user_fault (tsk, addr, esr, inf->sig, inf->code, regs); + }else __do_kernel_fault (mm, addr, esr, regs); }
@@ -481,12 +498,7 @@ static int do_bad(unsigned long addr, unreturn 1 ; } -static const struct fault_info { -int (*fn)(unsigned long addr,unsigned int esr,struct pt_regs *regs); -int sig; -int code; -const char *name; -} fault_info[] = { +static const struct fault_info fault_info[] = { { do_bad,SIGBUS ,0 ,"ttbr address size fault" }, { do_bad,SIGBUS ,0 ,"level 1 address size fault" }, { do_bad,SIGBUS ,0 ,"level 2 address size fault" },
@@ -553,19 +565,13 @@ static const struct fault_info { { do_bad, SIGBUS, 0, "unknown 63" }, }; -static const char *fault_name (unsigned int esr) -{ -const struct fault_info *inf = fault_info + (esr &63 ); -return inf->name; -} -/* * Dispatch a data abort to the relevant handler. */ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr,struct pt_regs *regs) { -const struct fault_info *inf = fault_info + (esr &63 ); +const struct fault_info *inf =esr_to_fault_info (esr);struct siginfo info;if (!inf->fn (addr, esr, regs))
Greg Kroah-Hartman
maintainerPATCH 16/152 cfg80211: check rdev resume callback only for registered wiphy
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Arend Van Spriel <[email protected]>
commit b3ef5520c1eabb56064474043c7c55a1a65b8708 upstream.
We got the following use-after-free KASAN report:
BUG: KASAN: use-after-free in wiphy_resume+0x591/0x5a0 [cfg80211]
at addr ffff8803fc244090
Read of size 8 by task kworker/u16:24/2587
CPU: 6 PID: 2587 Comm: kworker/u16:24 Tainted: G B 4.9.13-debug+
Hardware name: Dell Inc. XPS 15 9550/0N7TVV, BIOS 1.2.19 12/22/2016
Workqueue: events_unbound async_run_entry_fn
ffff880425d4f9d8 ffffffffaeedb541 ffff88042b80ef00 ffff8803fc244088
ffff880425d4fa00 ffffffffae84d7a1 ffff880425d4fa98 ffff8803fc244080
ffff88042b80ef00 ffff880425d4fa88 ffffffffae84da3a ffffffffc141f7d9
Call Trace:
[<ffffffffaeedb541>] dump_stack+0x85/0xc4
[<ffffffffae84d7a1>] kasan_object_err+0x21/0x70
[<ffffffffae84da3a>] kasan_report_error+0x1fa/0x500
[<ffffffffc141f7d9>] ? cfg80211_bss_age+0x39/0xc0 [cfg80211]
[<ffffffffc141f83a>] ? cfg80211_bss_age+0x9a/0xc0 [cfg80211]
[<ffffffffae48d46d>] ? trace_hardirqs_on+0xd/0x10
[<ffffffffc13fb1c0>] ? wiphy_suspend+0xc70/0xc70 [cfg80211]
[<ffffffffae84def1>] __asan_report_load8_noabort+0x61/0x70
[<ffffffffc13fb100>] ? wiphy_suspend+0xbb0/0xc70 [cfg80211]
[<ffffffffc13fb751>] ? wiphy_resume+0x591/0x5a0 [cfg80211]
[<ffffffffc13fb751>] wiphy_resume+0x591/0x5a0 [cfg80211]
[<ffffffffc13fb1c0>] ? wiphy_suspend+0xc70/0xc70 [cfg80211]
[<ffffffffaf3b206e>] dpm_run_callback+0x6e/0x4f0
[<ffffffffaf3b31b2>] device_resume+0x1c2/0x670
[<ffffffffaf3b367d>] async_resume+0x1d/0x50
[<ffffffffae3ee84e>] async_run_entry_fn+0xfe/0x610
[<ffffffffae3d0666>] process_one_work+0x716/0x1a50
[<ffffffffae3d05c9>] ? process_one_work+0x679/0x1a50
[<ffffffffafdd7b6d>] ? _raw_spin_unlock_irq+0x3d/0x60
[<ffffffffae3cff50>] ? pwq_dec_nr_in_flight+0x2b0/0x2b0
[<ffffffffae3d1a80>] worker_thread+0xe0/0x1460
[<ffffffffae3d19a0>] ? process_one_work+0x1a50/0x1a50
[<ffffffffae3e54c2>] kthread+0x222/0x2e0
[<ffffffffae3e52a0>] ? kthread_park+0x80/0x80
[<ffffffffae3e52a0>] ? kthread_park+0x80/0x80
[<ffffffffae3e52a0>] ? kthread_park+0x80/0x80
[<ffffffffafdd86aa>] ret_from_fork+0x2a/0x40
Object at ffff8803fc244088, in cache kmalloc-1024 size: 1024
Allocated:
PID = 71
save_stack_trace+0x1b/0x20
save_stack+0x46/0xd0
kasan_kmalloc+0xad/0xe0
kasan_slab_alloc+0x12/0x20
__kmalloc_track_caller+0x134/0x360
kmemdup+0x20/0x50
brcmf_cfg80211_attach+0x10b/0x3a90 [brcmfmac]
brcmf_bus_start+0x19a/0x9a0 [brcmfmac]
brcmf_pcie_setup+0x1f1a/0x3680 [brcmfmac]
brcmf_fw_request_nvram_done+0x44c/0x11b0 [brcmfmac]
request_firmware_work_func+0x135/0x280
process_one_work+0x716/0x1a50
worker_thread+0xe0/0x1460
kthread+0x222/0x2e0
ret_from_fork+0x2a/0x40
Freed:
PID = 2568
save_stack_trace+0x1b/0x20
save_stack+0x46/0xd0
kasan_slab_free+0x71/0xb0
kfree+0xe8/0x2e0
brcmf_cfg80211_detach+0x62/0xf0 [brcmfmac]
brcmf_detach+0x14a/0x2b0 [brcmfmac]
brcmf_pcie_remove+0x140/0x5d0 [brcmfmac]
brcmf_pcie_pm_leave_D3+0x198/0x2e0 [brcmfmac]
pci_pm_resume+0x186/0x220
dpm_run_callback+0x6e/0x4f0
device_resume+0x1c2/0x670
async_resume+0x1d/0x50
async_run_entry_fn+0xfe/0x610
process_one_work+0x716/0x1a50
worker_thread+0xe0/0x1460
kthread+0x222/0x2e0
ret_from_fork+0x2a/0x40
Memory state around the buggy address:
ffff8803fc243f80: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
ffff8803fc244000: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
>ffff8803fc244080: fc fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
^
ffff8803fc244100: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
ffff8803fc244180: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fbWhat is happening is that brcmf_pcie_resume() detects a device that is no longer responsive and it decides to unbind resulting in a wiphy_unregister() and wiphy_free() call. Now the wiphy instance remains allocated, because PM needs to call wiphy_resume() for it. However, brcmfmac already does a kfree() for the struct cfg80211_registered_device::ops field. Change the checks in wiphy_resume() to only access the struct cfg80211_registered_device::ops if the wiphy instance is still registered at this time.
--- net/wireless/sysfs.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
net/wireless/sysfs.c +4 -6
@@ -130,12 +130,10 @@ static int wiphy_resume(struct device *d/* Age scan results with time spent in suspend */ cfg80211_bss_age (rdev,get_seconds () - rdev->suspend_at); -if (rdev->ops->resume) { -rtnl_lock (); -if (rdev->wiphy.registered) - ret =rdev_resume (rdev); -rtnl_unlock (); - } +rtnl_lock (); +if (rdev->wiphy.registered && rdev->ops->resume) + ret =rdev_resume (rdev); +rtnl_unlock ();return ret; }
Greg Kroah-Hartman
maintainerPATCH 17/152 Reset TreeId to zero on SMB2 TREE_CONNECT
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jan-Marek Glogowski <[email protected]>
commit 806a28efe9b78ffae5e2757e1ee924b8e50c08ab upstream.
Currently the cifs module breaks the CIFS specs on reconnect as described in http://msdn.microsoft.com/en-us/library/cc246529.aspx:
"TreeId (4 bytes): Uniquely identifies the tree connect for the command. This MUST be 0 for the SMB2 TREE_CONNECT Request."
--- fs/cifs/smb2pdu.c | 4 ++++ 1 file changed, 4 insertions(+)
fs/cifs/smb2pdu.c +4 -0
@@ -1104,6 +1104,10 @@ SMB2_tcon(const unsigned int xid, structreturn -EINVAL ; } +/* SMB2 TREE_CONNECT request must be called with TreeId == 0 */ +if (tcon) + tcon->tid =0 ; + rc =small_smb2_init (SMB2_TREE_CONNECT , tcon, (void **) &req);if (rc) {kfree (unc_path);
Greg Kroah-Hartman
maintainerPATCH 18/152 mm/page_alloc.c: fix print order in show_free_areas()
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Alexander Polakov <[email protected]>
commit 1f06b81aea5ecba2c1f8afd87e0ba1b9f8f90160 upstream.
--- mm/page_alloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
mm/page_alloc.c +1 -1
@@ -4345,13 +4345,13 @@ void show_free_areas(unsigned int filterK (node_page_state (pgdat,NR_FILE_MAPPED )),K (node_page_state (pgdat,NR_FILE_DIRTY )),K (node_page_state (pgdat,NR_WRITEBACK )), +K (node_page_state (pgdat,NR_SHMEM )), #ifdef CONFIG_TRANSPARENT_HUGEPAGEK (node_page_state (pgdat,NR_SHMEM_THPS ) *HPAGE_PMD_NR ),K (node_page_state (pgdat,NR_SHMEM_PMDMAPPED ) *HPAGE_PMD_NR ),K (node_page_state (pgdat,NR_ANON_THPS ) *HPAGE_PMD_NR ), #endif -K (node_page_state (pgdat,NR_SHMEM )),K (node_page_state (pgdat,NR_WRITEBACK_TEMP )),K (node_page_state (pgdat,NR_UNSTABLE_NFS )), node_page_state(pgdat, NR_PAGES_SCANNED),
Greg Kroah-Hartman
maintainerPATCH 19/152 ptrace: fix PTRACE_LISTEN race corrupting task->state
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: [email protected] <[email protected]>
commit 5402e97af667e35e54177af8f6575518bf251d51 upstream.
In PT_SEIZED + LISTEN mode STOP/CONT signals cause a wakeup against __TASK_TRACED. If this races with the ptrace_unfreeze_traced at the end of a PTRACE_LISTEN, this can wake the task /after/ the check against __TASK_TRACED, but before the reset of state to TASK_TRACED. This causes it to instead clobber TASK_WAKING, allowing a subsequent wakeup against TRACED while the task is still on the rq wake_list, corrupting it.
Oleg said:
"The kernel can crash or this can lead to other hard-to-debug problems.
In short, "task->state = TASK_TRACED" in ptrace_unfreeze_traced() assumes that nobody else can wake it up, but PTRACE_LISTEN breaks the contract. Obviusly it is very wrong to manipulate task->state if this task is already running, or WAKING, or it sleeps again"
--- kernel/ptrace.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
kernel/ptrace.c +10 -4
@@ -181,11 +181,17 @@ static void ptrace_unfreeze_traced(strucWARN_ON (!task->ptrace || task->parent != current); +/* +* PTRACE_LISTEN can allow ptrace_trap_notify to wake us up remotely. +* Recheck state under the lock to close this race. +*/ spin_lock_irq (&task->sighand->siglock); -if (__fatal_signal_pending (task)) -wake_up_state (task, __TASK_TRACED); -else - task->state =TASK_TRACED ; +if (task->state == __TASK_TRACED) { +if (__fatal_signal_pending (task)) +wake_up_state (task, __TASK_TRACED); +else + task->state =TASK_TRACED ; + }spin_unlock_irq (&task->sighand->siglock); }
Greg Kroah-Hartman
maintainerPATCH 20/152 dm verity fec: limit error correction recursion
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sami Tolvanen <[email protected]>
commit f1a880a93baaadb14c10a348fd199f1cdb6bcccd upstream.
If the hash tree itself is sufficiently corrupt in addition to data blocks, it's possible for error correction to end up in a deep recursive loop, which eventually causes a kernel panic. This change limits the recursion to a reasonable level during a single I/O operation.
--- drivers/md/dm-verity-fec.c | 12 +++++++++++- drivers/md/dm-verity-fec.h | 4 ++++ 2 files changed, 15 insertions(+), 1 deletion(-)
drivers/md/dm-verity-fec.c +11 -1
@@ -439,6 +439,13 @@ int verity_fec_decode(struct dm_verity *if (!verity_fec_is_enabled (v))return -EOPNOTSUPP ; +if (fio->level >=DM_VERITY_FEC_MAX_RECURSION ) { +DMWARN_LIMIT ("%s: FEC: recursion too deep" , v->data_dev->name); +return -EIO ; + } + + fio->level++; +if (type ==DM_VERITY_BLOCK_TYPE_METADATA ) block += v->data_blocks;
@@ -470,7 +477,7 @@ int verity_fec_decode(struct dm_verity *if (r <0 ) { r =fec_decode_rsb (v, io, fio, rsb, offset, true);if (r <0 ) -return r; + goto done; }if (dest)
@@ -480,6 +487,8 @@ int verity_fec_decode(struct dm_verity * r =verity_for_bv_block (v, io, iter, fec_bv_copy); } +done: + fio->level--;return r; }
@@ -520,6 +529,7 @@ void verity_fec_init_io(struct dm_veritymemset (fio->bufs,0 ,sizeof (fio->bufs)); fio->nbufs =0 ; fio->output =NULL ; + fio->level =0 ; }/*
drivers/md/dm-verity-fec.h +4 -0
@@ -27,6 +27,9 @@#define DM_VERITY_FEC_BUF_MAX \ (1 << (PAGE_SHIFT - DM_VERITY_FEC_BUF_RS_BITS)) +/* maximum recursion level for verity_fec_decode */ +#define DM_VERITY_FEC_MAX_RECURSION 4 +#define DM_VERITY_OPT_FEC_DEV "use_fec_from_device"#define DM_VERITY_OPT_FEC_BLOCKS "fec_blocks"#define DM_VERITY_OPT_FEC_START "fec_start"
@@ -58,6 +61,7 @@ struct dm_verity_fec_io {unsigned nbufs;/* number of buffers allocated */ u8 *output;/* buffer for corrected output */ size_t output_pos; +unsigned level;/* recursion level */ };#ifdef CONFIG_DM_VERITY_FEC
Greg Kroah-Hartman
maintainerPATCH 21/152 dm verity fec: fix bufio leaks
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sami Tolvanen <[email protected]>
commit 86e3e83b443669dd2bcc5c8a83b23e3aa0694c0d upstream.
Buffers read through dm_bufio_read() were not released in all code paths.
--- drivers/md/dm-verity-fec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/md/dm-verity-fec.c +3 -3
@@ -146,8 +146,6 @@ static int fec_decode_bufs(struct dm_ver block =fec_buffer_rs_block (v, fio, n, i); res =fec_decode_rs8 (v, fio, block, &par[offset], neras);if (res <0 ) { -dm_bufio_release (buf); - r = res; goto error; }
@@ -172,6 +170,8 @@ static int fec_decode_bufs(struct dm_ver done: r = corrected; error: +dm_bufio_release (buf); +if (r <0 && neras)DMERR_LIMIT ("%s: FEC %llu: failed to correct: %d" , v->data_dev->name, (unsigned long long )rsb, r);
@@ -269,7 +269,7 @@ static int fec_read_bufs(struct dm_verit &is_zero) == 0) {/* skip known zero blocks entirely */ if (is_zero) -continue ; + goto done;/* * skip if we have already found the theoretical
Greg Kroah-Hartman
maintainerPATCH 22/152 ACPI / gpio: do not fall back to parsing _CRS when we get a deferral
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Dmitry Torokhov <[email protected]>
commit 693bdaa164b40b7aa6018b98af6f7e40dbd52457 upstream.
If, while locating GPIOs by name, we get probe deferral, we should immediately report it to caller rather than trying to fall back to parsing unnamed GPIOs from _CRS block.
--- drivers/gpio/gpiolib-acpi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/gpio/gpiolib-acpi.c +3 -1
@@ -571,8 +571,10 @@ struct gpio_desc *acpi_find_gpio(struct } desc =acpi_get_gpiod_by_index (adev, propname, idx, &info); -if (!IS_ERR (desc) || (PTR_ERR (desc) == -EPROBE_DEFER )) +if (!IS_ERR (desc))break ; +if (PTR_ERR (desc) == -EPROBE_DEFER ) +return ERR_CAST (desc); }/* Then from plain _CRS GPIOs */
Greg Kroah-Hartman
maintainerPATCH 23/152 Kbuild: use cc-disable-warning consistently for maybe-uninitialized
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Arnd Bergmann <[email protected]>
commit b334e19ae9381f12a7521976883022385d2b7eef upstream.
In commit a76bcf557ef4 ("Kbuild: enable -Wmaybe-uninitialized warning for "make W=1""), I reverted another change that happened to fix a problem with old compilers, and now we get this report again with old compilers (prior to gcc-4.8) and GCOV enabled:
cc1: warnings being treated as errors
drivers/gpu/drm/i915/intel_ringbuffer.c: In function 'intel_ring_setup_status_page':
drivers/gpu/drm/i915/intel_ringbuffer.c:438: error: 'mmio.reg' may be used uninitialized in this function At top level:
Quoted 1 line
Quoted 1 line
cc1: error: unrecognized command line option "-Wno-maybe-uninitialized"
The problem is that we turn off the warning conditionally in a number of places as we should, but one of them does it unconditionally. Instead, change it to call cc-disable-warning as we do elsewhere.
The original patch that caused it was merged into linux-4.7, then 4.8 removed the change and 4.9 brought it back, so we probably want a backport to 4.9 once this is merged.
Use a ':=' assignment instead of '=' to force the cc-disable-warning call to only be evaluated once instead of every time.
--- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Makefile +1 -1
@@ -370,7 +370,7 @@ LDFLAGS_MODULE = CFLAGS_KERNEL = AFLAGS_KERNEL = LDFLAGS_vmlinux = -CFLAGS_GCOV = -fprofile-arcs -ftest-coverage -fno-tree-loop-im -Wno-maybe-uninitialized +CFLAGS_GCOV := -fprofile-arcs -ftest-coverage -fno-tree-loop-im $(call cc-disable-warning,maybe-uninitialized,) CFLAGS_KCOV := $(call cc-option,-fsanitize-coverage=trace-pc,)
Greg Kroah-Hartman
maintainerPATCH 24/152 orangefs: move features validation to fix filesystem hang
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Martin Brandenburg <[email protected]>
commit cefdc26e86728812aea54248a534fd4a5da2a43d upstream.
Without this fix (and another to the userspace component itself described later), the kernel will be unable to process any OrangeFS requests after the userspace component is restarted (due to a crash or at the administrator's behest).
The bug here is that inside orangefs_remount, the orangefs_request_mutex is locked. When the userspace component restarts while the filesystem is mounted, it sends a ORANGEFS_DEV_REMOUNT_ALL ioctl to the device, which causes the kernel to send it a few requests aimed at synchronizing the state between the two. While this is happening the orangefs_request_mutex is locked to prevent any other requests going through.
This is only half of the bugfix. The other half is in the userspace component which outright ignores(!) requests made before it considers the filesystem remounted, which is after the ioctl returns. Of course the ioctl doesn't return until after the userspace component responds to the request it ignores. The userspace component has been changed to allow ORANGEFS_VFS_OP_FEATURES regardless of the mount status.
Mike Marshall says:
"I've tested this patch against the fixed userspace part. This patch is
real important, I hope it can make it into 4.11...
Here's what happens when the userspace daemon is restarted, without the patch:
=============================================
[ INFO: possible recursive locking detected ]
[ 4.10.0-00007-ge98bdb3 #1 Not tainted ]
---------------------------------------------
pvfs2-client-co/29032 is trying to acquire lock:
(orangefs_request_mutex){+.+.+.}, at: service_operation+0x3c7/0x7b0 [orangefs]
but task is already holding lock:
(orangefs_request_mutex){+.+.+.}, at: dispatch_ioctl_command+0x1bf/0x330 [orangefs]
CPU: 0 PID: 29032 Comm: pvfs2-client-co Not tainted 4.10.0-00007-ge98bdb3 #1
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.9.3-1.fc25 04/01/2014
Call Trace:
__lock_acquire+0x7eb/0x1290
lock_acquire+0xe8/0x1d0
mutex_lock_killable_nested+0x6f/0x6e0
service_operation+0x3c7/0x7b0 [orangefs]
orangefs_remount+0xea/0x150 [orangefs]
dispatch_ioctl_command+0x227/0x330 [orangefs]
orangefs_devreq_ioctl+0x29/0x70 [orangefs]
do_vfs_ioctl+0xa3/0x6e0
SyS_ioctl+0x79/0x90"--- fs/orangefs/super.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
fs/orangefs/super.c +7 -2
@@ -263,8 +263,13 @@ int orangefs_remount(struct orangefs_sb_if (!new_op)return -ENOMEM ; new_op->upcall.req.features.features =0 ; - ret =service_operation (new_op,"orangefs_features" ,0 ); - orangefs_features = new_op->downcall.resp.features.features; + ret =service_operation (new_op,"orangefs_features" , +ORANGEFS_OP_PRIORITY |ORANGEFS_OP_NO_MUTEX ); +if (!ret) + orangefs_features = + new_op->downcall.resp.features.features; +else + orangefs_features =0 ;op_release (new_op); }else { orangefs_features =0 ;
Greg Kroah-Hartman
maintainerPATCH 25/152 xfs: Honor FALLOC_FL_KEEP_SIZE when punching ends of files
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Calvin Owens <[email protected]>
commit 3dd09d5a8589c640abb49cfcf92b4ed669eafad1 upstream.
When punching past EOF on XFS, fallocate(mode=PUNCH_HOLE|KEEP_SIZE) will round the file size up to the nearest multiple of PAGE_SIZE:
calvinow@vm-disks/generic-xfs-1 ~$ dd if=/dev/urandom of=test bs=2048 count=1 calvinow@vm-disks/generic-xfs-1 ~$ stat test
Size: 2048 Blocks: 8 IO Block: 4096 regular file
calvinow@vm-disks/generic-xfs-1 ~$ fallocate -n -l 2048 -o 2048 -p test calvinow@vm-disks/generic-xfs-1 ~$ stat test
Size: 4096 Blocks: 8 IO Block: 4096 regular file
Commit 3c2bdc912a1cc050 ("xfs: kill xfs_zero_remaining_bytes") replaced xfs_zero_remaining_bytes() with calls to iomap helpers. The new helpers don't enforce that [pos,offset) lies strictly on [0,i_size) when being called from xfs_free_file_space(), so by "leaking" these ranges into xfs_zero_range() we get this buggy behavior.
Fix this by reintroducing the checks xfs_zero_remaining_bytes() did against i_size at the bottom of xfs_free_file_space().
--- fs/xfs/xfs_bmap_util.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
fs/xfs/xfs_bmap_util.c +9 -1
@@ -1318,8 +1318,16 @@ xfs_free_file_space(/* * Now that we've unmap all full blocks we'll have to zero out any * partial block at the beginning and/or end. xfs_zero_range is -* smart enough to skip any holes, including those we just created. +* smart enough to skip any holes, including those we just created, +* but we must take care not to zero beyond EOF and enlarge i_size. */ + +if (offset >=XFS_ISIZE (ip)) +return 0 ; + +if (offset + len >XFS_ISIZE (ip)) + len =XFS_ISIZE (ip) - offset; +return xfs_zero_range (ip, offset, len,NULL ); }
Greg Kroah-Hartman
maintainerPATCH 26/152 ring-buffer: Fix return value check in test_ringbuffer()
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Wei Yongjun <[email protected]>
commit 62277de758b155dc04b78f195a1cb5208c37b2df upstream.
In case of error, the function kthread_run() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR().
--- kernel/trace/ring_buffer.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
kernel/trace/ring_buffer.c +4 -4
@@ -4870,9 +4870,9 @@ static __init int test_ringbuffer(void) rb_data[cpu].cnt = cpu; rb_threads[cpu] =kthread_create (rb_test, &rb_data[cpu],"rbtester/%d" , cpu); -if (WARN_ON (!rb_threads[cpu])) { +if (WARN_ON (IS_ERR (rb_threads[cpu]))) {pr_cont ("FAILED\n" ); - ret =-1 ; + ret =PTR_ERR (rb_threads[cpu]); goto out_free; }
@@ -4882,9 +4882,9 @@ static __init int test_ringbuffer(void)/* Now create the rb hammer! */ rb_hammer =kthread_run (rb_hammer_test,NULL ,"rbhammer" ); -if (WARN_ON (!rb_hammer)) { +if (WARN_ON (IS_ERR (rb_hammer))) {pr_cont ("FAILED\n" ); - ret =-1 ; + ret =PTR_ERR (rb_hammer); goto out_free; }
Greg Kroah-Hartman
maintainerPATCH 27/152 mac80211: unconditionally start new netdev queues with iTXQ support
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Johannes Berg <[email protected]>
commit 7d65f82954dadbbe7b6e1aec7e07ad17bc6d958b upstream.
When internal mac80211 TXQs aren't supported, netdev queues must always started out started even when driver queues are stopped while the interface is added. This is necessary because with the internal TXQ support netdev queues are never stopped and packet scheduling/dropping is done in mac80211.
--- net/mac80211/iface.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
net/mac80211/iface.c +2 -1
@@ -726,7 +726,8 @@ int ieee80211_do_open(struct wireless_deieee80211_recalc_ps (local);if (sdata->vif.type ==NL80211_IFTYPE_MONITOR || - sdata->vif.type ==NL80211_IFTYPE_AP_VLAN ) { + sdata->vif.type ==NL80211_IFTYPE_AP_VLAN || + local->ops->wake_tx_queue) {/* XXX: for AP_VLAN, actually track AP queues */ netif_tx_start_all_queues (dev); }else if (dev) {
Greg Kroah-Hartman
maintainerPATCH 28/152 brcmfmac: use local iftype avoiding use-after-free of virtual interface
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Arend Van Spriel <[email protected]>
commit d77facb88448cdeaaa3adba5b9704a48ac2ac8d6 upstream.
A use-after-free was found using KASAN. In brcmf_p2p_del_if() the virtual interface is removed using call to brcmf_remove_interface(). After that the virtual interface instance has been freed and should not be referenced. Solve this by storing the nl80211 iftype in local variable, which is used in a couple of places anyway.
--- drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c +5 -3
@@ -2238,14 +2238,16 @@ int brcmf_p2p_del_vif(struct wiphy *wiphstruct brcmf_cfg80211_info *cfg =wiphy_priv (wiphy);struct brcmf_p2p_info *p2p = &cfg->p2p;struct brcmf_cfg80211_vif *vif; +enum nl80211_iftype iftype;bool wait_for_disable = false;int err;brcmf_dbg (TRACE ,"delete P2P vif\n" ); vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev); + iftype = vif->wdev.iftype;brcmf_cfg80211_arm_vif_event (cfg, vif); -switch (vif->wdev.iftype) { +switch (iftype) {case NL80211_IFTYPE_P2P_CLIENT :if (test_bit (BRCMF_VIF_STATUS_DISCONNECTING , &vif->sme_state)) wait_for_disable = true;
@@ -2275,7 +2277,7 @@ int brcmf_p2p_del_vif(struct wiphy *wiph BRCMF_P2P_DISABLE_TIMEOUT); err =0 ; -if (vif->wdev.iftype !=NL80211_IFTYPE_P2P_DEVICE ) { +if (iftype !=NL80211_IFTYPE_P2P_DEVICE ) {brcmf_vif_clear_mgmt_ies (vif); err =brcmf_p2p_release_p2p_if (vif); }
@@ -2291,7 +2293,7 @@ int brcmf_p2p_del_vif(struct wiphy *wiphbrcmf_remove_interface (vif->ifp, true);brcmf_cfg80211_arm_vif_event (cfg,NULL ); -if (vif->wdev.iftype !=NL80211_IFTYPE_P2P_DEVICE ) +if (iftype !=NL80211_IFTYPE_P2P_DEVICE ) p2p->bss_idx[P2PAPI_BSSCFG_CONNECTION ].vif =NULL ;return err;
Greg Kroah-Hartman
maintainerPATCH 29/152 metag/usercopy: Drop unused macros
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: James Hogan <[email protected]>
commit ef62a2d81f73d9cddef14bc3d9097a57010d551c upstream.
Metag's lib/usercopy.c has a bunch of copy_from_user macros for larger copies between 5 and 16 bytes which are completely unused. Before fixing zeroing lets drop these macros so there is less to fix.
--- arch/metag/lib/usercopy.c | 113 ---------------------------------------------- 1 file changed, 113 deletions(-)
arch/metag/lib/usercopy.c +0 -113
@@ -651,119 +651,6 @@ EXPORT_SYMBOL(__copy_user);#define __asm_copy_from_user_4 (to, from, ret) \ __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") -#define __asm_copy_from_user_5 (to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " GETB D1Ar1,[%1++]\n" \ - "4: SETB [%0++],D1Ar1\n", \ - "5: ADD %2,%2,#1\n" \ - " SETB [%0++],D1Ar1\n", \ - " .long 4b,5b\n") - -#define __asm_copy_from_user_6x_cont (to, from, ret,COPY ,FIXUP ,TENTRY ) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " GETW D1Ar1,[%1++]\n" \ - "4: SETW [%0++],D1Ar1\n" COPY, \ - "5: ADD %2,%2,#2\n" \ - " SETW [%0++],D1Ar1\n" FIXUP, \ - " .long 4b,5b\n" TENTRY) - -#define __asm_copy_from_user_6 (to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_7 (to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, \ - " GETB D1Ar1,[%1++]\n" \ - "6: SETB [%0++],D1Ar1\n", \ - "7: ADD %2,%2,#1\n" \ - " SETB [%0++],D1Ar1\n", \ - " .long 6b,7b\n") - -#define __asm_copy_from_user_8x_cont (to, from, ret,COPY ,FIXUP ,TENTRY ) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " GETD D1Ar1,[%1++]\n" \ - "4: SETD [%0++],D1Ar1\n" COPY, \ - "5: ADD %2,%2,#4\n" \ - " SETD [%0++],D1Ar1\n" FIXUP, \ - " .long 4b,5b\n" TENTRY) - -#define __asm_copy_from_user_8 (to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_9 (to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " GETB D1Ar1,[%1++]\n" \ - "6: SETB [%0++],D1Ar1\n", \ - "7: ADD %2,%2,#1\n" \ - " SETB [%0++],D1Ar1\n", \ - " .long 6b,7b\n") - -#define __asm_copy_from_user_10x_cont (to, from, ret,COPY ,FIXUP ,TENTRY ) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " GETW D1Ar1,[%1++]\n" \ - "6: SETW [%0++],D1Ar1\n" COPY, \ - "7: ADD %2,%2,#2\n" \ - " SETW [%0++],D1Ar1\n" FIXUP, \ - " .long 6b,7b\n" TENTRY) - -#define __asm_copy_from_user_10 (to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_11 (to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, \ - " GETB D1Ar1,[%1++]\n" \ - "8: SETB [%0++],D1Ar1\n", \ - "9: ADD %2,%2,#1\n" \ - " SETB [%0++],D1Ar1\n", \ - " .long 8b,9b\n") - -#define __asm_copy_from_user_12x_cont (to, from, ret,COPY ,FIXUP ,TENTRY ) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " GETD D1Ar1,[%1++]\n" \ - "6: SETD [%0++],D1Ar1\n" COPY, \ - "7: ADD %2,%2,#4\n" \ - " SETD [%0++],D1Ar1\n" FIXUP, \ - " .long 6b,7b\n" TENTRY) - -#define __asm_copy_from_user_12 (to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_13 (to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " GETB D1Ar1,[%1++]\n" \ - "8: SETB [%0++],D1Ar1\n", \ - "9: ADD %2,%2,#1\n" \ - " SETB [%0++],D1Ar1\n", \ - " .long 8b,9b\n") - -#define __asm_copy_from_user_14x_cont (to, from, ret,COPY ,FIXUP ,TENTRY ) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " GETW D1Ar1,[%1++]\n" \ - "8: SETW [%0++],D1Ar1\n" COPY, \ - "9: ADD %2,%2,#2\n" \ - " SETW [%0++],D1Ar1\n" FIXUP, \ - " .long 8b,9b\n" TENTRY) - -#define __asm_copy_from_user_14 (to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_15 (to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, \ - " GETB D1Ar1,[%1++]\n" \ - "10: SETB [%0++],D1Ar1\n", \ - "11: ADD %2,%2,#1\n" \ - " SETB [%0++],D1Ar1\n", \ - " .long 10b,11b\n") - -#define __asm_copy_from_user_16x_cont (to, from, ret,COPY ,FIXUP ,TENTRY ) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " GETD D1Ar1,[%1++]\n" \ - "8: SETD [%0++],D1Ar1\n" COPY, \ - "9: ADD %2,%2,#4\n" \ - " SETD [%0++],D1Ar1\n" FIXUP, \ - " .long 8b,9b\n" TENTRY) - -#define __asm_copy_from_user_16 (to, from, ret) \ - __asm_copy_from_user_16x_cont(to, from, ret, "", "", "")#define __asm_copy_from_user_8x64 (to, from, ret) \ asm volatile ( \
Greg Kroah-Hartman
maintainerPATCH 30/152 metag/usercopy: Fix alignment error checking
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: James Hogan <[email protected]>
commit 2257211942bbbf6c798ab70b487d7e62f7835a1a upstream.
Fix the error checking of the alignment adjustment code in raw_copy_from_user(), which mistakenly considers it safe to skip the error check when aligning the source buffer on a 2 or 4 byte boundary.
If the destination buffer was unaligned it may have started to copy using byte or word accesses, which could well be at the start of a new (valid) source page. This would result in it appearing to have copied 1 or 2 bytes at the end of the first (invalid) page rather than none at all.
--- arch/metag/lib/usercopy.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
arch/metag/lib/usercopy.c +4 -6
@@ -717,6 +717,8 @@ unsigned long __copy_user_zeroing(void *if ((unsigned long ) src &1 ) {__asm_copy_from_user_1 (dst, src, retn); n--; +if (retn) + goto copy_exception_bytes; }if ((unsigned long ) dst &1 ) {/* Worst case - byte copy */
@@ -730,6 +732,8 @@ unsigned long __copy_user_zeroing(void *if (((unsigned long ) src &2 ) && n >=2 ) {__asm_copy_from_user_2 (dst, src, retn); n -=2 ; +if (retn) + goto copy_exception_bytes; }if ((unsigned long ) dst &2 ) {/* Second worst case - word copy */
@@ -741,12 +745,6 @@ unsigned long __copy_user_zeroing(void * } } -/* We only need one check after the unalignment-adjustments, -because if both adjustments were done, either both or -neither reference had an exception. */ -if (retn !=0 ) - goto copy_exception_bytes; -#ifdef USE_RAPF /* 64 bit copy loop */ if (!(((unsigned long ) src | (unsigned long ) dst) &7 )) {
Greg Kroah-Hartman
maintainerPATCH 31/152 metag/usercopy: Add early abort to copy_to_user
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: James Hogan <[email protected]>
commit fb8ea062a8f2e85256e13f55696c5c5f0dfdcc8b upstream.
When copying to userland on Meta, if any faults are encountered immediately abort the copy instead of continuing on and repeatedly faulting, and worse potentially copying further bytes successfully to subsequent valid pages.
--- arch/metag/lib/usercopy.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
arch/metag/lib/usercopy.c +20 -0
@@ -538,23 +538,31 @@ unsigned long __copy_user(void __user *pif ((unsigned long ) src &1 ) {__asm_copy_to_user_1 (dst, src, retn); n--; +if (retn) +return retn + n; }if ((unsigned long ) dst &1 ) {/* Worst case - byte copy */ while (n >0 ) {__asm_copy_to_user_1 (dst, src, retn); n--; +if (retn) +return retn + n; } }if (((unsigned long ) src &2 ) && n >=2 ) {__asm_copy_to_user_2 (dst, src, retn); n -=2 ; +if (retn) +return retn + n; }if ((unsigned long ) dst &2 ) {/* Second worst case - word copy */ while (n >=2 ) {__asm_copy_to_user_2 (dst, src, retn); n -=2 ; +if (retn) +return retn + n; } }
@@ -569,6 +577,8 @@ unsigned long __copy_user(void __user *pwhile (n >=8 ) {__asm_copy_to_user_8x64 (dst, src, retn); n -=8 ; +if (retn) +return retn + n; } }if (n >=RAPF_MIN_BUF_SIZE ) {
@@ -581,6 +591,8 @@ unsigned long __copy_user(void __user *pwhile (n >=8 ) {__asm_copy_to_user_8x64 (dst, src, retn); n -=8 ; +if (retn) +return retn + n; } }#endif
@@ -588,11 +600,15 @@ unsigned long __copy_user(void __user *pwhile (n >=16 ) {__asm_copy_to_user_16 (dst, src, retn); n -=16 ; +if (retn) +return retn + n; }while (n >=4 ) {__asm_copy_to_user_4 (dst, src, retn); n -=4 ; +if (retn) +return retn + n; }switch (n) {
@@ -609,6 +625,10 @@ unsigned long __copy_user(void __user *pbreak ; } +/* +* If we get here, retn correctly reflects the number of failing +* bytes. +*/ return retn; }EXPORT_SYMBOL (__copy_user);
Greg Kroah-Hartman
maintainerPATCH 32/152 metag/usercopy: Zero rest of buffer from copy_from_user
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: James Hogan <[email protected]>
commit 563ddc1076109f2b3f88e6d355eab7b6fd4662cb upstream.
Currently we try to zero the destination for a failed read from userland in fixup code in the usercopy.c macros. The rest of the destination buffer is then zeroed from __copy_user_zeroing(), which is used for both copy_from_user() and __copy_from_user().
Unfortunately we fail to zero in the fixup code as D1Ar1 is set to 0 before the fixup code entry labels, and __copy_from_user() shouldn't even be zeroing the rest of the buffer.
Move the zeroing out into copy_from_user() and rename __copy_user_zeroing() to raw_copy_from_user() since it no longer does any zeroing. This also conveniently matches the name needed for RAW_COPY_USER support in a later patch.
--- arch/metag/include/asm/uaccess.h | 15 +++++----- arch/metag/lib/usercopy.c | 57 ++++++++++++--------------------------- 2 files changed, 26 insertions(+), 46 deletions(-)
arch/metag/include/asm/uaccess.h +8 -7
@@ -197,20 +197,21 @@ extern long __must_check strnlen_user(co#define strlen_user (str) strnlen_user(str, 32767) -extern unsigned long __must_check __copy_user_zeroing (void *to, -const void __user *from, -unsigned long n); +extern unsigned long raw_copy_from_user (void *to,const void __user *from, +unsigned long n);static inline unsigned long copy_from_user (void *to,const void __user *from,unsigned long n) { +unsigned long res = n;if (likely (access_ok (VERIFY_READ , from, n))) -return __copy_user_zeroing (to, from, n); -memset (to,0 , n); -return n; + res =raw_copy_from_user (to, from, n); +if (unlikely (res)) +memset (to + (n - res),0 , res); +return res; } -#define __copy_from_user (to, from, n) __copy_user_zeroing(to, from, n) +#define __copy_from_user (to, from, n) raw_copy_from_user(to, from, n)#define __copy_from_user_inatomic __copy_from_user extern unsigned long __must_check __copy_user(void __user *to,
arch/metag/lib/usercopy.c +18 -39
154 lines not on this page · raw message
Greg Kroah-Hartman
maintainerPATCH 33/152 metag/usercopy: Set flags before ADDZ
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: James Hogan <[email protected]>
commit fd40eee1290ad7add7aa665e3ce6b0f9fe9734b4 upstream.
The fixup code for the copy_to_user rapf loops reads TXStatus.LSM_STEP to decide how far to rewind the source pointer. There is a special case for the last execution of an MGETL/MGETD, since it leaves LSM_STEP=0 even though the number of MGETLs/MGETDs attempted was 4. This uses ADDZ which is conditional upon the Z condition flag, but the AND instruction which masked the TXStatus.LSM_STEP field didn't set the condition flags based on the result.
Fix that now by using ANDS which does set the flags, and also marking the condition codes as clobbered by the inline assembly.
--- arch/metag/lib/usercopy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/metag/lib/usercopy.c +4 -4
@@ -315,7 +315,7 @@ " .previous\n" \ : "=r" (to), "=r" (from), "=r" (ret), "=d" (n) \ : "0" (to), "1" (from), "2" (ret), "3" (n) \ -: " D1Ar1", " D0Ar2", " memory") +: " D1Ar1", " D0Ar2", " cc", " memory") /* rewind 'to' and 'from' pointers when a fault occurs *
@@ -341,7 +341,7 @@#define __asm_copy_to_user_64bit_rapf_loop (to, from, ret, n, id)\ __asm_copy_user_64bit_rapf_loop(to, from, ret, n, id, \ "LSR D0Ar2, D0Ar2, #8\n" \ - "AND D0Ar2, D0Ar2, #0x7\n" \ + "ANDS D0Ar2, D0Ar2, #0x7\n" \ "ADDZ D0Ar2, D0Ar2, #4\n" \ "SUB D0Ar2, D0Ar2, #1\n" \ "MOV D1Ar1, #4\n" \
@@ -486,7 +486,7 @@ " .previous\n" \ : "=r" (to), "=r" (from), "=r" (ret), "=d" (n) \ : "0" (to), "1" (from), "2" (ret), "3" (n) \ -: " D1Ar1", " D0Ar2", " memory") +: " D1Ar1", " D0Ar2", " cc", " memory") /* rewind 'to' and 'from' pointers when a fault occurs *
@@ -512,7 +512,7 @@#define __asm_copy_to_user_32bit_rapf_loop (to, from, ret, n, id)\ __asm_copy_user_32bit_rapf_loop(to, from, ret, n, id, \ "LSR D0Ar2, D0Ar2, #8\n" \ - "AND D0Ar2, D0Ar2, #0x7\n" \ + "ANDS D0Ar2, D0Ar2, #0x7\n" \ "ADDZ D0Ar2, D0Ar2, #4\n" \ "SUB D0Ar2, D0Ar2, #1\n" \ "MOV D1Ar1, #4\n" \
Greg Kroah-Hartman
maintainerPATCH 34/152 metag/usercopy: Fix src fixup in from user rapf loops
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: James Hogan <[email protected]>
commit 2c0b1df88b987a12d95ea1d6beaf01894f3cc725 upstream.
The fixup code to rewind the source pointer in __asm_copy_from_user_{32,64}bit_rapf_loop() always rewound the source by a single unit (4 or 8 bytes), however this is insufficient if the fault didn't occur on the first load in the loop, as the source pointer will have been incremented but nothing will have been stored until all 4 register [pairs] are loaded.
Read the LSM_STEP field of TXSTATUS (which is already loaded into a register), a bit like the copy_to_user versions, to determine how many iterations of MGET[DL] have taken place, all of which need rewinding.
--- arch/metag/lib/usercopy.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-)
arch/metag/lib/usercopy.c +28 -8
@@ -687,29 +687,49 @@ EXPORT_SYMBOL(__copy_user);* * Rationale: * A fault occurs while reading from user buffer, which is the -* source. Since the fault is at a single address, we only -* need to rewind by 8 bytes. +* source. * Since we don't write to kernel buffer until we read first, * the kernel buffer is at the right state and needn't be -* corrected. +* corrected, but the source must be rewound to the beginning of +* the block, which is LSM_STEP*8 bytes. +* LSM_STEP is bits 10:8 in TXSTATUS which is already read +* and stored in D0Ar2 +* +* NOTE: If a fault occurs at the last operation in M{G,S}ETL +* LSM_STEP will be 0. ie: we do 4 writes in our case, if +* a fault happens at the 4th write, LSM_STEP will be 0 +* instead of 4. The code copes with that. */ #define __asm_copy_from_user_64bit_rapf_loop (to, from, ret, n, id) \ __asm_copy_user_64bit_rapf_loop(to, from, ret, n, id, \ - "SUB %1, %1, #8\n") + "LSR D0Ar2, D0Ar2, #5\n" \ + "ANDS D0Ar2, D0Ar2, #0x38\n" \ + "ADDZ D0Ar2, D0Ar2, #32\n" \ + "SUB %1, %1, D0Ar2\n")/* rewind 'from' pointer when a fault occurs * * Rationale: * A fault occurs while reading from user buffer, which is the -* source. Since the fault is at a single address, we only -* need to rewind by 4 bytes. +* source. * Since we don't write to kernel buffer until we read first, * the kernel buffer is at the right state and needn't be -* corrected. +* corrected, but the source must be rewound to the beginning of +* the block, which is LSM_STEP*4 bytes. +* LSM_STEP is bits 10:8 in TXSTATUS which is already read +* and stored in D0Ar2 +* +* NOTE: If a fault occurs at the last operation in M{G,S}ETL +* LSM_STEP will be 0. ie: we do 4 writes in our case, if +* a fault happens at the 4th write, LSM_STEP will be 0 +* instead of 4. The code copes with that. */ #define __asm_copy_from_user_32bit_rapf_loop (to, from, ret, n, id) \ __asm_copy_user_32bit_rapf_loop(to, from, ret, n, id, \ - "SUB %1, %1, #4\n") + "LSR D0Ar2, D0Ar2, #6\n" \ + "ANDS D0Ar2, D0Ar2, #0x1c\n" \ + "ADDZ D0Ar2, D0Ar2, #16\n" \ + "SUB %1, %1, D0Ar2\n")/*
Greg Kroah-Hartman
maintainerPATCH 35/152 metag/usercopy: Add missing fixups
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: James Hogan <[email protected]>
commit b884a190afcecdbef34ca508ea5ee88bb7c77861 upstream.
The rapf copy loops in the Meta usercopy code is missing some extable entries for HTP cores with unaligned access checking enabled, where faults occur on the instruction immediately after the faulting access.
Add the fixup labels and extable entries for these cases so that corner case user copy failures don't cause kernel crashes.
--- arch/metag/lib/usercopy.c | 72 ++++++++++++++++++++++++++++++---------------- 1 file changed, 48 insertions(+), 24 deletions(-)
arch/metag/lib/usercopy.c +48 -24
@@ -259,27 +259,31 @@"MGETL D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \"22:\n" \"MSETL [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ -"SUB %3, %3, #32\n" \"23:\n" \ -"MGETL D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ +"SUB %3, %3, #32\n" \"24:\n" \ +"MGETL D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ +"25:\n" \"MSETL [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ +"26:\n" \"SUB %3, %3, #32\n" \"DCACHE [%1+#-64], D0Ar6\n" \"BR $Lloop" id"\n" \ \"MOV RAPF, %1\n" \ -"25:\n" \ +"27:\n" \"MGETL D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ -"26:\n" \ +"28:\n" \"MSETL [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ +"29:\n" \"SUB %3, %3, #32\n" \ -"27:\n" \ +"30:\n" \"MGETL D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ -"28:\n" \ +"31:\n" \"MSETL [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ +"32:\n" \"SUB %0, %0, #8\n" \ -"29:\n" \ +"33:\n" \"SETL [%0++], D0.7, D1.7\n" \"SUB %3, %3, #32\n" \"1:" \
@@ -311,7 +315,11 @@ " .long 26b,3b\n" \ " .long 27b,3b\n" \ " .long 28b,3b\n" \ - " .long 29b,4b\n" \ + " .long 29b,3b\n" \ + " .long 30b,3b\n" \ + " .long 31b,3b\n" \ + " .long 32b,3b\n" \ + " .long 33b,4b\n" \ " .previous\n" \ : "=r" (to), "=r" (from), "=r" (ret), "=d" (n) \ : "0" (to), "1" (from), "2" (ret), "3" (n) \
@@ -402,47 +410,55 @@"MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \"22:\n" \"MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ -"SUB %3, %3, #16\n" \"23:\n" \ -"MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ -"24:\n" \ -"MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \"SUB %3, %3, #16\n" \ -"25:\n" \ +"24:\n" \"MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ -"26:\n" \ +"25:\n" \"MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ +"26:\n" \"SUB %3, %3, #16\n" \"27:\n" \"MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \"28:\n" \"MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ +"29:\n" \ +"SUB %3, %3, #16\n" \ +"30:\n" \ +"MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ +"31:\n" \ +"MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ +"32:\n" \"SUB %3, %3, #16\n" \"DCACHE [%1+#-64], D0Ar6\n" \"BR $Lloop" id"\n" \ \"MOV RAPF, %1\n" \ -"29:\n" \ +"33:\n" \"MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ -"30:\n" \ +"34:\n" \"MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ +"35:\n" \"SUB %3, %3, #16\n" \ -"31:\n" \ +"36:\n" \"MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ -"32:\n" \ +"37:\n" \"MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ +"38:\n" \"SUB %3, %3, #16\n" \ -"33:\n" \ +"39:\n" \"MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ -"34:\n" \ +"40:\n" \"MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ +"41:\n" \"SUB %3, %3, #16\n" \ -"35:\n" \ +"42:\n" \"MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \ -"36:\n" \ +"43:\n" \"MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \ +"44:\n" \"SUB %0, %0, #4\n" \ -"37:\n" \ +"45:\n" \"SETD [%0++], D0.7\n" \"SUB %3, %3, #16\n" \"1:" \
@@ -482,7 +498,15 @@ " .long 34b,3b\n" \ " .long 35b,3b\n" \ " .long 36b,3b\n" \ - " .long 37b,4b\n" \ + " .long 37b,3b\n" \ + " .long 38b,3b\n" \ + " .long 39b,3b\n" \ + " .long 40b,3b\n" \ + " .long 41b,3b\n" \ + " .long 42b,3b\n" \ + " .long 43b,3b\n" \ + " .long 44b,3b\n" \ + " .long 45b,4b\n" \ " .previous\n" \ : "=r" (to), "=r" (from), "=r" (ret), "=d" (n) \ : "0" (to), "1" (from), "2" (ret), "3" (n) \
Greg Kroah-Hartman
maintainerPATCH 36/152 powerpc: Disable HFSCR[TM] if TM is not supported
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Benjamin Herrenschmidt <[email protected]>
commit 7ed23e1bae8bf7e37fd555066550a00b95a3a98b upstream.
On Power8 & Power9 the early CPU inititialisation in __init_HFSCR() turns on HFSCR[TM] (Hypervisor Facility Status and Control Register [Transactional Memory]), but that doesn't take into account that TM might be disabled by CPU features, or disabled by the kernel being built with CONFIG_PPC_TRANSACTIONAL_MEM=n.
So later in boot, when we have setup the CPU features, clear HSCR[TM] if the TM CPU feature has been disabled. We use CPU_FTR_TM_COMP to account for the CONFIG_PPC_TRANSACTIONAL_MEM=n case.
Without this a KVM guest might try use TM, even if told not to, and cause an oops in the host kernel. Typically the oops is seen in __kvmppc_vcore_entry() and may or may not be fatal to the host, but is always bad news.
In practice all shipping CPU revisions do support TM, and all host kernels we are aware of build with TM support enabled, so no one should actually be able to hit this in the wild.
--- arch/powerpc/kernel/setup_64.c | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/powerpc/kernel/setup_64.c +9 -0
@@ -245,6 +245,15 @@ static void cpu_ready_for_interrupts(voimtspr (SPRN_LPCR , lpcr |LPCR_AIL_3 ); } +/* +* Fixup HFSCR:TM based on CPU features. The bit is set by our +* early asm init because at that point we haven't updated our +* CPU features from firmware and device-tree. Here we have, +* so let's do it. +*/ +if (cpu_has_feature (CPU_FTR_HVMODE ) && !cpu_has_feature (CPU_FTR_TM_COMP )) +mtspr (SPRN_HFSCR ,mfspr (SPRN_HFSCR ) & ~HFSCR_TM ); +/* Set IR and DR in PACA MSR */ get_paca ()->kernel_msr =MSR_KERNEL ; }
Greg Kroah-Hartman
maintainerPATCH 37/152 powerpc/mm: Add missing global TLB invalidate if cxl is active
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Frederic Barrat <[email protected]>
commit 88b1bf7268f56887ca88eb09c6fb0f4fc970121a upstream.
Commit 4c6d9acce1f4 ("powerpc/mm: Add hooks for cxl") converted local TLB invalidates to global if the cxl driver is active. This is necessary because the CAPP snoops invalidations to forward them to the PSL on the cxl adapter. However one path was forgotten. native_flush_hash_range() still does local TLB invalidates, as found out the hard way recently.
This patch fixes it by following the same logic as previously: if the cxl driver is active, the local TLB invalidates are 'upgraded' to global.
--- arch/powerpc/mm/hash_native_64.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
arch/powerpc/mm/hash_native_64.c +5 -2
@@ -636,6 +636,10 @@ static void native_flush_hash_range(unsiunsigned long psize = batch->psize;int ssize = batch->ssize;int i; +unsigned int use_local; + + use_local = local &&mmu_has_feature (MMU_FTR_TLBIEL ) && + mmu_psize_defs[psize].tlbiel && !cxl_ctx_in_use ();local_irq_save (flags);
@@ -665,8 +669,7 @@ static void native_flush_hash_range(unsi }pte_iterate_hashed_end (); } -if (mmu_has_feature (MMU_FTR_TLBIEL ) && - mmu_psize_defs[psize].tlbiel && local) { +if (use_local) { asmvolatile ("ptesync" :::"memory" );for (i =0 ; i < number; i++) { vpn = batch->vpn[i];
Greg Kroah-Hartman
maintainerPATCH 38/152 powerpc/64: Fix flush_(d|i)cache_range() called from modules
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Oliver O'Halloran <[email protected]>
commit 8f5f525d5b83f7d76a6baf9c4e94d4bf312ea7f6 upstream.
When the kernel is compiled to use 64bit ABIv2 the _GLOBAL() macro does not include a global entry point. A function's global entry point is used when the function is called from a different TOC context and in the kernel this typically means a call from a module into the vmlinux (or vice-versa).
There are a few exported asm functions declared with _GLOBAL() and calling them from a module will likely crash the kernel since any TOC relative load will yield garbage.
flush_icache_range() and flush_dcache_range() are both exported to modules, and use the TOC, so must use _GLOBAL_TOC().
--- arch/powerpc/kernel/misc_64.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/powerpc/kernel/misc_64.S +2 -2
@@ -67,7 +67,7 @@ PPC64_CACHES: * flush all bytes from start through stop-1 inclusive */ -_GLOBAL(flush_icache_range) +_GLOBAL_TOC(flush_icache_range) BEGIN_FTR_SECTION PURGE_PREFETCHED_INS blr
@@ -120,7 +120,7 @@ EXPORT_SYMBOL(flush_icache_range) * * flush all bytes from start to stop-1 inclusive */ -_GLOBAL(flush_dcache_range) +_GLOBAL_TOC(flush_dcache_range) /* * Flush the data cache to memory
Greg Kroah-Hartman
maintainerPATCH 39/152 powerpc: Dont try to fix up misaligned load-with-reservation instructions
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Paul Mackerras <[email protected]>
commit 48fe9e9488743eec9b7c1addd3c93f12f2123d54 upstream.
In the past, there was only one load-with-reservation instruction, lwarx, and if a program attempted a lwarx on a misaligned address, it would take an alignment interrupt and the kernel handler would emulate it as though it was lwzx, which was not really correct, but benign since it is loading the right amount of data, and the lwarx should be paired with a stwcx. to the same address, which would also cause an alignment interrupt which would result in a SIGBUS being delivered to the process.
We now have 5 different sizes of load-with-reservation instruction. Of those, lharx and ldarx cause an immediate SIGBUS by luck since their entries in aligninfo[] overlap instructions which were not fixed up, but lqarx overlaps with lhz and will be emulated as such. lbarx can never generate an alignment interrupt since it only operates on 1 byte.
To straighten this out and fix the lqarx case, this adds code to detect the l[hwdq]arx instructions and return without fixing them up, resulting in a SIGBUS being delivered to the process.
--- arch/powerpc/kernel/align.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-)
arch/powerpc/kernel/align.c +19 -8
@@ -807,14 +807,25 @@ int fix_alignment(struct pt_regs *regs) nb = aligninfo[instr].len; flags = aligninfo[instr].flags; -/* ldbrx/stdbrx overlap lfs/stfs in the DSISR unfortunately */ -if (IS_XFORM (instruction) && ((instruction >>1 ) &0x3ff ) ==532 ) { - nb =8 ; - flags =LD +SW ; - }else if (IS_XFORM (instruction) && - ((instruction >>1 ) &0x3ff ) ==660 ) { - nb =8 ; - flags =ST +SW ; +/* +* Handle some cases which give overlaps in the DSISR values. +*/ +if (IS_XFORM (instruction)) { +switch (get_xop (instruction)) { +case 532 :/* ldbrx */ + nb =8 ; + flags =LD +SW ; +break ; +case 660 :/* stdbrx */ + nb =8 ; + flags =ST +SW ; +break ; +case 20 :/* lwarx */ +case 84 :/* ldarx */ +case 116 :/* lharx */ +case 276 :/* lqarx */ +return 0 ;/* not emulated ever */ + } }/* Byteswap little endian loads and stores */
Greg Kroah-Hartman
maintainerPATCH 40/152 powerpc/crypto/crc32c-vpmsum: Fix missing preempt_disable()
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Michael Ellerman <[email protected]>
commit 4749228f022893faf54a3dbc70796f78b7d4f342 upstream.
In crc32c_vpmsum() we call enable_kernel_altivec() without first disabling preemption, which is not allowed:
WARNING: CPU: 9 PID: 2949 at ../arch/powerpc/kernel/process.c:277 enable_kernel_altivec+0x100/0x120
Modules linked in: dm_thin_pool dm_persistent_data dm_bio_prison dm_bufio libcrc32c vmx_crypto ...
CPU: 9 PID: 2949 Comm: docker Not tainted 4.11.0-rc5-compiler_gcc-6.3.1-00033-g308ac7563944 #381
...
NIP [c00000000001e320] enable_kernel_altivec+0x100/0x120
LR [d000000003df0910] crc32c_vpmsum+0x108/0x150 [crc32c_vpmsum]
Call Trace:
0xc138fd09 (unreliable)
crc32c_vpmsum+0x108/0x150 [crc32c_vpmsum]
crc32c_vpmsum_update+0x3c/0x60 [crc32c_vpmsum]
crypto_shash_update+0x88/0x1c0
crc32c+0x64/0x90 [libcrc32c]
dm_bm_checksum+0x48/0x80 [dm_persistent_data]
sb_check+0x84/0x120 [dm_thin_pool]
dm_bm_validate_buffer.isra.0+0xc0/0x1b0 [dm_persistent_data]
dm_bm_read_lock+0x80/0xf0 [dm_persistent_data]
__create_persistent_data_objects+0x16c/0x810 [dm_thin_pool]
dm_pool_metadata_open+0xb0/0x1a0 [dm_thin_pool]
pool_ctr+0x4cc/0xb60 [dm_thin_pool]
dm_table_add_target+0x16c/0x3c0
table_load+0x184/0x400
ctl_ioctl+0x2f0/0x560
dm_ctl_ioctl+0x38/0x50
do_vfs_ioctl+0xd8/0x920
SyS_ioctl+0x68/0xc0
system_call+0x38/0xfcIt used to be sufficient just to call pagefault_disable(), because that also disabled preemption. But the two were decoupled in commit 8222dbe21e79 ("sched/preempt, mm/fault: Decouple preemption from the page fault logic") in mid 2015.
So add the missing preempt_disable/enable(). We should also call disable_kernel_fp(), although it does nothing by default, there is a debug switch to make it active and all enables should be paired with disables.
--- arch/powerpc/crypto/crc32c-vpmsum_glue.c | 3 +++ 1 file changed, 3 insertions(+)
arch/powerpc/crypto/crc32c-vpmsum_glue.c +3 -0
@@ -33,10 +33,13 @@ static u32 crc32c_vpmsum(u32 crc, unsign }if (len & ~VMX_ALIGN_MASK ) { +preempt_disable ();pagefault_disable ();enable_kernel_altivec (); crc =__crc32c_vpmsum (crc, p, len & ~VMX_ALIGN_MASK ); +disable_kernel_altivec ();pagefault_enable (); +preempt_enable (); } tail = len &VMX_ALIGN_MASK ;
Greg Kroah-Hartman
maintainerPATCH 42/152 nios2: reserve boot memory for device tree
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tobias Klauser <[email protected]>
commit 921d701e6f31e1ffaca3560416af1aa04edb4c4f upstream.
Make sure to reserve the boot memory for the flattened device tree. Otherwise it might get overwritten, e.g. when initial_boot_params is copied, leading to a corrupted FDT and a boot hang/crash:
bootconsole [early0] enabled
Early console on uart16650 initialized at 0xf8001600
OF: fdt: Error -11 processing FDT
Kernel panic - not syncing: setup_cpuinfo: No CPU found in devicetree! ---[ end Kernel panic - not syncing: setup_cpuinfo: No CPU found in devicetree!
Guenter Roeck says:
Quoted 8 lines
I think I found the problem. In
unflatten_and_copy_device_tree(), with added debug information:OF: fdt: initial_boot_params=c861e400, dt=c861f000 size=28874 (
0x70ca)... and then
initial_boot_paramsis copied to dt, which results in corrupted fdt since the memory overlaps. Looks like theinitial_boot_paramsmemory is not reserved and (re-)allocated byearly_init_dt_alloc_memory_arch().
Reference: http://lkml.kernel.org/r/[email protected]
--- arch/nios2/kernel/prom.c | 7 +++++++ arch/nios2/kernel/setup.c | 3 +++ 2 files changed, 10 insertions(+)
arch/nios2/kernel/prom.c +7 -0
@@ -48,6 +48,13 @@ void * __init early_init_dt_alloc_memoryreturn alloc_bootmem_align (size, align); } +int __init early_init_dt_reserve_memory_arch (phys_addr_t base,phys_addr_t size, +bool nomap) +{ +reserve_bootmem (base, size,BOOTMEM_DEFAULT ); +return 0 ; +} +void __init early_init_devtree (void *params) {__be32 *dtb = (u32 *)__dtb_start;
arch/nios2/kernel/setup.c +3 -0
@@ -195,6 +195,9 @@ void __init setup_arch(char **cmdline_p) }#endif /* CONFIG_BLK_DEV_INITRD */ +early_init_fdt_reserve_self (); +early_init_fdt_scan_reserved_mem (); +unflatten_and_copy_device_tree ();setup_cpuinfo ();
Greg Kroah-Hartman
maintainerPATCH 43/152 xtensa: make __pa work with uncached KSEG addresses
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Max Filippov <[email protected]>
commit 2b83878dd74a7c73bedcb6600663c1c46836e8af upstream.
When __pa is applied to virtual address in uncached KSEG region the result is incorrect. Fix it by checking if the original address is in the uncached KSEG and adjusting the result. It looks better than masking off bits because pfn_valid would correctly work with new __pa results and it may be made working in noMMU case, once we get definition for uncached memory view.
This is required for the dma_common_mmap and DMA debug code to work
correctly: they both indirectly use __pa with coherent DMA addresses. In case of DMA debug the visible effect is false reports that an address mapped for DMA is accessed by CPU.
--- arch/xtensa/include/asm/page.h | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/xtensa/include/asm/page.h +13 -0
@@ -164,8 +164,21 @@ void copy_user_highpage(struct page *to,#define ARCH_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) +#ifdef CONFIG_MMU +static inline unsigned long ___pa (unsigned long va) +{ +unsigned long off = va -PAGE_OFFSET ; + +if (off >=XCHAL_KSEG_SIZE ) + off -=XCHAL_KSEG_SIZE ; + +return off +PHYS_OFFSET ; +} +#define __pa (x) ___pa((unsigned long)(x)) +#else #define __pa (x) \ ((unsigned long) (x) - PAGE_OFFSET + PHYS_OFFSET) +#endif #define __va (x) \ ((void *)((unsigned long) (x) - PHYS_OFFSET + PAGE_OFFSET))#define pfn_valid (pfn) \
Greg Kroah-Hartman
maintainerPATCH 44/152 s390/decompressor: fix initrd corruption caused by bss clear
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Marcelo Henrique Cerri <[email protected]>
commit d82c0d12c92705ef468683c9b7a8298dd61ed191 upstream.
Reorder the operations in decompress_kernel() to ensure initrd is moved to a safe location before the bss section is zeroed.
During decompression bss can overlap with the initrd and this can corrupt the initrd contents depending on the size of the compressed kernel (which affects where the initrd is placed by the bootloader) and the size of the bss section of the decompressor.
Also use the correct initrd size when checking for overlaps with parmblock.
--- arch/s390/boot/compressed/misc.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-)
arch/s390/boot/compressed/misc.c +19 -16
@@ -141,31 +141,34 @@ static void check_ipl_parmblock(void *stunsigned long decompress_kernel (void ) { -unsigned long output_addr; -unsigned char *output; +void *output, *kernel_end; - output_addr = ((unsigned long ) &_end +HEAP_SIZE +4095UL ) &-4096UL ; -check_ipl_parmblock ((void *)0 , output_addr + SZ__bss_start); -memset (&_bss,0 , &_ebss - &_bss); - free_mem_ptr = (unsigned long )&_end; - free_mem_end_ptr = free_mem_ptr +HEAP_SIZE ; - output = (unsigned char *) output_addr; + output = (void *)ALIGN ((unsigned long ) &_end +HEAP_SIZE ,PAGE_SIZE ); + kernel_end = output + SZ__bss_start; +check_ipl_parmblock ((void *)0 , (unsigned long ) kernel_end);#ifdef CONFIG_BLK_DEV_INITRD /* * Move the initrd right behind the end of the decompressed -* kernel image. +* kernel image. This also prevents initrd corruption caused by +* bss clearing since kernel_end will always be located behind the +* current bss section.. */ -if (INITRD_START &&INITRD_SIZE && -INITRD_START < (unsigned long ) output + SZ__bss_start) { -check_ipl_parmblock (output + SZ__bss_start, -INITRD_START +INITRD_SIZE ); -memmove (output + SZ__bss_start, - (void *)INITRD_START ,INITRD_SIZE ); -INITRD_START = (unsigned long ) output + SZ__bss_start; +if (INITRD_START &&INITRD_SIZE && kernel_end > (void *)INITRD_START ) { +check_ipl_parmblock (kernel_end,INITRD_SIZE ); +memmove (kernel_end, (void *)INITRD_START ,INITRD_SIZE ); +INITRD_START = (unsigned long ) kernel_end; }#endif +/* +* Clear bss section. free_mem_ptr and free_mem_end_ptr need to be +* initialized afterwards since they reside in bss. +*/ +memset (&_bss,0 , &_ebss - &_bss); + free_mem_ptr = (unsigned long ) &_end; + free_mem_end_ptr = free_mem_ptr +HEAP_SIZE ; +puts ("Uncompressing Linux... " );__decompress (input_data, input_len,NULL ,NULL , output,0 ,NULL , error);puts ("Ok, booting the kernel.\n" );
Greg Kroah-Hartman
maintainerPATCH 45/152 s390/uaccess: get_user() should zero on failure (again)
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Heiko Carstens <[email protected]>
commit d09c5373e8e4eaaa09233552cbf75dc4c4f21203 upstream.
Commit fd2d2b191fe7 ("s390: get_user() should zero on failure") intended to fix s390's get_user() implementation which did not zero the target operand if the read from user space faulted. Unfortunately the patch has no effect: the corresponding inline assembly specifies that the operand is only written to ("=") and the previous value is discarded.
Therefore the compiler is free to and actually does omit the zero initialization.
To fix this simply change the contraint modifier to "+", so the compiler cannot omit the initialization anymore.
--- arch/s390/include/asm/uaccess.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/s390/include/asm/uaccess.h +1 -1
@@ -144,7 +144,7 @@ unsigned long __must_check __copy_to_use" jg 2b\n" \".popsection\n" \ EX_TABLE(0b,3b) EX_TABLE(1b,3b) \ - : "=d" (__rc), "=Q" (*(to)) \ + : "=d" (__rc), "+Q" (*(to)) \: " d" (size), " Q " (*(from)), \ " d" (__reg0), " K " (-EFAULT) \ : " cc"); \
Greg Kroah-Hartman
maintainerPATCH 46/152 MIPS: Force o32 fp64 support on 32bit MIPS64r6 kernels
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: James Hogan <[email protected]>
commit 2e6c7747730296a6d4fd700894286db1132598c4 upstream.
When a 32-bit kernel is configured to support MIPS64r6 (CPU_MIPS64_R6), MIPS_O32_FP64_SUPPORT won't be selected as it should be because MIPS32_O32 is disabled (o32 is already the default ABI available on 32-bit kernels).
This results in userland FP breakage as CP0_Status.FR is read-only 1 since r6 (when an FPU is present) so __enable_fpu() will fail to clear FR. This causes the FPU emulator to get used which will incorrectly emulate 32-bit FPU registers.
Force o32 fp64 support in this case by also selecting MIPS_O32_FP64_SUPPORT from CPU_MIPS64_R6 if 32BIT.
Patchwork: https://patchwork.linux-mips.org/patch/15310/
--- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/Kconfig +1 -1
@@ -1526,7 +1526,7 @@ config CPU_MIPS64_R6 select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_MSA select GENERIC_CSUM - select MIPS_O32_FP64_SUPPORT if MIPS32_O32 + select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32 select HAVE_KVM help Choose this option to build a kernel for release 6 or later of the
Greg Kroah-Hartman
maintainerPATCH 47/152 MIPS: ralink: Fix typos in rt3883 pinctrl
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: John Crispin <[email protected]>
commit 7c5a3d813050ee235817b0220dd8c42359a9efd8 upstream.
There are two copy & paste errors in the definition of the 5GHz LNA and second ethernet pinmux.
Patchwork: https://patchwork.linux-mips.org/patch/15328/
--- arch/mips/ralink/rt3883.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/mips/ralink/rt3883.c +2 -2
@@ -36,7 +36,7 @@ static struct rt2880_pmx_func uartlite_fstatic struct rt2880_pmx_func jtag_func[] = {FUNC ("jtag" ,0 ,17 ,5 ) };static struct rt2880_pmx_func mdio_func[] = {FUNC ("mdio" ,0 ,22 ,2 ) };static struct rt2880_pmx_func lna_a_func[] = {FUNC ("lna a" ,0 ,32 ,3 ) }; -static struct rt2880_pmx_func lna_g_func[] = {FUNC ("lna a" ,0 ,35 ,3 ) }; +static struct rt2880_pmx_func lna_g_func[] = {FUNC ("lna g" ,0 ,35 ,3 ) };static struct rt2880_pmx_func pci_func[] = {FUNC ("pci-dev" ,0 ,40 ,32 ),FUNC ("pci-host2" ,1 ,40 ,32 ),
@@ -44,7 +44,7 @@ static struct rt2880_pmx_func pci_func[]FUNC ("pci-fnc" ,3 ,40 ,32 ) };static struct rt2880_pmx_func ge1_func[] = {FUNC ("ge1" ,0 ,72 ,12 ) }; -static struct rt2880_pmx_func ge2_func[] = {FUNC ("ge1" ,0 ,84 ,12 ) }; +static struct rt2880_pmx_func ge2_func[] = {FUNC ("ge2" ,0 ,84 ,12 ) };static struct rt2880_pmx_group rt3883_pinmux_data[] = {GRP ("i2c" , i2c_func,1 ,RT3883_GPIO_MODE_I2C ),
Greg Kroah-Hartman
maintainerPATCH 48/152 MIPS: End spinlocks with .insn
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Paul Burton <[email protected]>
commit 4b5347a24a0f2d3272032c120664b484478455de upstream.
When building for microMIPS we need to ensure that the assembler always knows that there is code at the target of a branch or jump. Recent toolchains will fail to link a microMIPS kernel when this isn't the case due to what it thinks is a branch to non-microMIPS code.
mips-mti-linux-gnu-ld kernel/built-in.o: .spinlock.text+0x2fc: Unsupported branch between ISA modes. mips-mti-linux-gnu-ld final link failed: Bad value
This is due to inline assembly labels in spinlock.h not being followed by an instruction mnemonic, either due to a .subsection pseudo-op or the end of the inline asm block.
Fix this with a .insn direction after such labels.
Patchwork: https://patchwork.linux-mips.org/patch/15325/
--- arch/mips/include/asm/spinlock.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/mips/include/asm/spinlock.h +4 -4
@@ -127,7 +127,7 @@ static inline void arch_spin_lock(arch_s" andi %[ticket], %[ticket], 0xffff \n" " bne %[ticket], %[my_ticket], 4f \n" " subu %[ticket], %[my_ticket], %[ticket] \n" -"2: \n" +"2: .insn \n" " .subsection 2 \n" "4: andi %[ticket], %[ticket], 0xffff \n" " sll %[ticket], 5 \n"
@@ -202,7 +202,7 @@ static inline unsigned int arch_spin_try" sc %[ticket], %[ticket_ptr] \n" " beqz %[ticket], 1b \n" " li %[ticket], 1 \n" -"2: \n" +"2: .insn \n" " .subsection 2 \n" "3: b 2b \n" " li %[ticket], 0 \n"
@@ -382,7 +382,7 @@ static inline int arch_read_trylock(arch " .set reorder \n" __WEAK_LLSC_MB " li %2, 1 \n" - "2: \n" + "2: .insn \n" : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) : GCC_OFF_SMALL_ASM() (rw->lock) : "memory");
@@ -422,7 +422,7 @@ static inline int arch_write_trylock(arc " lui %1, 0x8000 \n" " sc %1, %0 \n" " li %2, 1 \n" - "2: \n" + "2: .insn \n" : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) : GCC_OFF_SMALL_ASM() (rw->lock)
Greg Kroah-Hartman
maintainerPATCH 49/152 MIPS: Lantiq: fix missing xbar kernel panic
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Hauke Mehrtens <[email protected]>
commit 6ef90877eee63a0d03e83183bb44b64229b624e6 upstream.
Commit 08b3c894e565 ("MIPS: lantiq: Disable xbar fpi burst mode") accidentally requested the resources from the pmu address region instead of the xbar registers region, but the check for the return value of request_mem_region() was wrong. Commit 98ea51cb0c8c ("MIPS:
Lantiq: Fix another request_mem_region() return code check") fixed the check of the return value of request_mem_region() which made the kernel panics.
This patch now makes use of the correct memory region for the cross bar.
Patchwork: https://patchwork.linux-mips.org/patch/15751
--- arch/mips/lantiq/xway/sysctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/lantiq/xway/sysctrl.c +1 -1
@@ -467,7 +467,7 @@ void __init ltq_soc_init(void)if (!np_xbar)panic ("Failed to load xbar nodes from devicetree" ); -if (of_address_to_resource (np_pmu,0 , &res_xbar)) +if (of_address_to_resource (np_xbar,0 , &res_xbar))panic ("Failed to get xbar resources" );if (request_mem_region (res_xbar.start,resource_size (&res_xbar), res_xbar.name) <0 )
Greg Kroah-Hartman
maintainerPATCH 50/152 MIPS: Check TLB before handle_ri_rdhwr() for Loongson-3
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Huacai Chen <[email protected]>
commit 5a34133167dce36666ea054e30a561b7f4413b7f upstream.
Loongson-3's micro TLB (ITLB) is not strictly a subset of JTLB. That
means: when a JTLB entry is replaced by hardware, there may be an old valid entry exists in ITLB. So, a TLB miss exception may occur while handle_ri_rdhwr() is running because it try to access EPC's content. However, handle_ri_rdhwr() doesn't clear EXL, which makes a TLB Refill exception be treated as a TLB Invalid exception and tlbp may fail. In this case, if FTLB (which is usually set-associative instead of set- associative) is enabled, a tlbp failure will cause an invalid tlbwi, which will hang the whole system.
This patch rename handle_ri_rdhwr_vivt to handle_ri_rdhwr_tlbp and use it for Loongson-3. It try to solve the same problem described as below, but more straightforwards.
https://patchwork.linux-mips.org/patch/12591/
I think Loongson-2 has the same problem, but it has no FTLB, so we just keep it as is.
Patchwork: https://patchwork.linux-mips.org/patch/15753/
--- arch/mips/kernel/genex.S | 4 ++-- arch/mips/kernel/traps.c | 17 +++++++++++++---- 2 files changed, 15 insertions(+), 6 deletions(-)
arch/mips/kernel/genex.S +2 -2
@@ -448,7 +448,7 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER reserved reserved sti verbose /* others */ .align 5 - LEAF(handle_ri_rdhwr_vivt) + LEAF(handle_ri_rdhwr_tlbp) .set push .set noat .set noreorder
@@ -467,7 +467,7 @@ NESTED(nmi_handler, PT_SIZE, sp) .set pop bltz k1, handle_ri /* slow path */ /* fall thru */ - END(handle_ri_rdhwr_vivt) + END(handle_ri_rdhwr_tlbp) LEAF(handle_ri_rdhwr) .set push
arch/mips/kernel/traps.c +13 -4
@@ -81,7 +81,7 @@ extern asmlinkage void handle_dbe(void); extern asmlinkage void handle_sys(void); extern asmlinkage void handle_bp(void); extern asmlinkage void handle_ri(void); -extern asmlinkage void handle_ri_rdhwr_vivt(void); +extern asmlinkage void handle_ri_rdhwr_tlbp(void); extern asmlinkage void handle_ri_rdhwr(void); extern asmlinkage void handle_cpu(void); extern asmlinkage void handle_ov(void);
@@ -2352,9 +2352,18 @@ void __init trap_init(void)set_except_vector (EXCCODE_SYS , handle_sys);set_except_vector (EXCCODE_BP , handle_bp); -set_except_vector (EXCCODE_RI , rdhwr_noopt ? handle_ri : - (cpu_has_vtag_icache ? - handle_ri_rdhwr_vivt : handle_ri_rdhwr)); + +if (rdhwr_noopt) +set_except_vector (EXCCODE_RI , handle_ri); +else { +if (cpu_has_vtag_icache) +set_except_vector (EXCCODE_RI , handle_ri_rdhwr_tlbp); +else if (current_cpu_type () ==CPU_LOONGSON3 ) +set_except_vector (EXCCODE_RI , handle_ri_rdhwr_tlbp); +else +set_except_vector (EXCCODE_RI , handle_ri_rdhwr); + } +set_except_vector (EXCCODE_CPU , handle_cpu);set_except_vector (EXCCODE_OV , handle_ov);set_except_vector (EXCCODE_TR , handle_tr);
Greg Kroah-Hartman
maintainerPATCH 51/152 MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Huacai Chen <[email protected]>
commit 033cffeedbd11c140952b98e8639bf652091a17d upstream.
Loongson-3A R2 and newer CPU have FTLB, but Config0.MT is 1, so add MIPS_CPU_FTLB to the CPU options.
Patchwork: https://patchwork.linux-mips.org/patch/15752/
--- arch/mips/kernel/cpu-probe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/kernel/cpu-probe.c +1 -1
@@ -1824,7 +1824,7 @@ static inline void cpu_probe_loongson(st }decode_configs (c); - c->options |=MIPS_CPU_TLBINV |MIPS_CPU_LDPTE ; + c->options |=MIPS_CPU_FTLB |MIPS_CPU_TLBINV |MIPS_CPU_LDPTE ; c->writecombine = _CACHE_UNCACHED_ACCELERATED;break ;default :
Greg Kroah-Hartman
maintainerPATCH 52/152 MIPS: Flush wrong invalid FTLB entry for huge page
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Huacai Chen <[email protected]>
commit 0115f6cbf26663c86496bc56eeea293f85b77897 upstream.
On VTLB+FTLB platforms (such as Loongson-3A R2), FTLB's pagesize is usually configured the same as PAGE_SIZE. In such a case, Huge page entry is not suitable to write in FTLB.
Unfortunately, when a huge page is created, its page table entries haven't created immediately. Then the TLB refill handler will fetch an invalid page table entry which has no "HUGE" bit, and this entry may be written to FTLB. Since it is invalid, TLB load/store handler will then use tlbwi to write the valid entry at the same place. However, the valid entry is a huge page entry which isn't suitable for FTLB.
Our solution is to modify build_huge_handler_tail. Flush the invalid old entry (whether it is in FTLB or VTLB, this is in order to reduce branches) and use tlbwr to write the valid new entry.
Patchwork: https://patchwork.linux-mips.org/patch/15754/
--- arch/mips/mm/tlbex.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-)
arch/mips/mm/tlbex.c +21 -4
@@ -762,7 +762,8 @@ static void build_huge_update_entries(u3static void build_huge_handler_tail (u32 **p,struct uasm_reloc **r,struct uasm_label **l,unsigned int pte, -unsigned int ptr) +unsigned int ptr, +unsigned int flush) {#ifdef CONFIG_SMP UASM_i_SC (p, pte,0 , ptr);
@@ -771,6 +772,22 @@ static void build_huge_handler_tail(u32#else UASM_i_SW (p, pte,0 , ptr);#endif +if (cpu_has_ftlb && flush) { +BUG_ON (!cpu_has_tlbinv); + +UASM_i_MFC0 (p, ptr,C0_ENTRYHI ); +uasm_i_ori (p, ptr, ptr,MIPS_ENTRYHI_EHINV ); +UASM_i_MTC0 (p, ptr,C0_ENTRYHI ); +build_tlb_write_entry (p, l, r, tlb_indexed); + +uasm_i_xori (p, ptr, ptr,MIPS_ENTRYHI_EHINV ); +UASM_i_MTC0 (p, ptr,C0_ENTRYHI ); +build_huge_update_entries (p, pte, ptr); +build_huge_tlb_write_entry (p, l, r, pte, tlb_random,0 ); + +return ; + } +build_huge_update_entries (p, pte, ptr);build_huge_tlb_write_entry (p, l, r, pte, tlb_indexed,0 ); }
@@ -2197,7 +2214,7 @@ static void build_r4000_tlb_load_handler uasm_l_tlbl_goaround2(&l, p); }uasm_i_ori (&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); -build_huge_handler_tail (&p, &r, &l, wr.r1, wr.r2); +build_huge_handler_tail (&p, &r, &l, wr.r1, wr.r2,1 );#endif uasm_l_nopage_tlbl (&l, p);
@@ -2252,7 +2269,7 @@ static void build_r4000_tlb_store_handlebuild_tlb_probe_entry (&p);uasm_i_ori (&p, wr.r1, wr.r1, _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); -build_huge_handler_tail (&p, &r, &l, wr.r1, wr.r2); +build_huge_handler_tail (&p, &r, &l, wr.r1, wr.r2,1 );#endif uasm_l_nopage_tlbs (&l, p);
@@ -2308,7 +2325,7 @@ static void build_r4000_tlb_modify_handlbuild_tlb_probe_entry (&p);uasm_i_ori (&p, wr.r1, wr.r1, _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); -build_huge_handler_tail (&p, &r, &l, wr.r1, wr.r2); +build_huge_handler_tail (&p, &r, &l, wr.r1, wr.r2,0 );#endif uasm_l_nopage_tlbm (&l, p);
Greg Kroah-Hartman
maintainerPATCH 53/152 MIPS: c-r4k: Fix Loongson-3s vcache/scache waysize calculation
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Huacai Chen <[email protected]>
commit 0be032c190abcdcfa948082b6a1e0d461184ba4d upstream.
If scache.waysize is 0, r4k___flush_cache_all() will do nothing and then cause bugs. BTW, though vcache.waysize isn't being used by now, we also fix its calculation.
Patchwork: https://patchwork.linux-mips.org/patch/15756/
--- arch/mips/mm/c-r4k.c | 2 ++ 1 file changed, 2 insertions(+)
arch/mips/mm/c-r4k.c +2 -0
@@ -1558,6 +1558,7 @@ static void probe_vcache(void) vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz; c->vcache.waybit =0 ; + c->vcache.waysize = vcache_size / c->vcache.ways;pr_info ("Unified victim cache %ldkB %s, linesize %d bytes.\n" , vcache_size >>10 , way_string[c->vcache.ways], c->vcache.linesz);
@@ -1660,6 +1661,7 @@ static void __init loongson3_sc_init(voi/* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ scache_size *=4 ; c->scache.waybit =0 ; + c->scache.waysize = scache_size / c->scache.ways;pr_info ("Unified secondary cache %ldkB %s, linesize %d bytes.\n" , scache_size >>10 , way_string[c->scache.ways], c->scache.linesz);if (scache_size)
Greg Kroah-Hartman
maintainerPATCH 54/152 Documentation: stable-kernel-rules: fix stable-tag format
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Johan Hovold <[email protected]>
commit cf903e9d3a97f89b224d2d07be37c0f160db8192 upstream.
A patch documenting how to specify which kernels a particular fix should be backported to (seemingly) inadvertently added a minus sign after the kernel version. This particular stable-tag format had never been used prior to this patch, and was neither present when the patch in question was first submitted (it was added in v2 without any comment).
Drop the minus sign to avoid any confusion.
--- Documentation/stable_kernel_rules.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Documentation/stable_kernel_rules.txt +1 -1
@@ -124,7 +124,7 @@ specified in the following format in the .. code-block:: none - Cc: <[email protected]> # 3.3.x- + Cc: <[email protected]> # 3.3.x The tag has the meaning of:
Greg Kroah-Hartman
maintainerPATCH 55/152 mm/mempolicy.c: fix error handling in set_mempolicy and mbind.
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Chris Salls <[email protected]>
commit cf01fb9985e8deb25ccf0ea54d916b8871ae0e62 upstream.
In the case that compat_get_bitmap fails we do not want to copy the bitmap to the user as it will contain uninitialized stack data and leak sensitive data.
--- mm/mempolicy.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-)
mm/mempolicy.c +8 -12
@@ -1524,7 +1524,6 @@ COMPAT_SYSCALL_DEFINE5(get_mempolicy, in COMPAT_SYSCALL_DEFINE3(set_mempolicy, int, mode, compat_ulong_t __user *, nmask, compat_ulong_t, maxnode) { -long err =0 ;unsigned long __user *nm =NULL ;unsigned long nr_bits, alloc_size;DECLARE_BITMAP (bm,MAX_NUMNODES );
@@ -1533,14 +1532,13 @@ COMPAT_SYSCALL_DEFINE3(set_mempolicy, in alloc_size =ALIGN (nr_bits,BITS_PER_LONG ) /8 ;if (nmask) { - err =compat_get_bitmap (bm, nmask, nr_bits); +if (compat_get_bitmap (bm, nmask, nr_bits)) +return -EFAULT ; nm =compat_alloc_user_space (alloc_size); - err |=copy_to_user (nm, bm, alloc_size); +if (copy_to_user (nm, bm, alloc_size)) +return -EFAULT ; } -if (err) -return -EFAULT ; -return sys_set_mempolicy (mode, nm, nr_bits+1 ); }
@@ -1548,7 +1546,6 @@ COMPAT_SYSCALL_DEFINE6(mbind, compat_ulo compat_ulong_t, mode, compat_ulong_t __user *, nmask, compat_ulong_t, maxnode, compat_ulong_t, flags) { -long err =0 ;unsigned long __user *nm =NULL ;unsigned long nr_bits, alloc_size;nodemask_t bm;
@@ -1557,14 +1554,13 @@ COMPAT_SYSCALL_DEFINE6(mbind, compat_ulo alloc_size =ALIGN (nr_bits,BITS_PER_LONG ) /8 ;if (nmask) { - err =compat_get_bitmap (nodes_addr (bm), nmask, nr_bits); +if (compat_get_bitmap (nodes_addr (bm), nmask, nr_bits)) +return -EFAULT ; nm =compat_alloc_user_space (alloc_size); - err |=copy_to_user (nm,nodes_addr (bm), alloc_size); +if (copy_to_user (nm,nodes_addr (bm), alloc_size)) +return -EFAULT ; } -if (err) -return -EFAULT ; -return sys_mbind (start, len, mode, nm, nr_bits+1 , flags); }
Greg Kroah-Hartman
maintainerPATCH 56/152 random: use chacha20 for get_random_int/long
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jason A. Donenfeld <[email protected]>
commit f5b98461cb8167ba362ad9f74c41d126b7becea7 upstream.
Now that our crng uses chacha20, we can rely on its speedy characteristics for replacing MD5, while simultaneously achieving a higher security guarantee. Before the idea was to use these functions if you wanted random integers that aren't stupidly insecure but aren't necessarily secure either, a vague gray zone, that hopefully was "good enough" for its users. With chacha20, we can strengthen this claim, since either we're using an rdrand-like instruction, or we're using the same crng as /dev/urandom. And it's faster than what was before.
We could have chosen to replace this with a SipHash-derived function, which might be slightly faster, but at the cost of having yet another RNG construction in the kernel. By moving to chacha20, we have a single RNG to analyze and verify, and we also already get good performance improvements on all platforms.
Implementation-wise, rather than use a generic buffer for both get_random_int/long and memcpy based on the size needs, we use a specific buffer for 32-bit reads and for 64-bit reads. This way, we're guaranteed to always have aligned accesses on all platforms. While slightly more verbose in C, the assembly this generates is a lot simpler than otherwise.
Finally, on 32-bit platforms where longs and ints are the same size, we simply alias get_random_int to get_random_long.
--- drivers/char/random.c | 84 +++++++++++++++++++++++++------------------------ include/linux/random.h | 1 init/main.c | 1 3 files changed, 43 insertions(+), 43 deletions(-)
drivers/char/random.c +43 -41
@@ -2042,63 +2042,65 @@ struct ctl_table random_table[] = { };#endif /* CONFIG_SYSCTL */ -static u32 random_int_secret[MD5_MESSAGE_BYTES /4 ]____cacheline_aligned ; - -int random_int_secret_init (void ) -{ -get_random_bytes (random_int_secret,sizeof (random_int_secret)); -return 0 ; -} - -static DEFINE_PER_CPU(__u32 [MD5_DIGEST_WORDS], get_random_int_hash) -__aligned(sizeof(unsigned long)) ; +struct batched_entropy { +union { +unsigned long entropy_long[CHACHA20_BLOCK_SIZE /sizeof (unsigned long )]; +unsigned int entropy_int[CHACHA20_BLOCK_SIZE /sizeof (unsigned int )]; + }; +unsigned int position; +};/* -* Get a random word for internal kernel use only. Similar to urandom but -* with the goal of minimal entropy pool depletion. As a result, the random -* value is not cryptographically secure but for several uses the cost of -* depleting entropy is too high +* Get a random word for internal kernel use only. The quality of the random +* number is either as good as RDRAND or as good as /dev/urandom, with the +* goal of being quite fast and not depleting entropy. */ -unsigned int get_random_int (void ) +static DEFINE_PER_CPU(struct batched_entropy, batched_entropy_long); +unsigned long get_random_long (void ) { -__u32 *hash; -unsigned int ret; +unsigned long ret; +struct batched_entropy *batch; -if (arch_get_random_int (&ret)) +if (arch_get_random_long (&ret))return ret; - hash =get_cpu_var (get_random_int_hash); - - hash[0 ] += current->pid + jiffies +random_get_entropy (); -md5_transform (hash, random_int_secret); - ret = hash[0 ]; -put_cpu_var (get_random_int_hash); - + batch = &get_cpu_var (batched_entropy_long); +if (batch->position %ARRAY_SIZE (batch->entropy_long) ==0 ) { +extract_crng ((u8 *)batch->entropy_long); + batch->position =0 ; + } + ret = batch->entropy_long[batch->position++]; +put_cpu_var (batched_entropy_long);return ret; } -EXPORT_SYMBOL (get_random_int); +EXPORT_SYMBOL (get_random_long); -/* -* Same as get_random_int(), but returns unsigned long. -*/ -unsigned long get_random_long (void ) +#if BITS_PER_LONG ==32 +unsigned int get_random_int (void ) { -__u32 *hash; -unsigned long ret; +return get_random_long (); +} +#else +static DEFINE_PER_CPU(struct batched_entropy, batched_entropy_int); +unsigned int get_random_int (void ) +{ +unsigned int ret; +struct batched_entropy *batch; -if (arch_get_random_long (&ret)) +if (arch_get_random_int (&ret))return ret; - hash =get_cpu_var (get_random_int_hash); - - hash[0 ] += current->pid + jiffies +random_get_entropy (); -md5_transform (hash, random_int_secret); - ret = *(unsigned long *)hash; -put_cpu_var (get_random_int_hash); - + batch = &get_cpu_var (batched_entropy_int); +if (batch->position %ARRAY_SIZE (batch->entropy_int) ==0 ) { +extract_crng ((u8 *)batch->entropy_int); + batch->position =0 ; + } + ret = batch->entropy_int[batch->position++]; +put_cpu_var (batched_entropy_int);return ret; } -EXPORT_SYMBOL (get_random_long); +#endif +EXPORT_SYMBOL (get_random_int);/** * randomize_page - Generate a random, page aligned address
include/linux/random.h +0 -1
@@ -37,7 +37,6 @@ extern void get_random_bytes(void *buf,extern int add_random_ready_callback (struct random_ready_callback *rdy);extern void del_random_ready_callback (struct random_ready_callback *rdy);extern void get_random_bytes_arch (void *buf,int nbytes); -extern int random_int_secret_init (void );#ifndef MODULE extern const struct file_operations random_fops, urandom_fops;
init/main.c +0 -1
@@ -868,7 +868,6 @@ static void __init do_basic_setup(void)do_ctors ();usermodehelper_enable ();do_initcalls (); -random_int_secret_init (); }static void __init do_pre_smp_initcalls (void )
Greg Kroah-Hartman
maintainerPATCH 57/152 drm/sun4i: tcon: Move SoC specific quirks to a DT matched data structure
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Chen-Yu Tsai <[email protected]>
commit 91ea2f29cba6a7fe035ea232e4f981211a9fce5d upstream.
We already have some differences between the 2 supported SoCs. More will be added as we support other SoCs. To avoid bloating the probe function with even more conditionals, move the quirks to a separate data structure that's tied to the compatible string.
--- drivers/gpu/drm/sun4i/sun4i_tcon.c | 33 ++++++++++++++++++--------------- drivers/gpu/drm/sun4i/sun4i_tcon.h | 11 +++++++---- 2 files changed, 25 insertions(+), 19 deletions(-)
drivers/gpu/drm/sun4i/sun4i_tcon.c +18 -15
@@ -20,6 +20,7 @@#include <linux/component.h> #include <linux/ioport.h> #include <linux/of_address.h> +#include <linux/of_device.h> #include <linux/of_graph.h> #include <linux/of_irq.h> #include <linux/regmap.h>
@@ -62,7 +63,7 @@ void sun4i_tcon_channel_disable(struct sreturn ; } -WARN_ON (!tcon->has_channel_1); +WARN_ON (!tcon->quirks->has_channel_1);regmap_update_bits (tcon->regs,SUN4I_TCON1_CTL_REG ,SUN4I_TCON1_CTL_TCON_ENABLE ,0 );clk_disable_unprepare (tcon->sclk1);
@@ -80,7 +81,7 @@ void sun4i_tcon_channel_enable(struct sureturn ; } -WARN_ON (!tcon->has_channel_1); +WARN_ON (!tcon->quirks->has_channel_1);regmap_update_bits (tcon->regs,SUN4I_TCON1_CTL_REG ,SUN4I_TCON1_CTL_TCON_ENABLE ,SUN4I_TCON1_CTL_TCON_ENABLE );
@@ -202,7 +203,7 @@ void sun4i_tcon1_mode_set(struct sun4i_tu8 clk_delay;u32 val; -WARN_ON (!tcon->has_channel_1); +WARN_ON (!tcon->quirks->has_channel_1);/* Adjust clock delay */ clk_delay =sun4i_tcon_get_clk_delay (mode,1 );
@@ -266,7 +267,7 @@ void sun4i_tcon1_mode_set(struct sun4i_t/* * FIXME: Undocumented bits */ -if (tcon->has_mux) +if (tcon->quirks->has_unknown_mux)regmap_write (tcon->regs,SUN4I_TCON_MUX_CTRL_REG ,1 ); }EXPORT_SYMBOL (sun4i_tcon1_mode_set);
@@ -327,7 +328,7 @@ static int sun4i_tcon_init_clocks(structreturn PTR_ERR (tcon->sclk0); } -if (tcon->has_channel_1) { +if (tcon->quirks->has_channel_1) { tcon->sclk1 =devm_clk_get (dev,"tcon-ch1" );if (IS_ERR (tcon->sclk1)) {dev_err (dev,"Couldn't get the TCON channel 1 clock\n" );
@@ -487,14 +488,7 @@ static int sun4i_tcon_bind(struct device drv->tcon = tcon; tcon->drm = drm; tcon->dev = dev; - -if (of_device_is_compatible (dev->of_node,"allwinner,sun5i-a13-tcon" )) { - tcon->has_mux = true; - tcon->has_channel_1 = true; - }else { - tcon->has_mux = false; - tcon->has_channel_1 = false; - } + tcon->quirks =of_device_get_match_data (dev); tcon->lcd_rst =devm_reset_control_get (dev,"lcd" );if (IS_ERR (tcon->lcd_rst)) {
@@ -588,9 +582,18 @@ static int sun4i_tcon_remove(struct platreturn 0 ; } +static const struct sun4i_tcon_quirks sun5i_a13_quirks = { + .has_unknown_mux = true, + .has_channel_1 = true, +}; + +static const struct sun4i_tcon_quirks sun8i_a33_quirks = { +/* nothing is supported */ +}; +static const struct of_device_id sun4i_tcon_of_table[] = { - { .compatible ="allwinner,sun5i-a13-tcon" }, - { .compatible ="allwinner,sun8i-a33-tcon" }, + { .compatible ="allwinner,sun5i-a13-tcon" , .data = &sun5i_a13_quirks }, + { .compatible ="allwinner,sun8i-a33-tcon" , .data = &sun8i_a33_quirks }, { } };MODULE_DEVICE_TABLE (of, sun4i_tcon_of_table);
drivers/gpu/drm/sun4i/sun4i_tcon.h +7 -4
@@ -142,6 +142,11 @@#define SUN4I_TCON_MAX_CHANNELS 2 +struct sun4i_tcon_quirks { +bool has_unknown_mux;/* sun5i has undocumented mux */ +bool has_channel_1;/* a33 does not have channel 1 */ +}; +struct sun4i_tcon {struct device *dev;struct drm_device *drm;
@@ -160,12 +165,10 @@ struct sun4i_tcon {/* Reset control */ struct reset_control *lcd_rst; -/* Platform adjustments */ -bool has_mux; -struct drm_panel *panel; -bool has_channel_1; +/* Platform adjustments */ +const struct sun4i_tcon_quirks *quirks; };struct drm_bridge *sun4i_tcon_find_bridge (struct device_node *node);
Greg Kroah-Hartman
maintainerPATCH 58/152 drm/sun4i: Add compatible strings for A31/A31s display pipelines
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Chen-Yu Tsai <[email protected]>
commit 49c440e87cd6f547f93d0dc53571ae0e11d9ec8f upstream.
The A31's display pipeline has 2 frontends, 2 backends, and 2 TCONs. It also has new display enhancement blocks, such as the DRC (Dynamic Range Controller), the DEU (Display Enhancement Unit), and the CMU (Color Management Unit). It supports HDMI, MIPI DSI, and 2 LCD/LVDS channels.
The A31s display pipeline is almost the same, just without MIPI DSI. Only the TCON seems to be different, due to the missing mux for MIPI DSI.
Add compatible strings for both of them.
--- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 4 ++++ drivers/gpu/drm/sun4i/sun4i_backend.c | 1 + drivers/gpu/drm/sun4i/sun4i_drv.c | 3 +++ 3 files changed, 8 insertions(+)
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +4 -0
@@ -87,6 +87,7 @@ system. Required properties: - compatible: value must be one of: * allwinner,sun5i-a13-display-backend + * allwinner,sun6i-a31-display-backend * allwinner,sun8i-a33-display-backend - reg: base address and size of the memory-mapped region. - clocks: phandles to the clocks feeding the frontend and backend
@@ -117,6 +118,7 @@ deinterlacing and color space conversion Required properties: - compatible: value must be one of: * allwinner,sun5i-a13-display-frontend + * allwinner,sun6i-a31-display-frontend * allwinner,sun8i-a33-display-frontend - reg: base address and size of the memory-mapped region. - interrupts: interrupt associated to this IP
@@ -142,6 +144,8 @@ extra node. Required properties: - compatible: value must be one of: * allwinner,sun5i-a13-display-engine + * allwinner,sun6i-a31-display-engine + * allwinner,sun6i-a31s-display-engine * allwinner,sun8i-a33-display-engine - allwinner,pipelines: list of phandle to the display engine
drivers/gpu/drm/sun4i/sun4i_backend.c +1 -0
@@ -408,6 +408,7 @@ static int sun4i_backend_remove(struct pstatic const struct of_device_id sun4i_backend_of_table[] = { { .compatible ="allwinner,sun5i-a13-display-backend" }, + { .compatible ="allwinner,sun6i-a31-display-backend" }, { .compatible ="allwinner,sun8i-a33-display-backend" }, { } };
drivers/gpu/drm/sun4i/sun4i_drv.c +3 -0
@@ -201,6 +201,7 @@ static const struct component_master_opsstatic bool sun4i_drv_node_is_frontend (struct device_node *node) {return of_device_is_compatible (node,"allwinner,sun5i-a13-display-frontend" ) || +of_device_is_compatible (node,"allwinner,sun6i-a31-display-frontend" ) ||of_device_is_compatible (node,"allwinner,sun8i-a33-display-frontend" ); }
@@ -322,6 +323,8 @@ static int sun4i_drv_remove(struct platfstatic const struct of_device_id sun4i_drv_of_table[] = { { .compatible ="allwinner,sun5i-a13-display-engine" }, + { .compatible ="allwinner,sun6i-a31-display-engine" }, + { .compatible ="allwinner,sun6i-a31s-display-engine" }, { .compatible ="allwinner,sun8i-a33-display-engine" }, { } };
Greg Kroah-Hartman
maintainerPATCH 59/152 drm/sun4i: Add compatible string for A31/A31s TCON (timing controller)
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Chen-Yu Tsai <[email protected]>
commit 93a5ec14da24a8abbac5bcb953b45cc7a5d0198a upstream.
The A31 TCON has mux controls for how TCON outputs are routed to the HDMI and MIPI DSI blocks.
Since the A31s does not have MIPI DSI, it only has a mux for the HDMI controller input.
This patch only adds support for the compatible strings. Actual support for the mux controls should be added with HDMI and MIPI DSI support.
--- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 4 +++- drivers/gpu/drm/sun4i/sun4i_drv.c | 2 ++ drivers/gpu/drm/sun4i/sun4i_tcon.c | 10 ++++++++++ 3 files changed, 15 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +3 -1
@@ -28,6 +28,8 @@ The TCON acts as a timing controller for Required properties: - compatible: value must be either: * allwinner,sun5i-a13-tcon + * allwinner,sun6i-a31-tcon + * allwinner,sun6i-a31s-tcon * allwinner,sun8i-a33-tcon - reg: base address and size of memory-mapped region - interrupts: interrupt associated to this IP
@@ -50,7 +52,7 @@ Required properties: second the block connected to the TCON channel 1 (usually the TV encoder) -On the A13, there is one more clock required: +On SoCs other than the A33, there is one more clock required: - 'tcon-ch1': The clock driving the TCON channel 1 DRC
drivers/gpu/drm/sun4i/sun4i_drv.c +2 -0
@@ -208,6 +208,8 @@ static bool sun4i_drv_node_is_frontend(sstatic bool sun4i_drv_node_is_tcon (struct device_node *node) {return of_device_is_compatible (node,"allwinner,sun5i-a13-tcon" ) || +of_device_is_compatible (node,"allwinner,sun6i-a31-tcon" ) || +of_device_is_compatible (node,"allwinner,sun6i-a31s-tcon" ) ||of_device_is_compatible (node,"allwinner,sun8i-a33-tcon" ); }
drivers/gpu/drm/sun4i/sun4i_tcon.c +10 -0
@@ -587,12 +587,22 @@ static const struct sun4i_tcon_quirks su .has_channel_1 = true, }; +static const struct sun4i_tcon_quirks sun6i_a31_quirks = { + .has_channel_1 = true, +}; + +static const struct sun4i_tcon_quirks sun6i_a31s_quirks = { + .has_channel_1 = true, +}; +static const struct sun4i_tcon_quirks sun8i_a33_quirks = {/* nothing is supported */ };static const struct of_device_id sun4i_tcon_of_table[] = { { .compatible ="allwinner,sun5i-a13-tcon" , .data = &sun5i_a13_quirks }, + { .compatible ="allwinner,sun6i-a31-tcon" , .data = &sun6i_a31_quirks }, + { .compatible ="allwinner,sun6i-a31s-tcon" , .data = &sun6i_a31s_quirks }, { .compatible ="allwinner,sun8i-a33-tcon" , .data = &sun8i_a33_quirks }, { } };
Greg Kroah-Hartman
maintainerPATCH 60/152 clk: lpc32xx: add a quirk for PWM and MS clock dividers
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Vladimir Zapolskiy <[email protected]>
[ Upstream commit f84d42a9cffc4ecd96f1ce3a038f841782142eb2 ]
In common clock framework CLK_DIVIDER_ONE_BASED or'ed with CLK_DIVIDER_ALLOW_ZERO flags indicates that
1) a divider clock may be set to zero value,
2) divider's zero value is interpreted as a non-divided clock.
On the LPC32xx platform clock dividers of PWM and memory card clocks comply with the first condition, but zero value means a gated clock, thus it may happen that the divider value is not updated when the clock is enabled and the clock remains gated.
The change adds one-shot quirks, which check for zero value of divider on initialization and set it to a non-zero value, therefore in runtime a gate clock will work as expected.
--- drivers/clk/nxp/clk-lpc32xx.c | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-)
drivers/clk/nxp/clk-lpc32xx.c +28 -4
@@ -1282,13 +1282,13 @@ static struct clk_hw_proto clk_hw_proto[LPC32XX_DEFINE_MUX (PWM1_MUX ,PWMCLK_CTRL ,1 ,0x1 ,NULL ,0 ),LPC32XX_DEFINE_DIV (PWM1_DIV ,PWMCLK_CTRL ,4 ,4 ,NULL , -CLK_DIVIDER_ONE_BASED |CLK_DIVIDER_ALLOW_ZERO ), +CLK_DIVIDER_ONE_BASED ),LPC32XX_DEFINE_GATE (PWM1_GATE ,PWMCLK_CTRL ,0 ,0 ),LPC32XX_DEFINE_COMPOSITE (PWM1 ,PWM1_MUX ,PWM1_DIV ,PWM1_GATE ),LPC32XX_DEFINE_MUX (PWM2_MUX ,PWMCLK_CTRL ,3 ,0x1 ,NULL ,0 ),LPC32XX_DEFINE_DIV (PWM2_DIV ,PWMCLK_CTRL ,8 ,4 ,NULL , -CLK_DIVIDER_ONE_BASED |CLK_DIVIDER_ALLOW_ZERO ), +CLK_DIVIDER_ONE_BASED ),LPC32XX_DEFINE_GATE (PWM2_GATE ,PWMCLK_CTRL ,2 ,0 ), LPC32XX_DEFINE_COMPOSITE(PWM2, PWM2_MUX, PWM2_DIV, PWM2_GATE),
@@ -1335,8 +1335,7 @@ static struct clk_hw_proto clk_hw_proto[LPC32XX_DEFINE_GATE (USB_DIV_GATE ,USB_CTRL ,17 ,0 ),LPC32XX_DEFINE_COMPOSITE (USB_DIV , _NULL,USB_DIV_DIV ,USB_DIV_GATE ), -LPC32XX_DEFINE_DIV (SD_DIV ,MS_CTRL ,0 ,4 ,NULL , -CLK_DIVIDER_ONE_BASED |CLK_DIVIDER_ALLOW_ZERO ), +LPC32XX_DEFINE_DIV (SD_DIV ,MS_CTRL ,0 ,4 ,NULL ,CLK_DIVIDER_ONE_BASED ),LPC32XX_DEFINE_CLK (SD_GATE ,MS_CTRL ,BIT (5 ) |BIT (9 ),BIT (5 ) |BIT (9 ),0x0 ,BIT (5 ) |BIT (9 ),0x0 ,0x0 , clk_mask_ops), LPC32XX_DEFINE_COMPOSITE(SD, _NULL, SD_DIV, SD_GATE),
@@ -1478,6 +1477,20 @@ static struct clk * __init lpc32xx_clk_rreturn clk; } +static void __init lpc32xx_clk_div_quirk (u32 reg,u32 div_mask,u32 gate) +{ +u32 val; + +regmap_read (clk_regmap, reg, &val); + +if (!(val & div_mask)) { + val &= ~gate; + val |=BIT (__ffs (div_mask)); + } + +regmap_update_bits (clk_regmap, reg, gate | div_mask, val); +} +static void __init lpc32xx_clk_init (struct device_node *np) {unsigned int i;
@@ -1517,6 +1530,17 @@ static void __init lpc32xx_clk_init(strureturn ; } +/* +* Divider part of PWM and MS clocks requires a quirk to avoid +* a misinterpretation of formally valid zero value in register +* bitfield, which indicates another clock gate. Instead of +* adding complexity to a gate clock ensure that zero value in +* divider clock is never met in runtime. +*/ +lpc32xx_clk_div_quirk (LPC32XX_CLKPWR_PWMCLK_CTRL ,0xf0 ,BIT (0 )); +lpc32xx_clk_div_quirk (LPC32XX_CLKPWR_PWMCLK_CTRL ,0xf00 ,BIT (2 )); +lpc32xx_clk_div_quirk (LPC32XX_CLKPWR_MS_CTRL ,0xf ,BIT (5 ) |BIT (9 )); +for (i =1 ; i <LPC32XX_CLK_MAX ; i++) { clk[i] =lpc32xx_clk_register (i);if (IS_ERR (clk[i])) {
Greg Kroah-Hartman
maintainerPATCH 61/152 HID: usbhid: Add quirks for Mayflash/Dragonrise GameCube and PS3 adapters
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Marcel Hasler <[email protected]>
[ Upstream commit b2554000f5b5d2a3a368d09c6debf7da64901fcf ]
All known gamepad adapters by Mayflash (identified as Dragonrise) need HID_QUIRK_MULTI_INPUT to split them up into four input devices. Without this quirk those adapters are falsely recognized as tablets. Fixes bug 115841
(https://bugzilla.kernel.org/show_bug.cgi?id=115841).
--- drivers/hid/hid-ids.h | 6 ++++-- drivers/hid/usbhid/hid-quirks.c | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-)
drivers/hid/hid-ids.h +4 -2
@@ -318,8 +318,10 @@#define USB_VENDOR_ID_DMI 0x0c0b#define USB_DEVICE_ID_DMI_ENC 0x5fab -#define USB_VENDOR_ID_DRAGONRISE 0x0079 -#define USB_DEVICE_ID_DRAGONRISE_WIIU 0x1800 +#define USB_VENDOR_ID_DRAGONRISE 0x0079 +#define USB_DEVICE_ID_DRAGONRISE_WIIU 0x1800 +#define USB_DEVICE_ID_DRAGONRISE_PS3 0x1801 +#define USB_DEVICE_ID_DRAGONRISE_GAMECUBE 0x1843#define USB_VENDOR_ID_DWAV 0x0eef#define USB_DEVICE_ID_EGALAX_TOUCHCONTROLLER 0x0001
drivers/hid/usbhid/hid-quirks.c +2 -0
@@ -83,6 +83,8 @@ static const struct hid_blacklist { { USB_VENDOR_ID_CREATIVELABS, USB_DEVICE_ID_CREATIVE_SB_OMNI_SURROUND_51, HID_QUIRK_NOGET }, { USB_VENDOR_ID_DMI, USB_DEVICE_ID_DMI_ENC, HID_QUIRK_NOGET }, { USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_WIIU, HID_QUIRK_MULTI_INPUT }, + { USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_PS3, HID_QUIRK_MULTI_INPUT }, + { USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE, HID_QUIRK_MULTI_INPUT }, { USB_VENDOR_ID_ELAN, HID_ANY_ID, HID_QUIRK_ALWAYS_POLL }, { USB_VENDOR_ID_ELO, USB_DEVICE_ID_ELO_TS2700, HID_QUIRK_NOGET }, { USB_VENDOR_ID_FORMOSA, USB_DEVICE_ID_FORMOSA_IR_RECEIVER, HID_QUIRK_NO_INIT_REPORTS },
Greg Kroah-Hartman
maintainerPATCH 62/152 HID: i2c-hid: add a simple quirk to fix device defects
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: HungNien Chen <[email protected]>
[ Upstream commit 71af01a8c85ad89449209594133bdfdfaa9f1e2a ]
Certain devices produced by Weida Tech need to have a wakeup command sent to them before powering on. The call itself will come back with error, but the device can be powered on afterwards.
--- drivers/hid/hid-ids.h | 4 ++ drivers/hid/i2c-hid/i2c-hid.c | 57 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+)
drivers/hid/hid-ids.h +4 -0
@@ -1039,6 +1039,10 @@#define USB_DEVICE_ID_WALTOP_MEDIA_TABLET_14_1_INCH 0x0500#define USB_DEVICE_ID_WALTOP_SIRIUS_BATTERY_FREE_TABLET 0x0502 +#define USB_VENDOR_ID_WEIDA 0x2575 +#define USB_DEVICE_ID_WEIDA_8752 0xC300 +#define USB_DEVICE_ID_WEIDA_8755 0xC301 +#define USB_VENDOR_ID_WISEGROUP 0x0925#define USB_DEVICE_ID_SMARTJOY_PLUS 0x0005#define USB_DEVICE_ID_SUPER_JOY_BOX_3 0x8888
drivers/hid/i2c-hid/i2c-hid.c +57 -0
92 lines not on this page · raw message
Greg Kroah-Hartman
maintainerPATCH 63/152 usb: dwc3: gadget: delay unmap of bounced requests
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Janusz Dziedzic <[email protected]>
commit de288e36fe33f7e06fa272bc8e2f85aa386d99aa upstream.
In the case of bounced ep0 requests, we must delay DMA operation until after ->complete() otherwise we might overwrite contents of req->buf.
This caused problems with RNDIS gadget.
--- drivers/usb/dwc3/gadget.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-)
drivers/usb/dwc3/gadget.c +17 -4
@@ -174,6 +174,7 @@ void dwc3_gadget_giveback(struct dwc3_ep int status) {struct dwc3 *dwc = dep->dwc; +unsigned int unmap_after_complete = false; req->started = false;list_del (&req->list);
@@ -182,11 +183,19 @@ void dwc3_gadget_giveback(struct dwc3_epif (req->request.status == -EINPROGRESS ) req->request.status = status; -if (dwc->ep0_bounced && dep->number <=1 ) +/* +* NOTICE we don't want to unmap before calling ->complete() if we're +* dealing with a bounced ep0 request. If we unmap it here, we would end +* up overwritting the contents of req->buf and this could confuse the +* gadget driver. +*/ +if (dwc->ep0_bounced && dep->number <=1 ) { dwc->ep0_bounced = false; - -usb_gadget_unmap_request (&dwc->gadget, &req->request, - req->direction); + unmap_after_complete = true; + }else { +usb_gadget_unmap_request (&dwc->gadget, + &req->request, req->direction); + }trace_dwc3_gadget_giveback (req);
@@ -194,6 +203,10 @@ void dwc3_gadget_giveback(struct dwc3_epusb_gadget_giveback_request (&dep->endpoint, &req->request);spin_lock (&dwc->lock); +if (unmap_after_complete) +usb_gadget_unmap_request (&dwc->gadget, + &req->request, req->direction); +if (dep->number >1 )pm_runtime_put (dwc->dev); }
Greg Kroah-Hartman
maintainerPATCH 64/152 ASoC: Intel: bytct_rt5640: change default capture settings
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pierre-Louis Bossart <[email protected]>
[ Upstream commit bf46241bee7bc3ec28703796f4fbd56085055fca ]
Most Baytrail-CR devices use analog differential microphones, modify capture default to avoid DMI quirks. Keep digital mics for all other configurations.
--- sound/soc/intel/boards/bytcr_rt5640.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
sound/soc/intel/boards/bytcr_rt5640.c +8 -3
@@ -57,9 +57,7 @@ struct byt_rt5640_private {struct clk *mclk; }; -static unsigned long byt_rt5640_quirk =BYT_RT5640_DMIC1_MAP | -BYT_RT5640_DMIC_EN | -BYT_RT5640_MCLK_EN ; +static unsigned long byt_rt5640_quirk =BYT_RT5640_MCLK_EN ;static void log_quirks (struct device *dev) {
@@ -738,6 +736,13 @@ static int snd_byt_rt5640_mc_probe(strucif (res_info->acpi_ipc_irq_index ==0 ) { byt_rt5640_quirk |=BYT_RT5640_SSP0_AIF2 ; } + +/* change defaults for Baytrail-CR capture */ + byt_rt5640_quirk |=BYT_RT5640_IN1_MAP ; + byt_rt5640_quirk |=BYT_RT5640_DIFF_MIC ; + }else { + byt_rt5640_quirk |= (BYT_RT5640_DMIC1_MAP | +BYT_RT5640_DMIC_EN ); }/* check quirks before creating card */
Greg Kroah-Hartman
maintainerPATCH 65/152 arm64: dts: hisi: fix hip06 sas am-max-trans quirk
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: John Garry <[email protected]>
[ Upstream commit f65e786604b34d0b599b8c01ecca28be2d746290 ]
The string for the am max transmissions quirk property is not correct -> fix it.
--- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/hisilicon/hip06.dtsi +1 -1
@@ -590,7 +590,7 @@ reg = <0 0xa2000000 0 0x10000>; sas-addr = [50 01 88 20 16 00 00 00]; hisilicon,sas-syscon = <&pcie_subctl>; - am-max-trans; + hip06-sas-v2-quirk-amt; ctrl-reset-reg = <0xa18>; ctrl-reset-sts-reg = <0x5a0c>; ctrl-clock-ena-reg = <0x318>;
Greg Kroah-Hartman
maintainerPATCH 66/152 net/mlx4_core: Use device ID defines
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Bjorn Helgaas <[email protected]>
[ Upstream commit c19e4b9037fa8a0477525a64e93847f534e8cc17 ]
We added a bunch of new Mellanox device ID definitions because they'll be used by INTx quirks. Use them in the mlx4 ID table also so grep can find both places. No functional change intended.
--- drivers/net/ethernet/mellanox/mlx4/main.c | 84 +++++++++++++++--------------- 1 file changed, 43 insertions(+), 41 deletions(-)
drivers/net/ethernet/mellanox/mlx4/main.c +43 -41
@@ -4020,49 +4020,51 @@ int mlx4_restart_one(struct pci_dev *pdereturn err; } +#define MLX_SP (id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT } +#define MLX_VF (id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF } +#define MLX_GN (id) { PCI_VDEVICE(MELLANOX, id), 0 } +static const struct pci_device_id mlx4_pci_table[] = { -/* MT25408 "Hermon" SDR */ - {PCI_VDEVICE (MELLANOX ,0x6340 ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT25408 "Hermon" DDR */ - {PCI_VDEVICE (MELLANOX ,0x634a ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT25408 "Hermon" QDR */ - {PCI_VDEVICE (MELLANOX ,0x6354 ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT25408 "Hermon" DDR PCIe gen2 */ - {PCI_VDEVICE (MELLANOX ,0x6732 ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT25408 "Hermon" QDR PCIe gen2 */ - {PCI_VDEVICE (MELLANOX ,0x673c ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT25408 "Hermon" EN 10GigE */ - {PCI_VDEVICE (MELLANOX ,0x6368 ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT25408 "Hermon" EN 10GigE PCIe gen2 */ - {PCI_VDEVICE (MELLANOX ,0x6750 ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT25458 ConnectX EN 10GBASE-T 10GigE */ - {PCI_VDEVICE (MELLANOX ,0x6372 ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ - {PCI_VDEVICE (MELLANOX ,0x675a ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT26468 ConnectX EN 10GigE PCIe gen2*/ - {PCI_VDEVICE (MELLANOX ,0x6764 ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ - {PCI_VDEVICE (MELLANOX ,0x6746 ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT26478 ConnectX2 40GigE PCIe gen2 */ - {PCI_VDEVICE (MELLANOX ,0x676e ),MLX4_PCI_DEV_FORCE_SENSE_PORT }, -/* MT25400 Family [ConnectX-2 Virtual Function] */ - {PCI_VDEVICE (MELLANOX ,0x1002 ),MLX4_PCI_DEV_IS_VF }, +/* MT25408 "Hermon" */ +MLX_SP (PCI_DEVICE_ID_MELLANOX_HERMON_SDR ),/* SDR */ +MLX_SP (PCI_DEVICE_ID_MELLANOX_HERMON_DDR ),/* DDR */ +MLX_SP (PCI_DEVICE_ID_MELLANOX_HERMON_QDR ),/* QDR */ +MLX_SP (PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2 ),/* DDR Gen2 */ +MLX_SP (PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2 ),/* QDR Gen2 */ +MLX_SP (PCI_DEVICE_ID_MELLANOX_HERMON_EN ),/* EN 10GigE */ +MLX_SP (PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2 ),/* EN 10GigE Gen2 */ +/* MT25458 ConnectX EN 10GBASE-T */ +MLX_SP (PCI_DEVICE_ID_MELLANOX_CONNECTX_EN ), +MLX_SP (PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2 ),/* Gen2 */ +/* MT26468 ConnectX EN 10GigE PCIe Gen2*/ +MLX_SP (PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2 ), +/* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */ +MLX_SP (PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2 ), +/* MT26478 ConnectX2 40GigE PCIe Gen2 */ +MLX_SP (PCI_DEVICE_ID_MELLANOX_CONNECTX2 ), +/* MT25400 Family [ConnectX-2] */ +MLX_VF (0x1002 ),/* Virtual Function */ /* MT27500 Family [ConnectX-3] */ - {PCI_VDEVICE (MELLANOX ,0x1003 ),0 }, -/* MT27500 Family [ConnectX-3 Virtual Function] */ - {PCI_VDEVICE (MELLANOX ,0x1004 ),MLX4_PCI_DEV_IS_VF }, - {PCI_VDEVICE (MELLANOX ,0x1005 ),0 },/* MT27510 Family */ - {PCI_VDEVICE (MELLANOX ,0x1006 ),0 },/* MT27511 Family */ - {PCI_VDEVICE (MELLANOX ,0x1007 ),0 },/* MT27520 Family */ - {PCI_VDEVICE (MELLANOX ,0x1008 ),0 },/* MT27521 Family */ - {PCI_VDEVICE (MELLANOX ,0x1009 ),0 },/* MT27530 Family */ - {PCI_VDEVICE (MELLANOX ,0x100a ),0 },/* MT27531 Family */ - {PCI_VDEVICE (MELLANOX ,0x100b ),0 },/* MT27540 Family */ - {PCI_VDEVICE (MELLANOX ,0x100c ),0 },/* MT27541 Family */ - {PCI_VDEVICE (MELLANOX ,0x100d ),0 },/* MT27550 Family */ - {PCI_VDEVICE (MELLANOX ,0x100e ),0 },/* MT27551 Family */ - {PCI_VDEVICE (MELLANOX ,0x100f ),0 },/* MT27560 Family */ - {PCI_VDEVICE (MELLANOX ,0x1010 ),0 },/* MT27561 Family */ +MLX_GN (PCI_DEVICE_ID_MELLANOX_CONNECTX3 ), +MLX_VF (0x1004 ),/* Virtual Function */ +MLX_GN (0x1005 ),/* MT27510 Family */ +MLX_GN (0x1006 ),/* MT27511 Family */ +MLX_GN (PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO ),/* MT27520 Family */ +MLX_GN (0x1008 ),/* MT27521 Family */ +MLX_GN (0x1009 ),/* MT27530 Family */ +MLX_GN (0x100a ),/* MT27531 Family */ +MLX_GN (0x100b ),/* MT27540 Family */ +MLX_GN (0x100c ),/* MT27541 Family */ +MLX_GN (0x100d ),/* MT27550 Family */ +MLX_GN (0x100e ),/* MT27551 Family */ +MLX_GN (0x100f ),/* MT27560 Family */ +MLX_GN (0x1010 ),/* MT27561 Family */ + +/* +* See the mellanox_check_broken_intx_masking() quirk when +* adding devices +*/ + {0 , } };
Greg Kroah-Hartman
maintainerPATCH 67/152 clocksource/drivers/arm_arch_timer: Dont assume clock runs in suspend
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Brian Norris <[email protected]>
[ Upstream commit d8ec7595a013237f82d965dcf981571aeb41855b ]
The ARM specifies that the system counter "must be implemented in an always-on power domain," and so we try to use the counter as a source of timekeeping across suspend/resume. Unfortunately, some SoCs (e.g., Rockchip's RK3399) do not keep the counter ticking properly when switched from their high-power clock to the lower-power clock used in system suspend. Support this quirk by adding a new device tree property.
--- Documentation/devicetree/bindings/arm/arch_timer.txt | 5 +++++ drivers/clocksource/arm_arch_timer.c | 9 ++++++++- 2 files changed, 13 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/arm/arch_timer.txt +5 -0
@@ -38,6 +38,11 @@ to deliver its interrupts via SPIs. architecturally-defined reset values. Only supported for 32-bit systems which follow the ARMv7 architected reset values. +- arm,no-tick-in-suspend : The main counter does not tick when the system is in + low-power system suspend on some SoCs. This behavior does not match the + Architecture Reference Manual's specification that the system counter "must + be implemented in an always-on power domain." + Example:
drivers/clocksource/arm_arch_timer.c +8 -1
@@ -81,6 +81,7 @@ static struct clock_event_device __percpstatic enum ppi_nr arch_timer_uses_ppi =VIRT_PPI ;static bool arch_timer_c3stop;static bool arch_timer_mem_use_virtual; +static bool arch_counter_suspend_stop;static bool evtstrm_enable =IS_ENABLED (CONFIG_ARM_ARCH_TIMER_EVTSTREAM );
@@ -576,7 +577,7 @@ static struct clocksource clocksource_co .rating = 400, .read = arch_counter_read, .mask = CLOCKSOURCE_MASK(56), - .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, };static struct cyclecounter cyclecounter = {
@@ -616,6 +617,8 @@ static void __init arch_counter_register arch_timer_read_counter = arch_counter_get_cntvct_mem; } +if (!arch_counter_suspend_stop) + clocksource_counter.flags |=CLOCK_SOURCE_SUSPEND_NONSTOP ; start_count =arch_timer_read_counter ();clocksource_register_hz (&clocksource_counter, arch_timer_rate); cyclecounter.mult = clocksource_counter.mult;
@@ -907,6 +910,10 @@ static int __init arch_timer_of_init(str of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) arch_timer_uses_ppi =PHYS_SECURE_PPI ; +/* On some systems, the counter stops ticking when in suspend. */ + arch_counter_suspend_stop =of_property_read_bool (np, +"arm,no-tick-in-suspend" ); +return arch_timer_init (); }CLOCKSOURCE_OF_DECLARE (armv7_arch_timer,"arm,armv7-timer" , arch_timer_of_init);
Greg Kroah-Hartman
maintainerPATCH 68/152 scsi: ufs: introduce UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Kiwoong Kim <[email protected]>
[ Upstream commit 75b1cc4ad63afa28c1a045b5157c008f405f06a9 ]
Some UFS host controllers may think granularities of PRDT length and offset as bytes, not double words.
--- drivers/scsi/ufs/ufshcd.c | 28 +++++++++++++++++++++------- drivers/scsi/ufs/ufshcd.h | 6 ++++++ 2 files changed, 27 insertions(+), 7 deletions(-)
drivers/scsi/ufs/ufshcd.c +21 -7
@@ -1088,7 +1088,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba,* * Returns 0 in case of success, non-zero value in case of failure */ -static int ufshcd_map_sg (struct ufshcd_lrb *lrbp) +static int ufshcd_map_sg (struct ufs_hba *hba,struct ufshcd_lrb *lrbp) {struct ufshcd_sg_entry *prd_table;struct scatterlist *sg;
@@ -1102,8 +1102,13 @@ static int ufshcd_map_sg(struct ufshcd_lreturn sg_segments;if (sg_segments) { - lrbp->utr_descriptor_ptr->prd_table_length = -cpu_to_le16 ((u16) (sg_segments)); +if (hba->quirks &UFSHCD_QUIRK_PRDT_BYTE_GRAN ) + lrbp->utr_descriptor_ptr->prd_table_length = +cpu_to_le16 ((u16)(sg_segments * +sizeof (struct ufshcd_sg_entry ))); +else + lrbp->utr_descriptor_ptr->prd_table_length = +cpu_to_le16 ((u16) (sg_segments)); prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -1465,7 +1470,7 @@ static int ufshcd_queuecommand(struct Scufshcd_comp_scsi_upiu (hba, lrbp); - err =ufshcd_map_sg (lrbp); + err =ufshcd_map_sg (hba, lrbp);if (err) { lrbp->cmd =NULL ;clear_bit_unlock (tag, &hba->lrb_in_use);
@@ -2320,12 +2325,21 @@ static void ufshcd_host_memory_configurecpu_to_le32 (upper_32_bits (cmd_desc_element_addr));/* Response upiu and prdt offset should be in double words */ - utrdlp[i].response_upiu_offset = +if (hba->quirks &UFSHCD_QUIRK_PRDT_BYTE_GRAN ) { + utrdlp[i].response_upiu_offset = +cpu_to_le16 (response_offset); + utrdlp[i].prd_table_offset = +cpu_to_le16 (prdt_offset); + utrdlp[i].response_upiu_length = +cpu_to_le16 (ALIGNED_UPIU_SIZE ); + }else { + utrdlp[i].response_upiu_offset =cpu_to_le16 ((response_offset >>2 )); - utrdlp[i].prd_table_offset = + utrdlp[i].prd_table_offset =cpu_to_le16 ((prdt_offset >>2 )); - utrdlp[i].response_upiu_length = + utrdlp[i].response_upiu_length =cpu_to_le16 (ALIGNED_UPIU_SIZE >>2 ); + } hba->lrb[i].utr_descriptor_ptr = (utrdlp + i); hba->lrb[i].ucd_req_ptr =
drivers/scsi/ufs/ufshcd.h +6 -0
@@ -474,6 +474,12 @@ struct ufs_hba {*/ #define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5) +/* +* This quirk needs to be enabled if the host contoller regards +* resolution of the values of PRDTO and PRDTL in UTRD as byte. +*/ +#define UFSHCD_QUIRK_PRDT_BYTE_GRAN UFS_BIT(7) +unsigned int quirks;/* Deviations from standard UFSHCI spec. */ /* Device deviations from standard UFS device spec. */
Greg Kroah-Hartman
maintainerPATCH 69/152 HID: sensor-hub add quirk for Microsoft Surface 3
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Benjamin Tissoires <[email protected]>
[ Upstream commit da809197a919942ab6ee0d008c20a011872181b1 ]
One more device requiring a quirk :/
--- drivers/hid/hid-sensor-hub.c | 3 +++ 1 file changed, 3 insertions(+)
drivers/hid/hid-sensor-hub.c +3 -0
@@ -796,6 +796,9 @@ static const struct hid_device_id sensor {HID_DEVICE (HID_BUS_ANY ,HID_GROUP_SENSOR_HUB ,USB_VENDOR_ID_MICROSOFT , USB_DEVICE_ID_MS_TYPE_COVER_2), .driver_data = HID_SENSOR_HUB_ENUM_QUIRK}, + { HID_DEVICE(HID_BUS_ANY, HID_GROUP_SENSOR_HUB, USB_VENDOR_ID_MICROSOFT, + 0x07bd), /* Microsoft Surface 3 */ + .driver_data = HID_SENSOR_HUB_ENUM_QUIRK}, { HID_DEVICE(HID_BUS_ANY, HID_GROUP_SENSOR_HUB, USB_VENDOR_ID_STM_0, USB_DEVICE_ID_STM_HID_SENSOR), .driver_data = HID_SENSOR_HUB_ENUM_QUIRK},
Greg Kroah-Hartman
maintainerPATCH 70/152 HID: sensor-hub: add quirk for Microchip MM7150
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Benjamin Tissoires <[email protected]>
[ Upstream commit 5cc5084dd9afa2f9bf953b0217bdb1b7c2158be1 ]
One more device requiring a quirk :/
--- drivers/hid/hid-sensor-hub.c | 3 +++ 1 file changed, 3 insertions(+)
drivers/hid/hid-sensor-hub.c +3 -0
@@ -799,6 +799,9 @@ static const struct hid_device_id sensor {HID_DEVICE (HID_BUS_ANY ,HID_GROUP_SENSOR_HUB ,USB_VENDOR_ID_MICROSOFT , 0x07bd), /* Microsoft Surface 3 */ .driver_data = HID_SENSOR_HUB_ENUM_QUIRK}, + { HID_DEVICE(HID_BUS_ANY, HID_GROUP_SENSOR_HUB, USB_VENDOR_ID_MICROCHIP, + 0x0f01), /* MM7150 */ + .driver_data = HID_SENSOR_HUB_ENUM_QUIRK}, { HID_DEVICE(HID_BUS_ANY, HID_GROUP_SENSOR_HUB, USB_VENDOR_ID_STM_0, USB_DEVICE_ID_STM_HID_SENSOR), .driver_data = HID_SENSOR_HUB_ENUM_QUIRK},
Greg Kroah-Hartman
maintainerPATCH 71/152 HID: multitouch: enable the Surface 3 Type Cover to report multitouch data
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Benjamin Tissoires <[email protected]>
[ Upstream commit 8fe89ef076fa104f514da6ef61d90f5bf93488e3 ]
There is no reasons to filter out keyboard and consumer control collections in hid-multitouch.
With the previous hid-input fix, there is now a full support of the Type Cover and we can remove all specific bits from hid-core and hid-microsoft.
hid-multitouch will automatically set HID_QUIRK_NO_INIT_REPORTS so we can also remove it from the list of ushbid quirks.
--- drivers/hid/hid-core.c | 2 -- drivers/hid/hid-ids.h | 1 - drivers/hid/hid-microsoft.c | 2 -- drivers/hid/hid-multitouch.c | 4 +++- drivers/hid/usbhid/hid-quirks.c | 1 - 5 files changed, 3 insertions(+), 7 deletions(-)
drivers/hid/hid-core.c +0 -2
@@ -728,7 +728,6 @@ static void hid_scan_collection(struct h hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_2 || hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP || hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP || - hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_3 || hid->product == USB_DEVICE_ID_MS_POWER_COVER) && hid->group == HID_GROUP_MULTITOUCH) hid->group = HID_GROUP_GENERIC;
@@ -1984,7 +1983,6 @@ static const struct hid_device_id hid_ha { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_2) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP) }, - { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_3) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_7K) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_600) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_3KV1) },
drivers/hid/hid-ids.h +0 -1
@@ -724,7 +724,6 @@#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_2 0x07e2#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP 0x07dd#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP 0x07e9 -#define USB_DEVICE_ID_MS_TYPE_COVER_3 0x07de#define USB_DEVICE_ID_MS_POWER_COVER 0x07da#define USB_VENDOR_ID_MOJO 0x8282
drivers/hid/hid-microsoft.c +0 -2
@@ -282,8 +282,6 @@ static const struct hid_device_id ms_dev .driver_data = MS_HIDINPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP), .driver_data = MS_HIDINPUT }, - { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_3), - .driver_data = MS_HIDINPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_POWER_COVER), .driver_data = MS_HIDINPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_COMFORT_KEYBOARD),
drivers/hid/hid-multitouch.c +3 -1
@@ -842,7 +842,9 @@ static int mt_input_mapping(struct hid_dif (!td->mtclass.export_all_inputs && field->application !=HID_DG_TOUCHSCREEN && field->application !=HID_DG_PEN && - field->application !=HID_DG_TOUCHPAD ) + field->application !=HID_DG_TOUCHPAD && + field->application !=HID_GD_KEYBOARD && + field->application !=HID_CP_CONSUMER_CONTROL )return -1 ;/*
drivers/hid/usbhid/hid-quirks.c +0 -1
@@ -105,7 +105,6 @@ static const struct hid_blacklist { { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_2, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP, HID_QUIRK_NO_INIT_REPORTS }, - { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_3, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_POWER_COVER, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MSI, USB_DEVICE_ID_MSI_GT683R_LED_PANEL, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_NEXIO, USB_DEVICE_ID_NEXIO_MULTITOUCH_PTI0750, HID_QUIRK_NO_INIT_REPORTS },
Greg Kroah-Hartman
maintainerPATCH 72/152 HID: multitouch: do not retrieve all reports for all devices
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Benjamin Tissoires <[email protected]>
[ Upstream commit b897f6db3ae2cd9a42377f8b1865450f34ceff0e ]
We already have in place a quirk for Windows 8 devices, but it looks like the Surface Cover are not conforming to it.
Given that we are only interested in 3 feature reports (the ones that the Windows driver retrieves), we should be safe to unconditionally apply the quirk to everybody.
In case there is an issue with a controller, we can always mark it as such in the transport driver, and hid-multitouch won't try to retrieve the feature report.
--- drivers/hid/hid-multitouch.c | 76 ++++++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 36 deletions(-)
drivers/hid/hid-multitouch.c +40 -36
@@ -108,6 +108,7 @@ struct mt_device {int cc_value_index;/* contact count value index in the field */ unsigned last_slot_field;/* the last field of a slot */ unsigned mt_report_id;/* the report ID of the multitouch device */ +unsigned long initial_quirks;/* initial quirks state */ __s16 inputmode;/* InputMode HID feature, -1 if non-existent */ __s16 inputmode_index;/* InputMode HID feature index in the report */ __s16 maxcontact_report_id;/* Maximum Contact Number HID feature,
@@ -318,13 +319,10 @@ static void mt_get_feature(struct hid_deu8 *buf;/* -* Only fetch the feature report if initial reports are not already -* been retrieved. Currently this is only done for Windows 8 touch -* devices. +* Do not fetch the feature report if the device has been explicitly +* marked as non-capable. */ -if (!(hdev->quirks &HID_QUIRK_NO_INIT_REPORTS )) -return ; -if (td->mtclass.name !=MT_CLS_WIN_8 ) +if (td->initial_quirks &HID_QUIRK_NO_INIT_REPORTS )return ; buf =hid_alloc_report_buf (report,GFP_KERNEL );
@@ -1085,36 +1083,6 @@ static int mt_probe(struct hid_device *h } } -/* This allows the driver to correctly support devices -* that emit events over several HID messages. -*/ - hdev->quirks |=HID_QUIRK_NO_INPUT_SYNC ; - -/* -* This allows the driver to handle different input sensors -* that emits events through different reports on the same HID -* device. -*/ - hdev->quirks |=HID_QUIRK_MULTI_INPUT ; - hdev->quirks |=HID_QUIRK_NO_EMPTY_INPUT ; - -/* -* Handle special quirks for Windows 8 certified devices. -*/ -if (id->group ==HID_GROUP_MULTITOUCH_WIN_8 ) -/* -* Some multitouch screens do not like to be polled for input -* reports. Fortunately, the Win8 spec says that all touches -* should be sent during each report, making the initialization -* of input reports unnecessary. -* -* In addition some touchpads do not behave well if we read -* all feature reports from them. Instead we prevent -* initial report fetching and then selectively fetch each -* report we are interested in. -*/ - hdev->quirks |=HID_QUIRK_NO_INIT_REPORTS ; - td =devm_kzalloc (&hdev->dev,sizeof (struct mt_device ),GFP_KERNEL );if (!td) {dev_err (&hdev->dev,"cannot allocate multitouch data\n" );
@@ -1138,6 +1106,39 @@ static int mt_probe(struct hid_device *hif (id->vendor ==HID_ANY_ID && id->product ==HID_ANY_ID ) td->serial_maybe = true; +/* +* Store the initial quirk state +*/ + td->initial_quirks = hdev->quirks; + +/* This allows the driver to correctly support devices +* that emit events over several HID messages. +*/ + hdev->quirks |=HID_QUIRK_NO_INPUT_SYNC ; + +/* +* This allows the driver to handle different input sensors +* that emits events through different reports on the same HID +* device. +*/ + hdev->quirks |=HID_QUIRK_MULTI_INPUT ; + hdev->quirks |=HID_QUIRK_NO_EMPTY_INPUT ; + +/* +* Some multitouch screens do not like to be polled for input +* reports. Fortunately, the Win8 spec says that all touches +* should be sent during each report, making the initialization +* of input reports unnecessary. For Win7 devices, well, let's hope +* they will still be happy (this is only be a problem if a touch +* was already there while probing the device). +* +* In addition some touchpads do not behave well if we read +* all feature reports from them. Instead we prevent +* initial report fetching and then selectively fetch each +* report we are interested in. +*/ + hdev->quirks |=HID_QUIRK_NO_INIT_REPORTS ; + ret =hid_parse (hdev);if (ret !=0 )return ret;
@@ -1206,8 +1207,11 @@ static int mt_resume(struct hid_device *static void mt_remove (struct hid_device *hdev) { +struct mt_device *td =hid_get_drvdata (hdev); +sysfs_remove_group (&hdev->dev.kobj, &mt_attribute_group);hid_hw_stop (hdev); + hdev->quirks = td->initial_quirks; }/*
Greg Kroah-Hartman
maintainerPATCH 73/152 mmc: sdhci-msm: Enable few quirks
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Ritesh Harjani <[email protected]>
[ Upstream commit a0e3142869d29688de6f77be31aa7a401a4a88f1 ]
sdhc-msm controller needs this SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN & SDHCI_QUIRK2_PRESET_VALUE_BROKEN to be set. Hence setting it.
--- drivers/mmc/host/sdhci-msm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/mmc/host/sdhci-msm.c +3 -1
@@ -524,7 +524,9 @@ static const struct sdhci_ops sdhci_msm_static const struct sdhci_pltfm_data sdhci_msm_pdata = { .quirks =SDHCI_QUIRK_BROKEN_CARD_DETECTION |SDHCI_QUIRK_NO_CARD_NO_RESET | -SDHCI_QUIRK_SINGLE_POWER_WRITE , +SDHCI_QUIRK_SINGLE_POWER_WRITE | +SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN , + .quirks2 =SDHCI_QUIRK2_PRESET_VALUE_BROKEN , .ops = &sdhci_msm_ops, };
Greg Kroah-Hartman
maintainerPATCH 74/152 scsi: ufs: ensure that host pa_tactivate is higher than device
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Subhash Jadavani <[email protected]>
[ Upstream commit c6a6db439868c7ba5cc90d4c461d9697ec731fa1 ]
Some UFS devices require host PA_TACTIVATE to be higher than device PA_TACTIVATE otherwise it may get stuck during hibern8 sequence. This change allows this by using quirk.
--- drivers/scsi/ufs/ufs_quirks.h | 9 +++++ drivers/scsi/ufs/ufshcd.c | 73 ++++++++++++++++++++++++++++++++++++++++++ drivers/scsi/ufs/unipro.h | 4 ++ 3 files changed, 86 insertions(+)
drivers/scsi/ufs/ufs_quirks.h +9 -0
@@ -128,6 +128,13 @@ struct ufs_dev_fix {*/ #define UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM (1 << 6) +/* +* Some UFS devices require host PA_TACTIVATE to be lower than device +* PA_TACTIVATE, enabling this quirk ensure this. +*/ +#define UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE (1 << 7) + +struct ufs_hba ;void ufs_advertise_fixup_device (struct ufs_hba *hba);
@@ -140,6 +147,8 @@ static struct ufs_dev_fix ufs_fixups[] = UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL ,UFS_DEVICE_NO_FASTAUTO ), +UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL , +UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE ),UFS_FIX (UFS_VENDOR_TOSHIBA ,UFS_ANY_MODEL ,UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM ), UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
drivers/scsi/ufs/ufshcd.c +73 -0
85 lines not on this page · raw message
drivers/scsi/ufs/unipro.h +4 -0
@@ -123,6 +123,7 @@#define PA_MAXRXHSGEAR 0x1587#define PA_RXHSUNTERMCAP 0x15A5#define PA_RXLSTERMCAP 0x15A6 +#define PA_GRANULARITY 0x15AA#define PA_PACPREQTIMEOUT 0x1590#define PA_PACPREQEOBTIMEOUT 0x1591#define PA_HIBERN8TIME 0x15A7
@@ -158,6 +159,9 @@#define VS_DEBUGOMC 0xD09E#define VS_POWERSTATE 0xD083 +#define PA_GRANULARITY_MIN_VAL 1 +#define PA_GRANULARITY_MAX_VAL 6 +/* PHY Adapter Protocol Constants */ #define PA_MAXDATALANES 4
Greg Kroah-Hartman
maintainerPATCH 75/152 svcauth_gss: Close connection when dropping an incoming message
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Chuck Lever <[email protected]>
[ Upstream commit 4d712ef1db05c3aa5c3b690a50c37ebad584c53f ]
S5.3.3.1 of RFC 2203 requires that an incoming GSS-wrapped message whose sequence number lies outside the current window is dropped. The rationale is:
The reason for discarding requests silently is that the server is unable to determine if the duplicate or out of range request was due to a sequencing problem in the client, network, or the operating system, or due to some quirk in routing, or a replay attack by an intruder. Discarding the request allows the client to recover after timing out, if indeed the duplication was unintentional or well intended.
However, clients may rely on the server dropping the connection to indicate that a retransmit is needed. Without a connection reset, a client can wait forever without retransmitting, and the workload just stops dead. I've reproduced this behavior by running xfstests generic/323 on an NFSv4.0 mount with proto=rdma and sec=krb5i.
To address this issue, have the server close the connection when it silently discards an incoming message due to a GSS sequence number problem.
There are a few other places where the server will never reply. Change those spots in a similar fashion.
--- net/sunrpc/auth_gss/svcauth_gss.c | 2 +- net/sunrpc/svc.c | 14 +++++++++----- 2 files changed, 10 insertions(+), 6 deletions(-)
net/sunrpc/auth_gss/svcauth_gss.c +1 -1
@@ -1548,7 +1548,7 @@ complete: ret =SVC_COMPLETE ; goto out; drop: - ret =SVC_DROP ; + ret =SVC_CLOSE ; out:if (rsci)cache_put (&rsci->h, sn->rsc_cache);
net/sunrpc/svc.c +9 -5
@@ -1155,8 +1155,7 @@ svc_process_common(struct svc_rqst *rqstcase SVC_DENIED : goto err_bad_auth;case SVC_CLOSE : -if (test_bit (XPT_TEMP , &rqstp->rq_xprt->xpt_flags)) -svc_close_xprt (rqstp->rq_xprt); + goto close;case SVC_DROP : goto dropit;case SVC_COMPLETE :
@@ -1246,7 +1245,7 @@ svc_process_common(struct svc_rqst *rqst sendit:if (svc_authorise (rqstp)) - goto dropit; + goto close;return 1 ;/* Caller can now send it */ dropit:
@@ -1254,11 +1253,16 @@ svc_process_common(struct svc_rqst *rqstdprintk ("svc: svc_process dropit\n" );return 0 ; + close: +if (test_bit (XPT_TEMP , &rqstp->rq_xprt->xpt_flags)) +svc_close_xprt (rqstp->rq_xprt); +dprintk ("svc: svc_process close\n" ); +return 0 ; + err_short_len:svc_printk (rqstp,"short len %Zd, dropping request\n" , argv->iov_len); - - goto dropit;/* drop request */ + goto close; err_bad_rpc: serv->sv_stats->rpcbadfmt++;
Greg Kroah-Hartman
maintainerPATCH 76/152 x86/intel_idle: Add CPU model 0x4a (Atom Z34xx series)
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Andy Shevchenko <[email protected]>
[ Upstream commit 5e7ec268fd48d63cfd0e3a9be6c6443f01673bd4 ]
Add CPU ID for Atom Z34xx processors. Datasheets indicate support for this, detailed information about potential quirks or limitations are missing, though. So we just reuse the definition from official BSP code.
--- drivers/idle/intel_idle.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+)
drivers/idle/intel_idle.c +49 -0
@@ -724,6 +724,50 @@ static struct cpuidle_state atom_cstates { .enter = NULL } }; +static struct cpuidle_state tangier_cstates[] = { + { + .name ="C1-TNG" , + .desc ="MWAIT 0x00" , + .flags =MWAIT2flg (0x00 ), + .exit_latency =1 , + .target_residency =4 , + .enter = &intel_idle, + .enter_freeze = intel_idle_freeze, }, + { + .name ="C4-TNG" , + .desc ="MWAIT 0x30" , + .flags =MWAIT2flg (0x30 ) |CPUIDLE_FLAG_TLB_FLUSHED , + .exit_latency =100 , + .target_residency =400 , + .enter = &intel_idle, + .enter_freeze = intel_idle_freeze, }, + { + .name ="C6-TNG" , + .desc ="MWAIT 0x52" , + .flags =MWAIT2flg (0x52 ) |CPUIDLE_FLAG_TLB_FLUSHED , + .exit_latency =140 , + .target_residency =560 , + .enter = &intel_idle, + .enter_freeze = intel_idle_freeze, }, + { + .name ="C7-TNG" , + .desc ="MWAIT 0x60" , + .flags =MWAIT2flg (0x60 ) |CPUIDLE_FLAG_TLB_FLUSHED , + .exit_latency =1200 , + .target_residency =4000 , + .enter = &intel_idle, + .enter_freeze = intel_idle_freeze, }, + { + .name ="C9-TNG" , + .desc ="MWAIT 0x64" , + .flags =MWAIT2flg (0x64 ) |CPUIDLE_FLAG_TLB_FLUSHED , + .exit_latency =10000 , + .target_residency =20000 , + .enter = &intel_idle, + .enter_freeze = intel_idle_freeze, }, + { + .enter =NULL } +};static struct cpuidle_state avn_cstates[] = { { .name ="C1-AVN" ,
@@ -978,6 +1022,10 @@ static const struct idle_cpu idle_cpu_at .state_table = atom_cstates, }; +static const struct idle_cpu idle_cpu_tangier = { + .state_table = tangier_cstates, +}; +static const struct idle_cpu idle_cpu_lincroft = { .state_table = atom_cstates, .auto_demotion_disable_flags =ATM_LNC_C6_AUTO_DEMOTE ,
@@ -1066,6 +1114,7 @@ static const struct x86_cpu_id intel_idlICPU (INTEL_FAM6_SANDYBRIDGE_X , idle_cpu_snb),ICPU (INTEL_FAM6_ATOM_CEDARVIEW , idle_cpu_atom),ICPU (INTEL_FAM6_ATOM_SILVERMONT1 , idle_cpu_byt), +ICPU (INTEL_FAM6_ATOM_MERRIFIELD , idle_cpu_tangier),ICPU (INTEL_FAM6_ATOM_AIRMONT , idle_cpu_cht),ICPU (INTEL_FAM6_IVYBRIDGE , idle_cpu_ivb), ICPU(INTEL_FAM6_IVYBRIDGE_X, idle_cpu_ivt),
Greg Kroah-Hartman
maintainerPATCH 77/152 arm64: PCI: Manage controller-specific data on per-controller basis
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tomasz Nowicki <[email protected]>
[ Upstream commit 093d24a204425f71f4f106b7e62c8df4b456e1cc ]
Currently we use one shared global acpi_pci_root_ops structure to keep controller-specific ops. We pass its pointer to acpi_pci_root_create() and associate it with a host bridge instance for good. Such a design implies serious drawback. Any potential manipulation on the single system-wide acpi_pci_root_ops leads to kernel crash. The structure content is not really changing even across multiple host bridges creation; thus it was not an issue so far.
In preparation for adding ECAM quirks mechanism (where controller-specific PCI ops may be different for each host bridge) allocate new acpi_pci_root_ops and fill in with data for each bridge. Now it is safe to have different controller-specific info. As a consequence free acpi_pci_root_ops when host bridge is released.
No functional changes in this patch.
--- arch/arm64/kernel/pci.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-)
arch/arm64/kernel/pci.c +10 -7
@@ -159,33 +159,36 @@ static void pci_acpi_generic_release_inf ri = container_of(ci, struct acpi_pci_generic_root_info, common);pci_ecam_free (ri->cfg); +kfree (ci->ops);kfree (ri); } -static struct acpi_pci_root_ops acpi_pci_root_ops = { - .release_info = pci_acpi_generic_release_info, -}; -/* Interface called from ACPI code to setup PCI host controller */ struct pci_bus *pci_acpi_scan_root (struct acpi_pci_root *root) {int node =acpi_get_node (root->device->handle);struct acpi_pci_generic_root_info *ri;struct pci_bus *bus, *child; +struct acpi_pci_root_ops *root_ops; ri =kzalloc_node (sizeof (*ri),GFP_KERNEL , node);if (!ri)return NULL ; + root_ops =kzalloc_node (sizeof (*root_ops),GFP_KERNEL , node); +if (!root_ops) +return NULL ; + ri->cfg =pci_acpi_setup_ecam_mapping (root);if (!ri->cfg) {kfree (ri); +kfree (root_ops);return NULL ; } - acpi_pci_root_ops.pci_ops = &ri->cfg->ops->pci_ops; - bus =acpi_pci_root_create (root, &acpi_pci_root_ops, &ri->common, - ri->cfg); + root_ops->release_info = pci_acpi_generic_release_info; + root_ops->pci_ops = &ri->cfg->ops->pci_ops; + bus =acpi_pci_root_create (root, root_ops, &ri->common, ri->cfg);if (!bus)return NULL ;
Greg Kroah-Hartman
maintainerPATCH 78/152 arm64: PCI: Add local struct device pointers
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Bjorn Helgaas <[email protected]>
[ Upstream commit dfd1972c2b464c10fb585c4c60b594e09d181a01 ]
Use a local "struct device *dev" for brevity. No functional change intended.
--- arch/arm64/kernel/pci.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)
arch/arm64/kernel/pci.c +5 -6
@@ -121,6 +121,7 @@ int pcibios_root_bridge_prepare(struct pstatic struct pci_config_window *pci_acpi_setup_ecam_mapping (struct acpi_pci_root *root) { +struct device *dev = &root->device->dev;struct resource *bus_res = &root->secondary;u16 seg = root->segment;struct pci_config_window *cfg;
@@ -132,8 +133,7 @@ pci_acpi_setup_ecam_mapping(struct acpi_ root->mcfg_addr =pci_mcfg_lookup (seg, bus_res);if (!root->mcfg_addr) { -dev_err (&root->device->dev,"%04x:%pR ECAM region not found\n" , - seg, bus_res); +dev_err (dev,"%04x:%pR ECAM region not found\n" , seg, bus_res);return NULL ; }
@@ -141,11 +141,10 @@ pci_acpi_setup_ecam_mapping(struct acpi_ cfgres.start = root->mcfg_addr + bus_res->start * bsz; cfgres.end = cfgres.start +resource_size (bus_res) * bsz -1 ; cfgres.flags =IORESOURCE_MEM ; - cfg =pci_ecam_create (&root->device->dev, &cfgres, bus_res, - &pci_generic_ecam_ops); + cfg =pci_ecam_create (dev, &cfgres, bus_res, &pci_generic_ecam_ops);if (IS_ERR (cfg)) { -dev_err (&root->device->dev,"%04x:%pR error %ld mapping ECAM\n" , - seg, bus_res,PTR_ERR (cfg)); +dev_err (dev,"%04x:%pR error %ld mapping ECAM\n" , seg, bus_res, +PTR_ERR (cfg));return NULL ; }
Greg Kroah-Hartman
maintainerPATCH 79/152 arm64: PCI: Search ACPI namespace to ensure ECAM space is reserved
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Bjorn Helgaas <[email protected]>
[ Upstream commit 08b1c19606b5fc7f895dae4d43d507b4da4a83bf ]
The static MCFG table tells us the base of ECAM space, but it does not reserve the space -- the reservation should be done via a device in the ACPI namespace whose _CRS includes the ECAM region.
Use acpi_resource_consumer() to check whether the ECAM space is reserved by an ACPI namespace device. If it is, emit a message showing which device reserves it. If not, emit a "[Firmware Bug]" warning.
--- arch/arm64/kernel/pci.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)
arch/arm64/kernel/pci.c +11 -1
@@ -124,8 +124,9 @@ pci_acpi_setup_ecam_mapping(struct acpi_struct device *dev = &root->device->dev;struct resource *bus_res = &root->secondary;u16 seg = root->segment; -struct pci_config_window *cfg;struct resource cfgres; +struct acpi_device *adev; +struct pci_config_window *cfg;unsigned int bsz;/* Use address from _CBA if present, otherwise lookup MCFG */
@@ -141,6 +142,15 @@ pci_acpi_setup_ecam_mapping(struct acpi_ cfgres.start = root->mcfg_addr + bus_res->start * bsz; cfgres.end = cfgres.start +resource_size (bus_res) * bsz -1 ; cfgres.flags =IORESOURCE_MEM ; + + adev =acpi_resource_consumer (&cfgres); +if (adev) +dev_info (dev,"ECAM area %pR reserved by %s\n" , &cfgres, +dev_name (&adev->dev)); +else +dev_warn (dev,FW_BUG "ECAM area %pR not reserved in ACPI namespace\n" , + &cfgres); + cfg =pci_ecam_create (dev, &cfgres, bus_res, &pci_generic_ecam_ops);if (IS_ERR (cfg)) { dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res,
Greg Kroah-Hartman
maintainerPATCH 80/152 PCI/ACPI: Extend pci_mcfg_lookup() to return ECAM config accessors
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tomasz Nowicki <[email protected]>
[ Upstream commit 13983eb89d5afaa65acd4479fad151cbd4de5509 ]
pci_mcfg_lookup() is the external interface to the generic MCFG code. Previously it merely looked up the ECAM base address for a given domain and bus range. We want a way to add MCFG quirks, some of which may require special config accessors and adjustments to the ECAM address range.
Extend pci_mcfg_lookup() so it can return a pointer to a pci_ecam_ops structure and a struct resource for the ECAM address space. For now, it always returns &pci_generic_ecam_ops (the standard accessor) and the resource described by the MCFG.
No functional changes intended.
--- arch/arm64/kernel/pci.c | 17 +++++------------ drivers/acpi/pci_mcfg.c | 28 +++++++++++++++++++++++++--- include/linux/pci-acpi.h | 4 +++- 3 files changed, 33 insertions(+), 16 deletions(-)
arch/arm64/kernel/pci.c +5 -12
@@ -124,25 +124,18 @@ pci_acpi_setup_ecam_mapping(struct acpi_struct device *dev = &root->device->dev;struct resource *bus_res = &root->secondary;u16 seg = root->segment; +struct pci_ecam_ops *ecam_ops;struct resource cfgres;struct acpi_device *adev;struct pci_config_window *cfg; -unsigned int bsz; +int ret; -/* Use address from _CBA if present, otherwise lookup MCFG */ -if (!root->mcfg_addr) - root->mcfg_addr =pci_mcfg_lookup (seg, bus_res); - -if (!root->mcfg_addr) { + ret =pci_mcfg_lookup (root, &cfgres, &ecam_ops); +if (ret) {dev_err (dev,"%04x:%pR ECAM region not found\n" , seg, bus_res);return NULL ; } - bsz =1 << pci_generic_ecam_ops.bus_shift; - cfgres.start = root->mcfg_addr + bus_res->start * bsz; - cfgres.end = cfgres.start +resource_size (bus_res) * bsz -1 ; - cfgres.flags =IORESOURCE_MEM ; - adev =acpi_resource_consumer (&cfgres);if (adev) dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres,
@@ -151,7 +144,7 @@ pci_acpi_setup_ecam_mapping(struct acpi_dev_warn (dev,FW_BUG "ECAM area %pR not reserved in ACPI namespace\n" , &cfgres); - cfg =pci_ecam_create (dev, &cfgres, bus_res, &pci_generic_ecam_ops); + cfg =pci_ecam_create (dev, &cfgres, bus_res, ecam_ops);if (IS_ERR (cfg)) {dev_err (dev,"%04x:%pR error %ld mapping ECAM\n" , seg, bus_res,PTR_ERR (cfg));
drivers/acpi/pci_mcfg.c +25 -3
@@ -22,6 +22,7 @@#include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-acpi.h> +#include <linux/pci-ecam.h> /* Structure to hold entries from the MCFG table */ struct mcfg_entry {
@@ -35,9 +36,18 @@ struct mcfg_entry {/* List to save MCFG entries */ static LIST_HEAD (pci_mcfg_list); -phys_addr_t pci_mcfg_lookup (u16 seg,struct resource *bus_res) +int pci_mcfg_lookup (struct acpi_pci_root *root,struct resource *cfgres, +struct pci_ecam_ops **ecam_ops) { +struct pci_ecam_ops *ops = &pci_generic_ecam_ops; +struct resource *bus_res = &root->secondary; +u16 seg = root->segment;struct mcfg_entry *e; +struct resource res; + +/* Use address from _CBA if present, otherwise lookup MCFG */ +if (root->mcfg_addr) + goto skip_lookup;/* * We expect exact match, unless MCFG entry end bus covers more than
@@ -45,10 +55,22 @@ phys_addr_t pci_mcfg_lookup(u16 seg, str*/ list_for_each_entry (e, &pci_mcfg_list, list) {if (e->segment == seg && e->bus_start == bus_res->start && - e->bus_end >= bus_res->end) -return e->addr; + e->bus_end >= bus_res->end) { + root->mcfg_addr = e->addr; + } + } +if (!root->mcfg_addr) +return -ENXIO ; + +skip_lookup: +memset (&res,0 ,sizeof (res)); + res.start = root->mcfg_addr + (bus_res->start <<20 ); + res.end = res.start + (resource_size (bus_res) <<20 ) -1 ; + res.flags =IORESOURCE_MEM ; + *cfgres = res; + *ecam_ops = ops;return 0 ; }
include/linux/pci-acpi.h +3 -1
@@ -24,7 +24,9 @@ static inline acpi_status pci_acpi_remov }extern phys_addr_t acpi_pci_root_get_mcfg_addr (acpi_handle handle); -extern phys_addr_t pci_mcfg_lookup (u16 domain,struct resource *bus_res); +struct pci_ecam_ops ; +extern int pci_mcfg_lookup (struct acpi_pci_root *root,struct resource *cfgres, +struct pci_ecam_ops **ecam_ops);static inline acpi_handle acpi_find_root_bridge_handle (struct pci_dev *pdev) {
Greg Kroah-Hartman
maintainerPATCH 81/152 PCI/ACPI: Check for platform-specific MCFG quirks
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tomasz Nowicki <[email protected]>
[ Upstream commit 5b69b85ba1ddd36be01f5c57830b37a3c8256009 ]
The PCIe spec (r3.0, sec 7.2.2) specifies an "Enhanced Configuration Access Mechanism" (ECAM) for memory-mapped access to configuration space. ECAM is required for PCIe systems unless there's a standard firmware interface for config access.
In the absence of a firmware interface, we use pci_generic_ecam_ops, and on ACPI systems, we discover the ECAM space via the MCFG table and/or the _CBA method.
Unfortunately some systems provide MCFG but don't implement ECAM according to spec, so we need a mechanism for quirks to make those systems work.
Add an MCFG quirk mechanism to override the config accessor functions and/or the memory-mapped address space.
A quirk is selected if it matches all of the following:
- OEM ID
- OEM Table ID
- OEM Revision
- PCI segment (from _SEG)
- PCI bus number range (from _CRS, wildcard allowed)
If the quirk specifies config accessor functions or a memory-mapped address range, these override the defaults.
[bhelgaas: changelog, reorder quirk matching, fix oem_revision typo per Duc, add under #ifdef CONFIG_PCI_QUIRKS]
--- drivers/acpi/pci_mcfg.c | 92 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 86 insertions(+), 6 deletions(-)
drivers/acpi/pci_mcfg.c +86 -6
@@ -33,6 +33,69 @@ struct mcfg_entry {u8 bus_end; }; +#ifdef CONFIG_PCI_QUIRKS +struct mcfg_fixup { +char oem_id[ACPI_OEM_ID_SIZE +1 ]; +char oem_table_id[ACPI_OEM_TABLE_ID_SIZE +1 ]; +u32 oem_revision; +u16 segment; +struct resource bus_range; +struct pci_ecam_ops *ops; +struct resource cfgres; +}; + +#define MCFG_BUS_RANGE (start, end) DEFINE_RES_NAMED((start), \ + ((end) - (start) + 1), \ + NULL, IORESOURCE_BUS) +#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff) + +static struct mcfg_fixup mcfg_quirks[] = { +/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */ +}; + +static char mcfg_oem_id[ACPI_OEM_ID_SIZE ]; +static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE ]; +static u32 mcfg_oem_revision; + +static int pci_mcfg_quirk_matches (struct mcfg_fixup *f,u16 segment, +struct resource *bus_range) +{ +if (!memcmp (f->oem_id, mcfg_oem_id,ACPI_OEM_ID_SIZE ) && + !memcmp (f->oem_table_id, mcfg_oem_table_id, +ACPI_OEM_TABLE_ID_SIZE ) && + f->oem_revision == mcfg_oem_revision && + f->segment == segment && +resource_contains (&f->bus_range, bus_range)) +return 1 ; + +return 0 ; +} +#endif + +static void pci_mcfg_apply_quirks (struct acpi_pci_root *root, +struct resource *cfgres, +struct pci_ecam_ops **ecam_ops) +{ +#ifdef CONFIG_PCI_QUIRKS +u16 segment = root->segment; +struct resource *bus_range = &root->secondary; +struct mcfg_fixup *f; +int i; + +for (i =0 , f = mcfg_quirks; i <ARRAY_SIZE (mcfg_quirks); i++, f++) { +if (pci_mcfg_quirk_matches (f, segment, bus_range)) { +if (f->cfgres.start) + *cfgres = f->cfgres; +if (f->ops) + *ecam_ops = f->ops; +dev_info (&root->device->dev,"MCFG quirk: ECAM at %pR for %pR with %ps\n" , + cfgres, bus_range, *ecam_ops); +return ; + } + } +#endif +} +/* List to save MCFG entries */ static LIST_HEAD (pci_mcfg_list);
@@ -61,14 +124,24 @@ int pci_mcfg_lookup(struct acpi_pci_root } -if (!root->mcfg_addr) -return -ENXIO ; - skip_lookup:memset (&res,0 ,sizeof (res)); - res.start = root->mcfg_addr + (bus_res->start <<20 ); - res.end = res.start + (resource_size (bus_res) <<20 ) -1 ; - res.flags =IORESOURCE_MEM ; +if (root->mcfg_addr) { + res.start = root->mcfg_addr + (bus_res->start <<20 ); + res.end = res.start + (resource_size (bus_res) <<20 ) -1 ; + res.flags =IORESOURCE_MEM ; + } + +/* +* Allow quirks to override default ECAM ops and CFG resource +* range. This may even fabricate a CFG resource range in case +* MCFG does not have it. Invalid CFG start address means MCFG +* firmware bug or we need another quirk in array. +*/ +pci_mcfg_apply_quirks (root, &res, &ops); +if (!res.start) +return -ENXIO ; + *cfgres = res; *ecam_ops = ops;return 0 ;
@@ -101,6 +174,13 @@ static __init int pci_mcfg_parse(structlist_add (&e->list, &pci_mcfg_list); } +#ifdef CONFIG_PCI_QUIRKS +/* Save MCFG IDs and revision for quirks matching */ +memcpy (mcfg_oem_id, header->oem_id,ACPI_OEM_ID_SIZE ); +memcpy (mcfg_oem_table_id, header->oem_table_id,ACPI_OEM_TABLE_ID_SIZE ); + mcfg_oem_revision = header->oem_revision; +#endif +pr_info ("MCFG table detected, %d entries\n" , n);return 0 ; }
Greg Kroah-Hartman
maintainerPATCH 82/152 PCI: Add MCFG quirks for Qualcomm QDF2432 host controller
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Christopher Covington <[email protected]>
[ Upstream commit 2ca5b8ddc6f70d77a51851ba5e5cd0d39c27dd88 ]
The Qualcomm Technologies QDF2432 SoC does not support accesses smaller than 32 bits to the PCI configuration space. Register the appropriate quirk.
--- drivers/acpi/pci_mcfg.c | 11 +++++++++++ drivers/pci/ecam.c | 12 ++++++++++++ include/linux/pci-ecam.h | 4 ++++ 3 files changed, 27 insertions(+)
drivers/acpi/pci_mcfg.c +11 -0
@@ -51,6 +51,17 @@ struct mcfg_fixup {static struct mcfg_fixup mcfg_quirks[] = {/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */ + +#define QCOM_ECAM32(seg) \ + { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops } +QCOM_ECAM32 (0 ), +QCOM_ECAM32 (1 ), +QCOM_ECAM32 (2 ), +QCOM_ECAM32 (3 ), +QCOM_ECAM32 (4 ), +QCOM_ECAM32 (5 ), +QCOM_ECAM32 (6 ), +QCOM_ECAM32 (7 ), };static char mcfg_oem_id[ACPI_OEM_ID_SIZE ];
drivers/pci/ecam.c +12 -0
@@ -162,3 +162,15 @@ struct pci_ecam_ops pci_generic_ecam_ops .write = pci_generic_config_write, } }; + +#if defined(CONFIG_ACPI ) && defined(CONFIG_PCI_QUIRKS ) +/* ECAM ops for 32-bit access only (non-compliant) */ +struct pci_ecam_ops pci_32b_ops = { + .bus_shift =20 , + .pci_ops = { + .map_bus = pci_ecam_map_bus, + .read = pci_generic_config_read32, + .write = pci_generic_config_write32, + } +}; +#endif
include/linux/pci-ecam.h +4 -0
@@ -59,6 +59,10 @@ void __iomem *pci_ecam_map_bus(struct pc/* default ECAM ops */ extern struct pci_ecam_ops pci_generic_ecam_ops; +#if defined(CONFIG_ACPI ) && defined(CONFIG_PCI_QUIRKS ) +extern struct pci_ecam_ops pci_32b_ops;/* 32-bit accesses only */ +#endif +#ifdef CONFIG_PCI_HOST_GENERIC /* for DT-based PCI controllers that support ECAM */ int pci_host_common_probe(struct platform_device *pdev,
Greg Kroah-Hartman
maintainerPATCH 83/152 PCI: Add MCFG quirks for HiSilicon Hip05/06/07 host controllers
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Dongdong Liu <[email protected]>
[ Upstream commit 5f00f1a0178cf52928366a5e1f376a65f1f3f389 ]
The PCIe controller in Hip05/Hip06/Hip07 SoCs is not completely ECAM-compliant. It is non-ECAM only for the RC bus config space; for any other bus underneath the root bus it does support ECAM access.
Add specific quirks for PCI config space accessors. This involves:
1. New initialization call hisi_pcie_init() to obtain RC base addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
2. New entry in common quirk array.
[bhelgaas: move to pcie-hisi.c and change Makefile/ifdefs so quirk doesn't depend on CONFIG_PCI_HISI]
--- drivers/acpi/pci_mcfg.c | 12 +++++ drivers/pci/host/Makefile | 2 drivers/pci/host/pcie-hisi.c | 101 +++++++++++++++++++++++++++++++++++++++++++ include/linux/pci-ecam.h | 1 4 files changed, 115 insertions(+), 1 deletion(-)
drivers/acpi/pci_mcfg.c +12 -0
@@ -62,6 +62,18 @@ static struct mcfg_fixup mcfg_quirks[] =QCOM_ECAM32 (5 ),QCOM_ECAM32 (6 ),QCOM_ECAM32 (7 ), + +#define HISI_QUAD_DOM(table_id, seg, ops) \ + { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \ + { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \ + { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \ + { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops } +HISI_QUAD_DOM ("HIP05 " ,0 , &hisi_pcie_ops), +HISI_QUAD_DOM ("HIP06 " ,0 , &hisi_pcie_ops), +HISI_QUAD_DOM ("HIP07 " ,0 , &hisi_pcie_ops), +HISI_QUAD_DOM ("HIP07 " ,4 , &hisi_pcie_ops), +HISI_QUAD_DOM ("HIP07 " ,8 , &hisi_pcie_ops), + HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops), };static char mcfg_oem_id[ACPI_OEM_ID_SIZE ];
drivers/pci/host/Makefile +1 -1
@@ -25,7 +25,7 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pci obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o -obj-$(CONFIG_PCI_HISI) += pcie-hisi.o +obj-$(CONFIG_ARM64) += pcie-hisi.o obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
drivers/pci/host/pcie-hisi.c +101 -0
111 lines not on this page · raw message
include/linux/pci-ecam.h +1 -0
@@ -61,6 +61,7 @@ extern struct pci_ecam_ops pci_generic_e#if defined(CONFIG_ACPI ) && defined(CONFIG_PCI_QUIRKS )extern struct pci_ecam_ops pci_32b_ops;/* 32-bit accesses only */ +extern struct pci_ecam_ops hisi_pcie_ops;/* HiSilicon */ #endif #ifdef CONFIG_PCI_HOST_GENERIC
Greg Kroah-Hartman
maintainerPATCH 84/152 PCI: thunder-pem: Factor out resource lookup
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Bjorn Helgaas <[email protected]>
[ Upstream commit 0d414268fb8d0844030f87027e904f69d96706be ]
Pull the register resource lookup out of thunder_pem_init() so we can easily add a corresponding lookup using ACPI. No functional change intended.
--- drivers/pci/host/pci-thunder-pem.c | 50 +++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 23 deletions(-)
drivers/pci/host/pci-thunder-pem.c +27 -23
@@ -284,35 +284,16 @@ static int thunder_pem_config_write(strureturn pci_generic_config_write (bus, devfn, where, size, val); } -static int thunder_pem_init (struct pci_config_window *cfg) +static int thunder_pem_init (struct device *dev,struct pci_config_window *cfg, +struct resource *res_pem) { -struct device *dev = cfg->parent; -resource_size_t bar4_start; -struct resource *res_pem;struct thunder_pem_pci *pem_pci; -struct platform_device *pdev; - -/* Only OF support for now */ -if (!dev->of_node) -return -EINVAL ; +resource_size_t bar4_start; pem_pci =devm_kzalloc (dev,sizeof (*pem_pci),GFP_KERNEL );if (!pem_pci)return -ENOMEM ; - pdev =to_platform_device (dev); - -/* -* The second register range is the PEM bridge to the PCIe -* bus. It has a different config access method than those -* devices behind the bridge. -*/ - res_pem =platform_get_resource (pdev,IORESOURCE_MEM ,1 ); -if (!res_pem) { -dev_err (dev,"missing \"reg[1]\"property\n" ); -return -EINVAL ; - } - pem_pci->pem_reg_base =devm_ioremap (dev, res_pem->start,0x10000 );if (!pem_pci->pem_reg_base)return -ENOMEM ;
@@ -332,9 +313,32 @@ static int thunder_pem_init(struct pci_creturn 0 ; } +static int thunder_pem_platform_init (struct pci_config_window *cfg) +{ +struct device *dev = cfg->parent; +struct platform_device *pdev =to_platform_device (dev); +struct resource *res_pem; + +if (!dev->of_node) +return -EINVAL ; + +/* +* The second register range is the PEM bridge to the PCIe +* bus. It has a different config access method than those +* devices behind the bridge. +*/ + res_pem =platform_get_resource (pdev,IORESOURCE_MEM ,1 ); +if (!res_pem) { +dev_err (dev,"missing \"reg[1]\"property\n" ); +return -EINVAL ; + } + +return thunder_pem_init (dev, cfg, res_pem); +} +static struct pci_ecam_ops pci_thunder_pem_ops = { .bus_shift =24 , - .init = thunder_pem_init, + .init = thunder_pem_platform_init, .pci_ops = { .map_bus = pci_ecam_map_bus, .read = thunder_pem_config_read,
Greg Kroah-Hartman
maintainerPATCH 85/152 PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tomasz Nowicki <[email protected]>
[ Upstream commit 44f22bd91e88f9a1203a6e564a237e593f5f2f74 ]
ThunderX PCIe controller to off-chip devices (so-called PEM) is not fully compliant with ECAM standard. It uses non-standard configuration space accessors (see thunder_pem_ecam_ops) and custom configuration space granulation (see bus_shift = 24). In order to access configuration space and probe PEM as ACPI-based PCI host controller we need to add MCFG quirk infrastructure. This involves:
1. A new thunder_pem_acpi_init() init function to locate PEM-specific register ranges using ACPI.
2. Export PEM thunder_pem_ecam_ops structure so it is visible to MCFG quirk code.
3. New quirk entries for each PEM segment. Each contains platform IDs, mentioned thunder_pem_ecam_ops and CFG resources.
Quirk is considered for ThunderX silicon pass2.x only which is identified via MCFG revision 1.
ThunderX pass 2.x requires the following accessors:
NUMA Node 0 PCI segments 0- 3: pci_generic_ecam_ops (ECAM-compliant) NUMA Node 0 PCI segments 4- 9: thunder_pem_ecam_ops (MCFG quirk) NUMA Node 1 PCI segments 10-13: pci_generic_ecam_ops (ECAM-compliant) NUMA Node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk)
[bhelgaas: adapt to use acpi_get_rc_resources(), update Makefile/ifdefs so quirk doesn't depend on CONFIG_PCI_HOST_THUNDER_PEM]
--- drivers/acpi/pci_mcfg.c | 19 +++++++++++++++ drivers/pci/host/Kconfig | 3 +- drivers/pci/host/Makefile | 2 - drivers/pci/host/pci-thunder-pem.c | 44 +++++++++++++++++++++++++++++++++++++ include/linux/pci-ecam.h | 1 5 files changed, 67 insertions(+), 2 deletions(-)
drivers/acpi/pci_mcfg.c +19 -0
@@ -74,6 +74,25 @@ static struct mcfg_fixup mcfg_quirks[] = HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops), HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops), HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops), + +#define THUNDER_PEM_RES (addr, node) \ + DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M) +#define THUNDER_PEM_QUIRK (rev, node) \ + { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \ + &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \ + { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \ + &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \ + { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \ + &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \ + { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \ + &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \ + { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \ + &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \ + { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \ + &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) } +/* SoC pass2.x */ + THUNDER_PEM_QUIRK(1, 0), + THUNDER_PEM_QUIRK(1, 1), };static char mcfg_oem_id[ACPI_OEM_ID_SIZE ];
drivers/pci/host/Kconfig +2 -1
@@ -240,7 +240,8 @@ config PCIE_QCOM config PCI_HOST_THUNDER_PEM bool "Cavium Thunder PCIe controller to off-chip devices" - depends on OF && ARM64 + depends on ARM64 + depends on OF || (ACPI && PCI_QUIRKS) select PCI_HOST_COMMON help Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.
drivers/pci/host/Makefile +1 -1
@@ -28,7 +28,7 @@ obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-al obj-$(CONFIG_ARM64) += pcie-hisi.o obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o -obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o +obj-$(CONFIG_ARM64) += pci-thunder-pem.o obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
drivers/pci/host/pci-thunder-pem.c +44 -0
61 lines not on this page · raw message
include/linux/pci-ecam.h +1 -0
@@ -62,6 +62,7 @@ extern struct pci_ecam_ops pci_generic_e#if defined(CONFIG_ACPI ) && defined(CONFIG_PCI_QUIRKS )extern struct pci_ecam_ops pci_32b_ops;/* 32-bit accesses only */ extern struct pci_ecam_ops hisi_pcie_ops;/* HiSilicon */ +extern struct pci_ecam_ops thunder_pem_ecam_ops;/* Cavium ThunderX 2.x */ #endif #ifdef CONFIG_PCI_HOST_GENERIC
Greg Kroah-Hartman
maintainerPATCH 86/152 PCI: Add MCFG quirks for Cavium ThunderX pass1.x host controller
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tomasz Nowicki <[email protected]>
[ Upstream commit 648d93fc77da4f655cf13108417f33c91d745e2c ]
ThunderX pass1.x requires to emulate the EA headers for on-chip devices hence it has to use custom pci_thunder_ecam_ops for accessing PCI config space (pci-thunder-ecam.c). Add new entries to MCFG quirk array where it can be applied while probing ACPI based PCI host controller.
ThunderX pass1.x is using the same way for accessing off-chip devices (so-called PEM) as silicon pass-2.x so we need to add PEM quirk entries too.
Quirk is considered for ThunderX silicon pass1.x only which is identified via MCFG revision 2.
ThunderX pass 1.x requires the following accessors:
NUMA node 0 PCI segments 0- 3: pci_thunder_ecam_ops (MCFG quirk) NUMA node 0 PCI segments 4- 9: thunder_pem_ecam_ops (MCFG quirk) NUMA node 1 PCI segments 10-13: pci_thunder_ecam_ops (MCFG quirk) NUMA node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk)
[bhelgaas: change Makefile/ifdefs so quirk doesn't depend on CONFIG_PCI_HOST_THUNDER_ECAM]
--- drivers/acpi/pci_mcfg.c | 15 +++++++++++++++ drivers/pci/host/Kconfig | 3 ++- drivers/pci/host/Makefile | 2 +- drivers/pci/host/pci-thunder-ecam.c | 9 ++++++++- include/linux/pci-ecam.h | 3 ++- 5 files changed, 28 insertions(+), 4 deletions(-)
drivers/acpi/pci_mcfg.c +15 -0
@@ -93,6 +93,21 @@ static struct mcfg_fixup mcfg_quirks[] =/* SoC pass2.x */ THUNDER_PEM_QUIRK (1 ,0 ),THUNDER_PEM_QUIRK (1 ,1 ), + +#define THUNDER_ECAM_QUIRK(rev, seg) \ + { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \ + &pci_thunder_ecam_ops } +/* SoC pass1.x */ +THUNDER_PEM_QUIRK (2 ,0 ),/* off-chip devices */ +THUNDER_PEM_QUIRK (2 ,1 ),/* off-chip devices */ +THUNDER_ECAM_QUIRK (2 ,0 ), +THUNDER_ECAM_QUIRK (2 ,1 ), +THUNDER_ECAM_QUIRK (2 ,2 ), +THUNDER_ECAM_QUIRK (2 ,3 ), +THUNDER_ECAM_QUIRK (2 ,10 ), +THUNDER_ECAM_QUIRK (2 ,11 ), +THUNDER_ECAM_QUIRK (2 ,12 ), + THUNDER_ECAM_QUIRK(2, 13), };static char mcfg_oem_id[ACPI_OEM_ID_SIZE ];
drivers/pci/host/Kconfig +2 -1
@@ -248,7 +248,8 @@ config PCI_HOST_THUNDER_PEM config PCI_HOST_THUNDER_ECAM bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon" - depends on OF && ARM64 + depends on ARM64 + depends on OF || (ACPI && PCI_QUIRKS) select PCI_HOST_COMMON help Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
drivers/pci/host/Makefile +1 -1
@@ -27,7 +27,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o obj-$(CONFIG_ARM64) += pcie-hisi.o obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o -obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o +obj-$(CONFIG_ARM64) += pci-thunder-ecam.o obj-$(CONFIG_ARM64) += pci-thunder-pem.o obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
drivers/pci/host/pci-thunder-ecam.c +8 -1
@@ -14,6 +14,8 @@#include <linux/pci-ecam.h> #include <linux/platform_device.h> +#if defined(CONFIG_PCI_HOST_THUNDER_ECAM ) || (defined(CONFIG_ACPI ) && defined(CONFIG_PCI_QUIRKS )) +static void set_val (u32 v,int where,int size,u32 *val) {int shift = (where &3 ) *8 ;
@@ -346,7 +348,7 @@ static int thunder_ecam_config_write(strreturn pci_generic_config_write (bus, devfn, where, size, val); } -static struct pci_ecam_ops pci_thunder_ecam_ops = { +struct pci_ecam_ops pci_thunder_ecam_ops = { .bus_shift =20 , .pci_ops = { .map_bus = pci_ecam_map_bus,
@@ -355,6 +357,8 @@ static struct pci_ecam_ops pci_thunder_e } }; +#ifdef CONFIG_PCI_HOST_THUNDER_ECAM +static const struct of_device_id thunder_ecam_of_match[] = { { .compatible ="cavium,pci-host-thunder-ecam" }, { },
@@ -373,3 +377,6 @@ static struct platform_driver thunder_ec .probe = thunder_ecam_probe, };builtin_platform_driver (thunder_ecam_driver); + +#endif +#endif
include/linux/pci-ecam.h +2 -1
@@ -62,7 +62,8 @@ extern struct pci_ecam_ops pci_generic_e#if defined(CONFIG_ACPI ) && defined(CONFIG_PCI_QUIRKS )extern struct pci_ecam_ops pci_32b_ops;/* 32-bit accesses only */ extern struct pci_ecam_ops hisi_pcie_ops;/* HiSilicon */ -extern struct pci_ecam_ops thunder_pem_ecam_ops;/* Cavium ThunderX 2.x */ +extern struct pci_ecam_ops thunder_pem_ecam_ops;/* Cavium ThunderX 1.x & 2.x */ +extern struct pci_ecam_ops pci_thunder_ecam_ops;/* Cavium ThunderX 1.x */ #endif #ifdef CONFIG_PCI_HOST_GENERIC
Greg Kroah-Hartman
maintainerPATCH 87/152 PCI: Add MCFG quirks for X-Gene host controller
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Duc Dang <[email protected]>
[ Upstream commit c5d4603961009c39de94725213d8b5420f110f9e ]
PCIe controllers in X-Gene SoCs are not ECAM compliant: software needs to configure additional controller's register to address device at bus:dev:function.
Add a quirk to discover controller MMIO register space and configure controller registers to select and address the target secondary device.
The quirk will only be applied for X-Gene PCIe MCFG table with OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).
--- drivers/acpi/pci_mcfg.c | 25 ++++++++ drivers/pci/host/Kconfig | 4 - drivers/pci/host/Makefile | 2 drivers/pci/host/pci-xgene.c | 126 ++++++++++++++++++++++++++++++++++++++++--- include/linux/pci-ecam.h | 2 5 files changed, 149 insertions(+), 10 deletions(-)
drivers/acpi/pci_mcfg.c +25 -0
@@ -108,6 +108,31 @@ static struct mcfg_fixup mcfg_quirks[] =THUNDER_ECAM_QUIRK (2 ,11 ),THUNDER_ECAM_QUIRK (2 ,12 ),THUNDER_ECAM_QUIRK (2 ,13 ), + +#define XGENE_V1_ECAM_MCFG(rev, seg) \ + {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \ + &xgene_v1_pcie_ecam_ops } +#define XGENE_V2_ECAM_MCFG(rev, seg) \ + {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \ + &xgene_v2_pcie_ecam_ops } +/* X-Gene SoC with v1 PCIe controller */ +XGENE_V1_ECAM_MCFG (1 ,0 ), +XGENE_V1_ECAM_MCFG (1 ,1 ), +XGENE_V1_ECAM_MCFG (1 ,2 ), +XGENE_V1_ECAM_MCFG (1 ,3 ), +XGENE_V1_ECAM_MCFG (1 ,4 ), +XGENE_V1_ECAM_MCFG (2 ,0 ), +XGENE_V1_ECAM_MCFG (2 ,1 ), +XGENE_V1_ECAM_MCFG (2 ,2 ), +XGENE_V1_ECAM_MCFG (2 ,3 ), +XGENE_V1_ECAM_MCFG (2 ,4 ), +/* X-Gene SoC with v2.1 PCIe controller */ +XGENE_V2_ECAM_MCFG (3 ,0 ), +XGENE_V2_ECAM_MCFG (3 ,1 ), +/* X-Gene SoC with v2.2 PCIe controller */ +XGENE_V2_ECAM_MCFG (4 ,0 ), +XGENE_V2_ECAM_MCFG (4 ,1 ), + XGENE_V2_ECAM_MCFG(4, 2), };static char mcfg_oem_id[ACPI_OEM_ID_SIZE ];
drivers/pci/host/Kconfig +2 -2
@@ -133,8 +133,8 @@ config PCIE_XILINX config PCI_XGENE bool "X-Gene PCIe controller" - depends on ARCH_XGENE - depends on OF + depends on ARM64 + depends on OF || (ACPI && PCI_QUIRKS) select PCIEPORTBUS help Say Y here if you want internal PCI support on APM X-Gene SoC.
drivers/pci/host/Makefile +1 -1
@@ -15,7 +15,7 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spe obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o -obj-$(CONFIG_PCI_XGENE) += pci-xgene.o +obj-$(CONFIG_ARM64) += pci-xgene.o obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
drivers/pci/host/pci-xgene.c +119 -7
181 lines not on this page · raw message
include/linux/pci-ecam.h +2 -0
@@ -64,6 +64,8 @@ extern struct pci_ecam_ops pci_32b_ops;extern struct pci_ecam_ops hisi_pcie_ops;/* HiSilicon */ extern struct pci_ecam_ops thunder_pem_ecam_ops;/* Cavium ThunderX 1.x & 2.x */ extern struct pci_ecam_ops pci_thunder_ecam_ops;/* Cavium ThunderX 1.x */ +extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops;/* APM X-Gene PCIe v1 */ +extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops;/* APM X-Gene PCIe v2.x */ #endif #ifdef CONFIG_PCI_HOST_GENERIC
Greg Kroah-Hartman
maintainerPATCH 88/152 PCI: Explain ARM64 ACPI/MCFG quirk Kconfig and build strategy
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Bjorn Helgaas <[email protected]>
[ Upstream commit ca5ab37b19dfd1d77787d0474b767ec1185670f4 ]
Add Makefile comments to explain the Kconfig and build strategy for ARM64 drivers that work around not-quite-ECAM issues. No functional change intended.
--- drivers/pci/host/Makefile | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-)
drivers/pci/host/Makefile +15 -4
@@ -15,7 +15,6 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spe obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o -obj-$(CONFIG_ARM64) += pci-xgene.o obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
@@ -25,11 +24,23 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pci obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o -obj-$(CONFIG_ARM64) += pcie-hisi.o obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o -obj-$(CONFIG_ARM64) += pci-thunder-ecam.o -obj-$(CONFIG_ARM64) += pci-thunder-pem.o obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o obj-$(CONFIG_VMD) += vmd.o + +# The following drivers are for devices that use the generic ACPI +# pci_root.c driver but don't support standard ECAM config access. +# They contain MCFG quirks to replace the generic ECAM accessors with +# device-specific ones that are shared with the DT driver. + +# The ACPI driver is generic and should not require driver-specific +# config options to be enabled, so we always build these drivers on +# ARM64 and use internal ifdefs to only build the pieces we need +# depending on whether ACPI, the DT driver, or both are enabled. + +obj-$(CONFIG_ARM64) += pcie-hisi.o +obj-$(CONFIG_ARM64) += pci-thunder-ecam.o +obj-$(CONFIG_ARM64) += pci-thunder-pem.o +obj-$(CONFIG_ARM64) += pci-xgene.o
Greg Kroah-Hartman
maintainerPATCH 89/152 scsi: ufs: add quirk to increase host PA_SaveConfigTime
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Subhash Jadavani <[email protected]>
[ Upstream commit 56d4a1866d748732fd8d690b2c2156bbc9c9eb02 ]
The maximum value PA_SaveConfigTime is 250 (10us) but this is not enough for some vendors. Gear switch from PWM to HS may fail even with this max. PA_SaveConfigTime. Gear switch can be issued by host controller as an error recovery and any software delay will not help on this case so we need to increase PA_SaveConfigTime to >32us as per vendor recommendation. This change adds a quirk to increase the PA_SaveConfigTime parameter.
--- drivers/scsi/ufs/ufs-qcom.c | 30 ++++++++++++++++++++++++++++++ drivers/scsi/ufs/ufs-qcom.h | 1 + drivers/scsi/ufs/ufs_quirks.h | 30 +++++++++--------------------- drivers/scsi/ufs/ufshcd.c | 26 ++++++++++++++++++++++++++ drivers/scsi/ufs/ufshcd.h | 9 +++++++++ 5 files changed, 75 insertions(+), 21 deletions(-)
drivers/scsi/ufs/ufs-qcom.c +30 -0
@@ -23,6 +23,7 @@#include "unipro.h" #include "ufs-qcom.h" #include "ufshci.h" +#include "ufs_quirks.h" #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \ (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
@@ -1031,6 +1032,34 @@ out:return ret; } +static int ufs_qcom_quirk_host_pa_saveconfigtime (struct ufs_hba *hba) +{ +int err; +u32 pa_vs_config_reg1; + + err =ufshcd_dme_get (hba,UIC_ARG_MIB (PA_VS_CONFIG_REG1 ), + &pa_vs_config_reg1); +if (err) + goto out; + +/* Allow extension of MSB bits of PA_SaveConfigTime attribute */ + err =ufshcd_dme_set (hba,UIC_ARG_MIB (PA_VS_CONFIG_REG1 ), + (pa_vs_config_reg1 | (1 <<12 ))); + +out: +return err; +} + +static int ufs_qcom_apply_dev_quirks (struct ufs_hba *hba) +{ +int err =0 ; + +if (hba->dev_quirks &UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME ) + err =ufs_qcom_quirk_host_pa_saveconfigtime (hba); + +return err; +} +static u32 ufs_qcom_get_ufs_hci_version (struct ufs_hba *hba) {struct ufs_qcom_host *host =ufshcd_get_variant (hba);
@@ -1616,6 +1645,7 @@ static struct ufs_hba_variant_ops ufs_hb .hce_enable_notify = ufs_qcom_hce_enable_notify, .link_startup_notify = ufs_qcom_link_startup_notify, .pwr_change_notify = ufs_qcom_pwr_change_notify, + .apply_dev_quirks = ufs_qcom_apply_dev_quirks, .suspend = ufs_qcom_suspend, .resume = ufs_qcom_resume, .dbg_register_dump = ufs_qcom_dump_dbg_regs,
drivers/scsi/ufs/ufs-qcom.h +1 -0
@@ -142,6 +142,7 @@ enum ufs_qcom_phy_init_type { UFS_QCOM_DBG_PRINT_TEST_BUS_EN)/* QUniPro Vendor specific attributes */ +#define PA_VS_CONFIG_REG1 0x9000#define DME_VS_CORE_CLK_CTRL 0xD002/* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
drivers/scsi/ufs/ufs_quirks.h +9 -21
@@ -134,29 +134,17 @@ struct ufs_dev_fix {*/ #define UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE (1 << 7) +/* +* The max. value PA_SaveConfigTime is 250 (10us) but this is not enough for +* some vendors. +* Gear switch from PWM to HS may fail even with this max. PA_SaveConfigTime. +* Gear switch can be issued by host controller as an error recovery and any +* software delay will not help on this case so we need to increase +* PA_SaveConfigTime to >32us as per vendor recommendation. +*/ +#define UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME (1 << 8)struct ufs_hba ;void ufs_advertise_fixup_device (struct ufs_hba *hba); -static struct ufs_dev_fix ufs_fixups[] = { -/* UFS cards deviations table */ -UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL , -UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM ), -UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL ,UFS_DEVICE_NO_VCCQ ), -UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL , -UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS ), -UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL , -UFS_DEVICE_NO_FASTAUTO ), -UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL , -UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE ), -UFS_FIX (UFS_VENDOR_TOSHIBA ,UFS_ANY_MODEL , -UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM ), -UFS_FIX (UFS_VENDOR_TOSHIBA ,"THGLF2G9C8KBADG" , -UFS_DEVICE_QUIRK_PA_TACTIVATE ), -UFS_FIX (UFS_VENDOR_TOSHIBA ,"THGLF2G9D8KBADG" , -UFS_DEVICE_QUIRK_PA_TACTIVATE ), -UFS_FIX (UFS_VENDOR_SKHYNIX ,UFS_ANY_MODEL ,UFS_DEVICE_NO_VCCQ ), - -END_FIX -};#endif /* UFS_QUIRKS_H_ */
drivers/scsi/ufs/ufshcd.c +26 -0
@@ -188,6 +188,30 @@ ufs_get_pm_lvl_to_link_pwr_state(enum ufreturn ufs_pm_lvl_states[lvl].link_state; } +static struct ufs_dev_fix ufs_fixups[] = { +/* UFS cards deviations table */ +UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL , +UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM ), +UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL ,UFS_DEVICE_NO_VCCQ ), +UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL , +UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS ), +UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL , +UFS_DEVICE_NO_FASTAUTO ), +UFS_FIX (UFS_VENDOR_SAMSUNG ,UFS_ANY_MODEL , +UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE ), +UFS_FIX (UFS_VENDOR_TOSHIBA ,UFS_ANY_MODEL , +UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM ), +UFS_FIX (UFS_VENDOR_TOSHIBA ,"THGLF2G9C8KBADG" , +UFS_DEVICE_QUIRK_PA_TACTIVATE ), +UFS_FIX (UFS_VENDOR_TOSHIBA ,"THGLF2G9D8KBADG" , +UFS_DEVICE_QUIRK_PA_TACTIVATE ), +UFS_FIX (UFS_VENDOR_SKHYNIX ,UFS_ANY_MODEL ,UFS_DEVICE_NO_VCCQ ), +UFS_FIX (UFS_VENDOR_SKHYNIX ,UFS_ANY_MODEL , +UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME ), + +END_FIX +}; +static void ufshcd_tmc_handler (struct ufs_hba *hba);static void ufshcd_async_scan (void *data,async_cookie_t cookie);static int ufshcd_reset_and_restore (struct ufs_hba *hba);
@@ -5062,6 +5086,8 @@ static void ufshcd_tune_unipro_params(stif (hba->dev_quirks &UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE )ufshcd_quirk_tune_host_pa_tactivate (hba); + +ufshcd_vops_apply_dev_quirks (hba); }/**
drivers/scsi/ufs/ufshcd.h +9 -0
@@ -261,6 +261,7 @@ struct ufs_pwr_mode_info {* @pwr_change_notify: called before and after a power mode change * is carried out to allow vendor spesific capabilities * to be set. +* @apply_dev_quirks: called to apply device specific quirks * @suspend: called during host controller PM callback * @resume: called during host controller PM callback * @dbg_register_dump: used to dump controller debug information
@@ -283,6 +284,7 @@ struct ufs_hba_variant_ops {enum ufs_notify_change_status status, struct ufs_pa_layer_attr *, struct ufs_pa_layer_attr *); +int (*apply_dev_quirks)(struct ufs_hba *);int (*suspend)(struct ufs_hba *,enum ufs_pm_op );int (*resume)(struct ufs_hba *,enum ufs_pm_op );void (*dbg_register_dump)(struct ufs_hba *hba);
@@ -805,6 +807,13 @@ static inline int ufshcd_vops_pwr_changereturn -ENOTSUPP ; } +static inline int ufshcd_vops_apply_dev_quirks (struct ufs_hba *hba) +{ +if (hba->vops && hba->vops->apply_dev_quirks) +return hba->vops->apply_dev_quirks (hba); +return 0 ; +} +static inline int ufshcd_vops_suspend (struct ufs_hba *hba,enum ufs_pm_op op) {if (hba->vops && hba->vops->suspend)
Greg Kroah-Hartman
maintainerPATCH 90/152 ALSA: usb-audio: add implicit fb quirk for Axe-Fx II
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Alberto Aguirre <[email protected]>
[ Upstream commit 17f08b0d9aafccdb10038ab6dbd9ddb6433c13e2 ]
The Axe-Fx II implicit feedback end point and the data sync endpoint are in different interface descriptors. Add quirk to ensure a sync endpoint is properly configured.
--- sound/usb/pcm.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
sound/usb/pcm.c +10 -0
@@ -348,6 +348,16 @@ static int set_sync_ep_implicit_fb_quirk alts = &iface->altsetting[1 ]; goto add_sync_ep; +case USB_ID (0x2466 ,0x8003 ): + ep =0x86 ; + iface =usb_ifnum_to_if (dev,2 ); + +if (!iface || iface->num_altsetting ==0 ) +return -EINVAL ; + + alts = &iface->altsetting[1 ]; + goto add_sync_ep; + } if (attr == USB_ENDPOINT_SYNC_ASYNC && altsd->bInterfaceClass == USB_CLASS_VENDOR_SPEC &&
Greg Kroah-Hartman
maintainerPATCH 91/152 PCI: Expand "VPD access disabled" quirk message
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Bjorn Helgaas <[email protected]>
[ Upstream commit 044bc425bb72ffdecfb2a66d50cb1d024ecb96d0 ]
It's not very enlightening to see
pci 0000:07:00.0: [Firmware Bug]: VPD access disabled
in the dmesg log because there's no clue about what the firmware bug is. Expand the message to explain why we're disabling VPD.
--- drivers/pci/quirks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pci/quirks.c +1 -1
@@ -2156,7 +2156,7 @@ static void quirk_blacklist_vpd(struct p {if (dev->vpd) { dev->vpd->len =0 ; -dev_warn (&dev->dev,FW_BUG "VPD access disabled\n" ); +dev_warn (&dev->dev,FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n" ); } }
Greg Kroah-Hartman
maintainerPATCH 92/152 ALSA: usb-audio: Add native DSD support for TEAC 501/503 DAC
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Nobutaka Okabe <[email protected]>
[ Upstream commit 7f38ca047b0cb54df7f6d9e4110e292e45dba6ad ]
This patch adds native DSD support for the following devices.
- TEAC NT-503
- TEAC UD-503
- TEAC UD-501
(1) Add quirks for native DSD support for TEAC devices.
(2) A specific vendor command is needed to switch between PCM/DOP and DSD mode, same as Denon/Marantz devices.
--- sound/usb/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
sound/usb/quirks.c +38 -0
@@ -1166,6 +1166,18 @@ static bool is_marantz_denon_dac(unsignereturn false; } +/* TEAC UD-501/UD-503/NT-503 USB DACs need a vendor cmd to switch +* between PCM/DOP and native DSD mode +*/ +static bool is_teac_50X_dac (unsigned int id) +{ +switch (id) { +case USB_ID (0x0644 ,0x8043 ):/* TEAC UD-501/UD-503/NT-503 */ +return true; + } +return false; +} +int snd_usb_select_mode_quirk (struct snd_usb_substream *subs,struct audioformat *fmt) {
@@ -1193,6 +1205,26 @@ int snd_usb_select_mode_quirk(struct sndbreak ; }mdelay (20 ); + }else if (is_teac_50X_dac (subs->stream->chip->usb_id)) { +/* Vendor mode switch cmd is required. */ +switch (fmt->altsetting) { +case 3 :/* DSD mode (DSD_U32) requested */ + err =snd_usb_ctl_msg (dev,usb_sndctrlpipe (dev,0 ),0 , +USB_DIR_OUT |USB_TYPE_VENDOR |USB_RECIP_INTERFACE , +1 ,1 ,NULL ,0 ); +if (err <0 ) +return err; +break ; + +case 2 :/* PCM or DOP mode (S32) requested */ +case 1 :/* PCM mode (S16) requested */ + err =snd_usb_ctl_msg (dev,usb_sndctrlpipe (dev,0 ),0 , +USB_DIR_OUT |USB_TYPE_VENDOR |USB_RECIP_INTERFACE , +0 ,1 ,NULL ,0 ); +if (err <0 ) +return err; +break ; + } }return 0 ; }
@@ -1338,5 +1370,11 @@ u64 snd_usb_interface_dsd_format_quirks(return SNDRV_PCM_FMTBIT_DSD_U32_BE ; } +/* TEAC devices with USB DAC functionality */ +if (is_teac_50X_dac (chip->usb_id)) { +if (fp->altsetting ==3 ) +return SNDRV_PCM_FMTBIT_DSD_U32_BE ; + } +return 0 ; }
Greg Kroah-Hartman
maintainerPATCH 94/152 HID: asus: Add i2c touchpad support
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Brendan McGrath <[email protected]>
[ Upstream commit 9ce12d8be12c94334634dd57050444910415e45f ]
Update the hid-asus module to add multitouch support for the Asus i2c touchpad.
This patch aims to resolve the issue raised here:
https://bugzilla.kernel.org/show_bug.cgi?id=120181
The issue is in relation to an Asus touchpad device which currently does not have multitouch support.
The device currently falls through to the hid-generic driver which treats the device as a mouse.
This patch aims to add the multitouch support.
--- drivers/hid/Kconfig | 2 drivers/hid/hid-asus.c | 299 ++++++++++++++++++++++++++++++++++++++++++++++++- drivers/hid/hid-core.c | 1 drivers/hid/hid-ids.h | 1 4 files changed, 296 insertions(+), 7 deletions(-)
drivers/hid/Kconfig +1 -1
@@ -138,7 +138,7 @@ config HID_ASUS tristate "Asus" depends on I2C_HID ---help--- - Support for Asus notebook built-in keyboard via i2c. + Support for Asus notebook built-in keyboard and touchpad via i2c. Supported devices: - EeeBook X205TA
drivers/hid/hid-asus.c +293 -6
330 lines not on this page · raw message
drivers/hid/hid-core.c +1 -0
@@ -1856,6 +1856,7 @@ static const struct hid_device_id hid_ha { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY) }, { HID_I2C_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_NOTEBOOK_KEYBOARD) }, + { HID_I2C_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_TOUCHPAD) }, { HID_USB_DEVICE(USB_VENDOR_ID_AUREAL, USB_DEVICE_ID_AUREAL_W01RN) }, { HID_USB_DEVICE(USB_VENDOR_ID_BELKIN, USB_DEVICE_ID_FLIP_KVM) }, { HID_USB_DEVICE(USB_VENDOR_ID_BETOP_2185BFM, 0x2208) },
drivers/hid/hid-ids.h +1 -0
@@ -174,6 +174,7 @@#define USB_DEVICE_ID_ASUSTEK_LCM 0x1726#define USB_DEVICE_ID_ASUSTEK_LCM2 0x175b#define USB_DEVICE_ID_ASUSTEK_NOTEBOOK_KEYBOARD 0x8585 +#define USB_DEVICE_ID_ASUSTEK_TOUCHPAD 0x0101#define USB_VENDOR_ID_ATEN 0x0557#define USB_DEVICE_ID_ATEN_UC100KM 0x2004
Greg Kroah-Hartman
maintainerPATCH 95/152 HID: asus: Fix keyboard support
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Brendan McGrath <[email protected]>
[ Upstream commit c8b1b3dd89ea7b3f77a73e59c4c4495e16338e15 ]
The previous submission which added Touchpad support broke the Keyboard support of this driver. This patch:
1. fixes the Keyboard support (by assigning drvdata->input);
2. renames NOTEBOOK_QUIRKS to KEYBOARD_QUIRKS;
3. adds the NO_INIT_REPORT quirk to the KEYBOARD_QUIRKS; and
4. sets the input->name to 'Asus Keyboard' for the keyboard
--- drivers/hid/hid-asus.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-)
drivers/hid/hid-asus.c +11 -6
@@ -64,7 +64,8 @@ MODULE_DESCRIPTION("Asus HID Keyboard an#define QUIRK_SKIP_INPUT_MAPPING BIT(2)#define QUIRK_IS_MULTITOUCH BIT(3) -#define NOTEBOOK_QUIRKS QUIRK_FIX_NOTEBOOK_REPORT +#define KEYBOARD_QUIRKS (QUIRK_FIX_NOTEBOOK_REPORT | \ + QUIRK_NO_INIT_REPORTS)#define TOUCHPAD_QUIRKS (QUIRK_NO_INIT_REPORTS | \ QUIRK_SKIP_INPUT_MAPPING | \ QUIRK_IS_MULTITOUCH)
@@ -170,11 +171,11 @@ static int asus_raw_event(struct hid_devstatic int asus_input_configured (struct hid_device *hdev,struct hid_input *hi) { +struct input_dev *input = hi->input;struct asus_drvdata *drvdata =hid_get_drvdata (hdev);if (drvdata->quirks &QUIRK_IS_MULTITOUCH ) {int ret; -struct input_dev *input = hi->input;input_set_abs_params (input,ABS_MT_POSITION_X ,0 ,MAX_X ,0 ,0 );input_set_abs_params (input,ABS_MT_POSITION_Y ,0 ,MAX_Y ,0 ,0 );
@@ -191,10 +192,10 @@ static int asus_input_configured(structhid_err (hdev,"Asus input mt init slots failed: %d\n" , ret);return ret; } - - drvdata->input = input; } + drvdata->input = input; +return 0 ; }
@@ -286,7 +287,11 @@ static int asus_probe(struct hid_device goto err_stop_hw; } - drvdata->input->name ="Asus TouchPad" ; +if (drvdata->quirks &QUIRK_IS_MULTITOUCH ) { + drvdata->input->name ="Asus TouchPad" ; + }else { + drvdata->input->name ="Asus Keyboard" ; + }if (drvdata->quirks &QUIRK_IS_MULTITOUCH ) { ret =asus_start_multitouch (hdev);
@@ -315,7 +320,7 @@ static __u8 *asus_report_fixup(struct histatic const struct hid_device_id asus_devices[] = { {HID_I2C_DEVICE (USB_VENDOR_ID_ASUSTEK , -USB_DEVICE_ID_ASUSTEK_NOTEBOOK_KEYBOARD ),NOTEBOOK_QUIRKS }, +USB_DEVICE_ID_ASUSTEK_NOTEBOOK_KEYBOARD ),KEYBOARD_QUIRKS }, {HID_I2C_DEVICE (USB_VENDOR_ID_ASUSTEK ,USB_DEVICE_ID_ASUSTEK_TOUCHPAD ),TOUCHPAD_QUIRKS }, { }
Greg Kroah-Hartman
maintainerPATCH 96/152 HID: microsoft: Add Surface 4 type cover pro 4 not JP versions
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Daniel Keller <[email protected]>
[ Upstream commit 2ae3986b84e9d325bc92a1efbcf0c6b0f5016b35 ]
Adding support for not JP versions of the Microsoft Surface 4 Type Cover Pro
[[email protected]: The identical patch has been sent by Jeff Farthing, so I am
including his signoff as well]
--- drivers/hid/hid-core.c | 4 ++++ drivers/hid/hid-ids.h | 2 ++ drivers/hid/hid-microsoft.c | 4 ++++ drivers/hid/usbhid/hid-quirks.c | 2 ++ 4 files changed, 12 insertions(+)
drivers/hid/hid-core.c +4 -0
@@ -727,6 +727,8 @@ static void hid_scan_collection(struct h (hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_3 || hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_2 || hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP || + hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_4 || + hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_2 || hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP || hid->product ==USB_DEVICE_ID_MS_POWER_COVER ) && hid->group == HID_GROUP_MULTITOUCH)
@@ -1983,6 +1985,8 @@ static const struct hid_device_id hid_ha { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_2) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP) }, + { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4) }, + { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_2) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_7K) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_600) },
drivers/hid/hid-ids.h +2 -0
@@ -724,6 +724,8 @@#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_3 0x07dc#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_2 0x07e2#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP 0x07dd +#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_4 0x07e4 +#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_2 0x07e8#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP 0x07e9#define USB_DEVICE_ID_MS_POWER_COVER 0x07da
drivers/hid/hid-microsoft.c +4 -0
@@ -280,6 +280,10 @@ static const struct hid_device_id ms_dev .driver_data = MS_HIDINPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP), .driver_data = MS_HIDINPUT }, + { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4), + .driver_data = MS_HIDINPUT }, + { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_2), + .driver_data = MS_HIDINPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP), .driver_data = MS_HIDINPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_POWER_COVER),
drivers/hid/usbhid/hid-quirks.c +2 -0
@@ -104,6 +104,8 @@ static const struct hid_blacklist { { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_2, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP, HID_QUIRK_NO_INIT_REPORTS }, + { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4, HID_QUIRK_NO_INIT_REPORTS }, + { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_2, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_POWER_COVER, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MSI, USB_DEVICE_ID_MSI_GT683R_LED_PANEL, HID_QUIRK_NO_INIT_REPORTS },
A message that is not in the archive (sent off-list or not yet received): [email protected]
Greg Kroah-Hartman
maintainerRe: [PATCH 4.9 096/152] HID: microsoft: Add Surface 4 type cover pro 4 not JP versions
Quoted 5 lines · Daniel Keller
I think this commit is not necessary since commit
8fe89ef076fa1("HID:
multitouch: enable the Surface 3 Type Cover to report multitouch data") the TypeCover can be properly handled without the patch and you have the commit in your stable tree.
Quoted 7 lines
Or you adding the commit
66e5c5ffc7a5e4d36d136ce4fd8bdb4e92ecec7b"HID:
multitouch: enable Surface 4 Type Cover Pro (non-JP) to report multitouch data" from the 4.11 kernel which revert my patch.The commit
0a76ac80e84d0be0aba24ab60ac3bc14bc49bbc9"HID: multitouch: enable Surface 3 Type Cover Pro to report multitouch data" doing the same for the other TypeCover devices.
Ok, this is a mess, I've dropped these from the 4.9 and 4.10 stable queues, thanks.
Sasha, if you think these are still needed, can you please sort it out?
thanks,
greg k-h
Greg Kroah-Hartman
maintainerPATCH 97/152 HID: multitouch: enable the Surface 4 Type Cover Pro (JP) to report multitouch data
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Yuta Kobayashi <[email protected]>
[ Upstream commit 4fed0231994b27b3896bc63885ac66d02fff625b ]
Since commit 8fe89ef076fa1 ("HID: multitouch: enable the Surface 3 Type Cover to report multitouch data"), the TypeCover can be properly handled by hid-multitouch and don't require any special quirk in the kernel.
Remove the support of the Surface 4 Type Cover Pro (JP) from hid-microsoft so it can properly report multitouch from the touchpad.
--- drivers/hid/hid-core.c | 2 -- drivers/hid/hid-ids.h | 1 - drivers/hid/hid-microsoft.c | 2 -- drivers/hid/usbhid/hid-quirks.c | 1 - 4 files changed, 6 deletions(-)
drivers/hid/hid-core.c +0 -2
@@ -729,7 +729,6 @@ static void hid_scan_collection(struct h hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP || hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_4 || hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_2 || - hid->product ==USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP || hid->product == USB_DEVICE_ID_MS_POWER_COVER) && hid->group == HID_GROUP_MULTITOUCH) hid->group = HID_GROUP_GENERIC;
@@ -1987,7 +1986,6 @@ static const struct hid_device_id hid_ha { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_2) }, - { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_7K) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_600) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_3KV1) },
drivers/hid/hid-ids.h +0 -1
@@ -726,7 +726,6 @@#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP 0x07dd#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_4 0x07e4#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_2 0x07e8 -#define USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP 0x07e9#define USB_DEVICE_ID_MS_POWER_COVER 0x07da#define USB_VENDOR_ID_MOJO 0x8282
drivers/hid/hid-microsoft.c +0 -2
@@ -284,8 +284,6 @@ static const struct hid_device_id ms_dev .driver_data = MS_HIDINPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_2), .driver_data = MS_HIDINPUT }, - { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP), - .driver_data = MS_HIDINPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_POWER_COVER), .driver_data = MS_HIDINPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_COMFORT_KEYBOARD),
drivers/hid/usbhid/hid-quirks.c +0 -1
@@ -106,7 +106,6 @@ static const struct hid_blacklist { { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_3_JP, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_2, HID_QUIRK_NO_INIT_REPORTS }, - { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_TYPE_COVER_PRO_4_JP, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_POWER_COVER, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_MSI, USB_DEVICE_ID_MSI_GT683R_LED_PANEL, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_NEXIO, USB_DEVICE_ID_NEXIO_MULTITOUCH_PTI0750, HID_QUIRK_NO_INIT_REPORTS },
Greg Kroah-Hartman
maintainerPATCH 98/152 nvme: simplify stripe quirk
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Keith Busch <[email protected]>
[ Upstream commit e6282aef7b89a11d26e731060c4409b7aac278bf ]
Some OEMs believe they own the Identify Controller vendor specific region and will repurpose it with their own values. While not common, we can't rely on the PCI VID:DID to tell use how to decode the field we reserved for this as the stripe size so we need to do something else for the list of devices using this quirk.
The field was supposed to allow flexibility on the device's back-end striping, but it turned out that never materialized; the chunk is always the same as MDTS in the products subscribing to this quirk, so this patch removes the stripe_size field and sets the chunk to the max hw transfer size for the devices using this quirk.
--- drivers/nvme/host/core.c | 17 ++--------------- drivers/nvme/host/nvme.h | 1 - 2 files changed, 2 insertions(+), 16 deletions(-)
drivers/nvme/host/core.c +2 -15
@@ -1204,8 +1204,8 @@ static void nvme_set_queue_limits(structblk_queue_max_hw_sectors (q, ctrl->max_hw_sectors);blk_queue_max_segments (q,min_t (u32, max_segments,USHRT_MAX )); } -if (ctrl->stripe_size) -blk_queue_chunk_sectors (q, ctrl->stripe_size >>9 ); +if (ctrl->quirks &NVME_QUIRK_STRIPE_SIZE ) +blk_queue_chunk_sectors (q, ctrl->max_hw_sectors);blk_queue_virt_boundary (q, ctrl->page_size -1 );if (ctrl->vwc &NVME_CTRL_VWC_PRESENT ) vwc = true;
@@ -1261,19 +1261,6 @@ int nvme_init_identify(struct nvme_ctrl ctrl->max_hw_sectors =min_not_zero (ctrl->max_hw_sectors, max_hw_sectors); -if ((ctrl->quirks &NVME_QUIRK_STRIPE_SIZE ) && id->vs[3 ]) { -unsigned int max_hw_sectors; - - ctrl->stripe_size =1 << (id->vs[3 ] + page_shift); - max_hw_sectors = ctrl->stripe_size >> (page_shift -9 ); -if (ctrl->max_hw_sectors) { - ctrl->max_hw_sectors =min (max_hw_sectors, - ctrl->max_hw_sectors); - }else { - ctrl->max_hw_sectors = max_hw_sectors; - } - } -nvme_set_queue_limits (ctrl, ctrl->admin_q); ctrl->sgls =le32_to_cpu (id->sgls); ctrl->kas =le16_to_cpu (id->kas);
drivers/nvme/host/nvme.h +0 -1
@@ -121,7 +121,6 @@ struct nvme_ctrl {u32 page_size;u32 max_hw_sectors; -u32 stripe_size;u16 oncs;u16 vid;atomic_t abort_limit;
Greg Kroah-Hartman
maintainerPATCH 99/152 ACPI / sysfs: Provide quirk mechanism to prevent GPE flooding
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Lv Zheng <[email protected]>
[ Upstream commit 9c4aa1eecb48cfac18ed5e3aca9d9ae58fbafc11 ]
Sometimes, the users may require a quirk to be provided from ACPI subsystem core to prevent a GPE from flooding.
Normally, if a GPE cannot be dispatched, ACPICA core automatically prevents the GPE from firing. But there are cases the GPE is dispatched by _Lxx/_Exx provided via AML table, and OSPM is lacking of the knowledge to get _Lxx/_Exx correctly executed to handle the GPE, thus the GPE flooding may still occur.
The existing quirk mechanism can be enabled/disabled using the following commands to prevent such kind of GPE flooding during runtime:
# echo mask > /sys/firmware/acpi/interrupts/gpe00 # echo unmask > /sys/firmware/acpi/interrupts/gpe00 To avoid GPE flooding during boot, we need a boot stage mechanism.
This patch provides such a boot stage quirk mechanism to stop this kind of GPE flooding. This patch doesn't fix any feature gap but since the new feature gaps could be found in the future endlessly, and can disappear if the feature gaps are filled, providing a boot parameter rather than a DMI table should suffice.
--- Documentation/kernel-parameters.txt | 10 ++++++ drivers/acpi/internal.h | 1 drivers/acpi/scan.c | 1 drivers/acpi/sysfs.c | 56 ++++++++++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+)
Documentation/kernel-parameters.txt +10 -0
@@ -305,6 +305,16 @@ bytes respectively. Such letter suffixes use by PCI Format: <irq>,<irq>... + acpi_mask_gpe= [HW,ACPI] + Due to the existence of _Lxx/_Exx, some GPEs triggered + by unsupported hardware/firmware features can result in + GPE floodings that cannot be automatically disabled by + the GPE dispatcher. + This facility can be used to prevent such uncontrolled + GPE floodings. + Format: <int> + Support masking of GPEs numbered from 0x00 to 0x7f. + acpi_no_auto_serialize [HW,ACPI] Disable auto-serialization of AML methods AML control methods that contain the opcodes to create
drivers/acpi/internal.h +1 -0
@@ -37,6 +37,7 @@ void acpi_amba_init(void);static inline void acpi_amba_init (void ) {}#endif int acpi_sysfs_init (void ); +void acpi_gpe_apply_masked_gpes (void );void acpi_container_init (void );void acpi_memory_hotplug_init (void );#ifdef CONFIG_ACPI_HOTPLUG_IOAPIC
drivers/acpi/scan.c +1 -0
@@ -2044,6 +2044,7 @@ int __init acpi_scan_init(void) } } +acpi_gpe_apply_masked_gpes ();acpi_update_all_gpes ();acpi_ec_ecdt_start ();
drivers/acpi/sysfs.c +56 -0
62 lines not on this page · raw message
Greg Kroah-Hartman
maintainerPATCH 100/152 HID: usbhid: Add quirk for the Futaba TOSD-5711BB VFD
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Alex Wood <[email protected]>
[ Upstream commit f83f90cf7ba68deb09406ea9da80852a64c4db29 ]
The Futaba TOSD-5711BB VFD crashes when the initial HID report is requested, register the display in hid-ids and tell hid-quirks to not do the init.
--- drivers/hid/hid-ids.h | 3 +++ drivers/hid/usbhid/hid-quirks.c | 1 + 2 files changed, 4 insertions(+)
drivers/hid/hid-ids.h +3 -0
@@ -368,6 +368,9 @@#define USB_VENDOR_ID_FLATFROG 0x25b5#define USB_DEVICE_ID_MULTITOUCH_3200 0x0002 +#define USB_VENDOR_ID_FUTABA 0x0547 +#define USB_DEVICE_ID_LED_DISPLAY 0x7000 +#define USB_VENDOR_ID_ESSENTIAL_REALITY 0x0d7f#define USB_DEVICE_ID_ESSENTIAL_REALITY_P5 0x0100
drivers/hid/usbhid/hid-quirks.c +1 -0
@@ -89,6 +89,7 @@ static const struct hid_blacklist { { USB_VENDOR_ID_ELO, USB_DEVICE_ID_ELO_TS2700, HID_QUIRK_NOGET }, { USB_VENDOR_ID_FORMOSA, USB_DEVICE_ID_FORMOSA_IR_RECEIVER, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_FREESCALE, USB_DEVICE_ID_FREESCALE_MX28, HID_QUIRK_NOGET }, + { USB_VENDOR_ID_FUTABA, USB_DEVICE_ID_LED_DISPLAY, HID_QUIRK_NO_INIT_REPORTS }, { USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A, HID_QUIRK_ALWAYS_POLL }, { USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A, HID_QUIRK_ALWAYS_POLL }, { USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE, HID_QUIRK_ALWAYS_POLL },
Greg Kroah-Hartman
maintainerPATCH 101/152 HID: usbhid: Add quirk for Mayflash/Dragonrise DolphinBar.
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Marcel Hasler <[email protected]>
[ Upstream commit 8aa2cc7e747881d1fd52db28261b201d4e3e5565 ]
The DolphinBar by Mayflash (identified as Dragonrise) needs HID_QUIRK_MULTI_INPUT to split it up into four input devices. Without this quirk the adapter is falsely recognized as a tablet. See also bug 115841
(https://bugzilla.kernel.org/show_bug.cgi?id=115841).
--- drivers/hid/hid-ids.h | 1 + drivers/hid/usbhid/hid-quirks.c | 1 + 2 files changed, 2 insertions(+)
drivers/hid/hid-ids.h +1 -0
@@ -322,6 +322,7 @@#define USB_VENDOR_ID_DRAGONRISE 0x0079#define USB_DEVICE_ID_DRAGONRISE_WIIU 0x1800#define USB_DEVICE_ID_DRAGONRISE_PS3 0x1801 +#define USB_DEVICE_ID_DRAGONRISE_DOLPHINBAR 0x1803#define USB_DEVICE_ID_DRAGONRISE_GAMECUBE 0x1843#define USB_VENDOR_ID_DWAV 0x0eef
drivers/hid/usbhid/hid-quirks.c +1 -0
@@ -84,6 +84,7 @@ static const struct hid_blacklist { { USB_VENDOR_ID_DMI, USB_DEVICE_ID_DMI_ENC, HID_QUIRK_NOGET }, { USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_WIIU, HID_QUIRK_MULTI_INPUT }, { USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_PS3, HID_QUIRK_MULTI_INPUT }, + { USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_DOLPHINBAR, HID_QUIRK_MULTI_INPUT }, { USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE, HID_QUIRK_MULTI_INPUT }, { USB_VENDOR_ID_ELAN, HID_ANY_ID, HID_QUIRK_ALWAYS_POLL }, { USB_VENDOR_ID_ELO, USB_DEVICE_ID_ELO_TS2700, HID_QUIRK_NOGET },
Greg Kroah-Hartman
maintainerPATCH 102/152 drm/edid: constify edid quirk list
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jani Nikula <[email protected]>
[ Upstream commit 23c4cfbdab494568600ae6073a2bf02be4b10f4e ]
No reason not to be const.
--- drivers/gpu/drm/drm_edid.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/gpu/drm/drm_edid.c +3 -3
@@ -90,7 +90,7 @@ struct detailed_mode_closure {#define LEVEL_GTF2 2#define LEVEL_CVT 3 -static struct edid_quirk { +static const struct edid_quirk { char vendor[4]; int product_id; u32 quirks;
@@ -1449,7 +1449,7 @@ EXPORT_SYMBOL(drm_edid_duplicate);* * Returns true if @vendor is in @edid, false otherwise */ -static bool edid_vendor (struct edid *edid,char *vendor) +static bool edid_vendor (struct edid *edid,const char *vendor) {char edid_vendor[3 ];
@@ -1469,7 +1469,7 @@ static bool edid_vendor(struct edid *edi*/ static u32 edid_get_quirks (struct edid *edid) { -struct edid_quirk *quirk; +const struct edid_quirk *quirk;int i;for (i =0 ; i <ARRAY_SIZE (edid_quirk_list); i++) {
Greg Kroah-Hartman
maintainerPATCH 103/152 drm/i915: fix INTEL_BDW_IDS definition
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Paulo Zanoni <[email protected]>
[ Upstream commit 7fbd995ce4241e98d30859405504c3fb279c4ccb ]
Remove duplicated IDs from the list. Currently, this definition is only used by early-quirks.c. From my understanding of the code, having duplicated IDs shouldn't be causing any bugs.
--- include/drm/i915_pciids.h | 2 -- 1 file changed, 2 deletions(-)
include/drm/i915_pciids.h +0 -2
@@ -240,8 +240,6 @@INTEL_BDW_GT12_IDS (info), \INTEL_BDW_GT3_IDS (info), \INTEL_BDW_RSVDM_IDS (info), \ -INTEL_BDW_GT12_IDS (info ), \ -INTEL_BDW_GT3_IDS (info ), \ INTEL_BDW_RSVDD_IDS(info)#define INTEL_CHV_IDS (info) \
Greg Kroah-Hartman
maintainerPATCH 104/152 drm/i915: more .is_mobile cleanups for BDW
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Paulo Zanoni <[email protected]>
[ Upstream commit 0784bc624ae9be4269f8129572ee164ca680ca7c ]
Commit 8d9c20e1d1e3 ("drm/i915: Remove .is_mobile field from platform struct") removed mobile vs desktop differences for HSW+, but forgot the Broadwell reserved IDs, so do it now.
It's interesting to notice that these IDs are used by early-quirks.c but are *not* used by i915_pci.c.
--- include/drm/i915_pciids.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)
include/drm/i915_pciids.h +3 -6
@@ -226,21 +226,18 @@INTEL_VGA_DEVICE (0x162A , info),/* Server */ \ INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ -#define INTEL_BDW_RSVDM_IDS (info) \ +#define INTEL_BDW_RSVD_IDS (info) \ INTEL_VGA_DEVICE(0x1632, info),/* ULT */ \INTEL_VGA_DEVICE (0x1636 , info),/* ULT */ \INTEL_VGA_DEVICE (0x163B , info),/* Iris */ \ - INTEL_VGA_DEVICE(0x163E, info) /* ULX */ - -#define INTEL_BDW_RSVDD_IDS (info) \ +INTEL_VGA_DEVICE (0x163E , info),/* ULX */ \INTEL_VGA_DEVICE (0x163A , info),/* Server */ \ INTEL_VGA_DEVICE(0x163D, info) /* Workstation */#define INTEL_BDW_IDS (info) \ INTEL_BDW_GT12_IDS(info), \ INTEL_BDW_GT3_IDS(info), \ - INTEL_BDW_RSVDM_IDS(info), \ - INTEL_BDW_RSVDD_IDS(info) + INTEL_BDW_RSVD_IDS(info)#define INTEL_CHV_IDS (info) \ INTEL_VGA_DEVICE(0x22b0, info), \
Greg Kroah-Hartman
maintainerPATCH 105/152 drm/i915: actually drive the BDW reserved IDs
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Paulo Zanoni <[email protected]>
[ Upstream commit 98b2f01c8dfc8922a2af1fe82a1c40cac4911634 ]
Back in 2014, commit fb7023e0e248 ("drm/i915: BDW: Adding Reserved PCI IDs.") added the reserved PCI IDs in order to try to make sure we had working drivers in case we ever released products using these IDs (since we had instances of this type of problem in the past). The problem is that the patch only touched the macros used by early-quirks.c and by the user space components that rely on i915_pciids.h, it didn't touch the macros used by i915_pci.c. So we correctly handled the stolen memory for these theoretical IDs, but we didn't actually drive the devices from i915.ko.
So this patch fixes the original commit by actually making i915.ko drive these IDs, which was the goal. There's no information on what would be the GT count on these IDs, so we just go with the safer intel_broadwell_info, at the risk of ignoring a possibly inexistent BSD2_RING.
I did some checking, and it seems that these IDs are driven by intel-gpu-tools, xf86-video-intel and libdrm (since they contain old copies of i915_pciids.h), but they are not checked by mesa.
The alternative to this patch would be to just assume we're actually never going to use these IDs, and then remove them from our ID lists and make sure our user space components sync the latest i915_pciids.h copy. I'm fine with either approaches, as long as we make sure that every component tries to drive the same list of PCI IDs.
--- drivers/gpu/drm/i915/i915_pci.c | 1 + 1 file changed, 1 insertion(+)
drivers/gpu/drm/i915/i915_pci.c +1 -0
@@ -417,6 +417,7 @@ static const struct pci_device_id pciidlINTEL_VLV_IDS (&intel_valleyview_info),INTEL_BDW_GT12_IDS (&intel_broadwell_info),INTEL_BDW_GT3_IDS (&intel_broadwell_gt3_info), +INTEL_BDW_RSVD_IDS (&intel_broadwell_info),INTEL_CHV_IDS (&intel_cherryview_info),INTEL_SKL_GT1_IDS (&intel_skylake_info), INTEL_SKL_GT2_IDS(&intel_skylake_info),
Greg Kroah-Hartman
maintainerPATCH 106/152 ASoC: Intel: bytcr_rt5640: quirks for Insyde devices
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: youling257 <[email protected]>
[ Upstream commit 571800487837263e914ef68681e4ad6a57d49c7f ]
There are literally dozens of Insyde devices with a different name but with the same audio routing. Use a generic quirk to match on vendor name only to avoid recurring edits of the same thing.
--- sound/soc/intel/boards/bytcr_rt5640.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
sound/soc/intel/boards/bytcr_rt5640.c +10 -0
@@ -387,6 +387,16 @@ static const struct dmi_system_id byt_rt BYT_RT5640_SSP0_AIF1), }, + { + .callback = byt_rt5640_quirk_cb, + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Insyde"), + }, + .driver_data = (unsigned long *)(BYT_RT5640_IN3_MAP | + BYT_RT5640_MCLK_EN | + BYT_RT5640_SSP0_AIF1), + + }, {} };
Greg Kroah-Hartman
maintainerPATCH 107/152 scsi: ufs: introduce a new ufshcd_statea UFSHCD_STATE_EH_SCHEDULED
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Zang Leigang <[email protected]>
[ Upstream commit 141f81651037ea109188a6bafdc5c9a318bd5a46 ]
Add a new ufshcd_state, indicats that an err handler may get to run immediately. Use UFSHCD_STATE_ERROR here looks not literaly correct.
--- drivers/scsi/ufs/ufshcd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/scsi/ufs/ufshcd.c +3 -1
@@ -123,6 +123,7 @@ enum {UFSHCD_STATE_RESET ,UFSHCD_STATE_ERROR ,UFSHCD_STATE_OPERATIONAL , + UFSHCD_STATE_EH_SCHEDULED, };/* UFSHCD error handling flags */
@@ -1439,6 +1440,7 @@ static int ufshcd_queuecommand(struct Scswitch (hba->ufshcd_state) {case UFSHCD_STATE_OPERATIONAL :break ; +case UFSHCD_STATE_EH_SCHEDULED :case UFSHCD_STATE_RESET : err =SCSI_MLQUEUE_HOST_BUSY ; goto out_unlock;
@@ -4196,7 +4198,7 @@ static void ufshcd_check_errors(struct u/* block commands from scsi mid-layer */ scsi_block_requests (hba->host); - hba->ufshcd_state =UFSHCD_STATE_ERROR ; + hba->ufshcd_state =UFSHCD_STATE_EH_SCHEDULED ;schedule_work (&hba->eh_work); } }
Greg Kroah-Hartman
maintainerPATCH 108/152 scsi: ufs: issue link starup 2 times if device isnt active
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: "[email protected]" <[email protected]>
[ Upstream commit 7caf489b99a42a9017ef3d733912aea8794677e7 ]
If we issue the link startup to the device while its UniPro state is LinkDown (and device state is sleep/power-down) then link startup will not move the device state to Active. Device will only move to active state if the link starup is issued when its UniPro state is LinkUp. So in this case, we would have to issue the link startup 2 times to make sure that device moves to active state.
--- drivers/scsi/ufs/ufshcd.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-)
drivers/scsi/ufs/ufshcd.c +20 -3
@@ -3130,7 +3130,16 @@ static int ufshcd_link_startup(struct uf {int ret;int retries =DME_LINKSTARTUP_RETRIES ; +bool link_startup_again = false; +/* +* If UFS device isn't active then we will have to issue link startup +* 2 times to make sure the device state move to active. +*/ +if (!ufshcd_is_ufs_dev_active (hba)) + link_startup_again = true; + +link_startup: do { ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
@@ -3156,6 +3165,12 @@ static int ufshcd_link_startup(struct uf/* failed to get the link up... retire */ goto out; +if (link_startup_again) { + link_startup_again = false; + retries =DME_LINKSTARTUP_RETRIES ; + goto link_startup; + } +if (hba->quirks &UFSHCD_QUIRK_BROKEN_LCC ) { ret =ufshcd_disable_device_tx_lcc (hba);if (ret)
@@ -6630,10 +6645,12 @@ int ufshcd_init(struct ufs_hba *hba, voipm_runtime_get_sync (dev);/* -* The device-initialize-sequence hasn't been invoked yet. -* Set the device to power-off state +* We are assuming that device wasn't put in sleep/power-down +* state exclusively during the boot stage before kernel. +* This assumption helps avoid doing link startup twice during +* ufshcd_probe_hba(). */ -ufshcd_set_ufs_dev_poweroff (hba); +ufshcd_set_ufs_dev_active (hba);async_schedule (ufshcd_async_scan, hba);
Greg Kroah-Hartman
maintainerPATCH 109/152 ARM: OMAP2+: Fix init for multiple quirks for the same SoC
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tony Lindgren <[email protected]>
[ Upstream commit 6e613ebf4405fc09e2a8c16ed193b47f80a3cbed ]
It's possible that there are multiple quirks that need to be initialized for the same SoC. Fix the issue by not returning on the first match.
--- arch/arm/mach-omap2/pdata-quirks.c | 1 - 1 file changed, 1 deletion(-)
arch/arm/mach-omap2/pdata-quirks.c +0 -1
@@ -600,7 +600,6 @@ static void pdata_quirks_check(struct pdif (of_machine_is_compatible (quirks->compatible)) {if (quirks->fn) quirks->fn (); -break ; } quirks++; }
Greg Kroah-Hartman
maintainerPATCH 110/152 usb: chipidea: msm: Rely on core to override AHBBURST
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Stephen Boyd <[email protected]>
[ Upstream commit dd3749099cfa2c80039193c438b90f3160eaf7f9 ]
The core framework already handles setting this parameter with a platform quirk. Add the appropriate flag so that we always set AHBBURST to 0. Technically DT should be doing this, but we always do it for msm chipidea devices so setting the flag in the driver works just as well. If the burst needs to be anything besides 0, we expect the 'ahb-burst-config' dts property to be present.
--- drivers/usb/chipidea/ci_hdrc_msm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/usb/chipidea/ci_hdrc_msm.c +2 -2
@@ -24,7 +24,6 @@ static void ci_hdrc_msm_notify_event(strswitch (event) {case CI_HDRC_CONTROLLER_RESET_EVENT :dev_dbg (dev,"CI_HDRC_CONTROLLER_RESET_EVENT received\n" ); -writel (0 ,USB_AHBBURST );/* use AHB transactor, allow posted data writes */ writel (0x8 ,USB_AHBMODE );usb_phy_init (ci->usb_phy);
@@ -47,7 +46,8 @@ static struct ci_hdrc_platform_data ci_h .name = "ci_hdrc_msm", .capoffset = DEF_CAPOFFSET, .flags =CI_HDRC_REGS_SHARED | - CI_HDRC_DISABLE_STREAMING, +CI_HDRC_DISABLE_STREAMING | + CI_HDRC_OVERRIDE_AHB_BURST, .notify_event = ci_hdrc_msm_notify_event, };
Greg Kroah-Hartman
maintainerPATCH 111/152 serial: 8250_omap: Add OMAP_DMA_TX_KICK quirk for AM437x
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Vignesh R <[email protected]>
[ Upstream commit b6ffcf21082300519bc4f9c3d24f61207cc9eae4 ]
UART uses as EDMA as dma engine on AM437x SoC and therefore, requires OMAP_DMA_TX_KICK quirk just like AM33xx. So, enable OMAP_DMA_TX_KICK quirk for AM437x platform as well. While at that, drop use of of_machine_is_compatible() and instead pass quirks via device data.
--- drivers/tty/serial/8250/8250_omap.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)
drivers/tty/serial/8250/8250_omap.c +3 -6
@@ -1075,15 +1075,15 @@ static int omap8250_no_handle_irq(struct }static const u8 am3352_habit =OMAP_DMA_TX_KICK |UART_ERRATA_CLOCK_DISABLE ; -static const u8 am4372_habit =UART_ERRATA_CLOCK_DISABLE ; +static const u8 dra742_habit =UART_ERRATA_CLOCK_DISABLE ;static const struct of_device_id omap8250_dt_ids[] = { { .compatible ="ti,omap2-uart" }, { .compatible ="ti,omap3-uart" }, { .compatible ="ti,omap4-uart" }, { .compatible ="ti,am3352-uart" , .data = &am3352_habit, }, - { .compatible ="ti,am4372-uart" , .data = &am4372_habit, }, - { .compatible ="ti,dra742-uart" , .data = &am4372_habit, }, + { .compatible ="ti,am4372-uart" , .data = &am3352_habit, }, + { .compatible ="ti,dra742-uart" , .data = &dra742_habit, }, {}, };MODULE_DEVICE_TABLE (of, omap8250_dt_ids);
@@ -1218,9 +1218,6 @@ static int omap8250_probe(struct platfor priv->omap8250_dma.rx_size =RX_TRIGGER ; priv->omap8250_dma.rxconf.src_maxburst =RX_TRIGGER ; priv->omap8250_dma.txconf.dst_maxburst =TX_TRIGGER ; - -if (of_machine_is_compatible ("ti,am33xx" )) - priv->habit |=OMAP_DMA_TX_KICK ;/* * pause is currently not supported atleast on omap-sdma * and edma on most earlier kernels.
Greg Kroah-Hartman
maintainerPATCH 112/152 Input: gpio_keys - add support for GPIO descriptors
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Geert Uytterhoeven <[email protected]>
[ Upstream commit 5feeca3c1e39c01f9ef5abc94dea94021ccf94fc ]
GPIO descriptors are the preferred way over legacy GPIO numbers nowadays. Convert the driver to use GPIO descriptors internally but still allow passing legacy GPIO numbers from platform data to support existing platforms.
Based on commits 633a21d80b4a2cd6 ("input: gpio_keys_polled: Add support for GPIO descriptors") and 1ae5ddb6f8837558 ("Input: gpio_keys_polled - request GPIO pin as input.").
--- drivers/input/keyboard/gpio_keys.c | 37 ++++++++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 11 deletions(-)
drivers/input/keyboard/gpio_keys.c +26 -11
@@ -26,6 +26,7 @@#include <linux/gpio_keys.h> #include <linux/workqueue.h> #include <linux/gpio.h> +#include <linux/gpio/consumer.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/of_gpio.h>
@@ -35,6 +36,7 @@struct gpio_button_data {const struct gpio_keys_button *button;struct input_dev *input; +struct gpio_desc *gpiod;struct timer_list release_timer;unsigned int release_delay;/* in msecs, for IRQ-only buttons */
@@ -140,7 +142,7 @@ static void gpio_keys_disable_button(str*/ disable_irq (bdata->irq); -if (gpio_is_valid (bdata->button->gpio)) +if (bdata->gpiod)cancel_delayed_work_sync (&bdata->work);else del_timer_sync (&bdata->release_timer);
@@ -358,19 +360,20 @@ static void gpio_keys_gpio_report_event(const struct gpio_keys_button *button = bdata->button;struct input_dev *input = bdata->input;unsigned int type = button->type ?:EV_KEY ; -int state =gpio_get_value_cansleep (button->gpio); +int state; + state =gpiod_get_value_cansleep (bdata->gpiod);if (state <0 ) { -dev_err (input->dev.parent,"failed to get gpio state\n" ); +dev_err (input->dev.parent, +"failed to get gpio state: %d\n" , state);return ; } - state = (state ?1 :0 ) ^ button->active_low;if (type ==EV_ABS ) {if (state)input_event (input, type, button->code, button->value); }else { -input_event (input, type, button->code, !!state); +input_event (input, type, button->code, state); }input_sync (input); }
@@ -456,7 +459,7 @@ static void gpio_keys_quiesce_key(void * {struct gpio_button_data *bdata = data; -if (gpio_is_valid (bdata->button->gpio)) +if (bdata->gpiod)cancel_delayed_work_sync (&bdata->work);else del_timer_sync (&bdata->release_timer);
@@ -478,18 +481,30 @@ static int gpio_keys_setup_key(struct pl bdata->button = button;spin_lock_init (&bdata->lock); +/* +* Legacy GPIO number, so request the GPIO here and +* convert it to descriptor. +*/ if (gpio_is_valid (button->gpio)) { +unsigned flags =GPIOF_IN ; + +if (button->active_low) + flags |=GPIOF_ACTIVE_LOW ; - error =devm_gpio_request_one (&pdev->dev, button->gpio, -GPIOF_IN , desc); + error =devm_gpio_request_one (&pdev->dev, button->gpio, flags, + desc);if (error <0 ) {dev_err (dev,"Failed to request GPIO %d, error %d\n" , button->gpio, error);return error; } + bdata->gpiod =gpio_to_desc (button->gpio); +if (!bdata->gpiod) +return -EINVAL ; +if (button->debounce_interval) { - error =gpio_set_debounce (button->gpio, + error =gpiod_set_debounce (bdata->gpiod, button->debounce_interval *1000 );/* use timer if gpiolib doesn't provide debounce */ if (error <0 )
@@ -500,7 +515,7 @@ static int gpio_keys_setup_key(struct plif (button->irq) { bdata->irq = button->irq; }else { - irq =gpio_to_irq (button->gpio); + irq =gpiod_to_irq (bdata->gpiod);if (irq <0 ) { error = irq; dev_err(dev,
@@ -575,7 +590,7 @@ static void gpio_keys_report_state(strucfor (i =0 ; i < ddata->pdata->nbuttons; i++) {struct gpio_button_data *bdata = &ddata->data[i]; -if (gpio_is_valid (bdata->button->gpio)) +if (bdata->gpiod)gpio_keys_gpio_report_event (bdata); }input_sync (input);
Re: [PATCH 4.9 112/152] Input: gpio_keys - add support for GPIO descriptors
Quoted 1 line · Greg Kroah-Hartman
4.9-stable review patch. If anyone has any objections, please let me know.
Confused why it needs to be in stable as there should be no chnage in behavior. Is it because there are other patches depending on this one?
Quoted 141 lines
------------------
From: Geert Uytterhoeven <[email protected]>
[ Upstream commit
5feeca3c1e39c01f9ef5abc94dea94021ccf94fc]GPIO descriptors are the preferred way over legacy GPIO numbers nowadays. Convert the driver to use GPIO descriptors internally but still allow passing legacy GPIO numbers from platform data to support existing platforms.
Based on commits
633a21d80b4a2cd6("input:gpio_keys_polled: Add support for GPIO descriptors") and1ae5ddb6f8837558("Input:gpio_keys_polled- request GPIO pin as input.").Signed-off-by Geert Uytterhoeven <[email protected]>Reviewed-by Linus Walleij <[email protected]>Tested-by Mika Westerberg <[email protected]>Signed-off-by Dmitry Torokhov <[email protected]>Signed-off-by Sasha Levin <[email protected]>Signed-off-by Greg Kroah-Hartman <[email protected]>--- drivers/input/keyboard/gpio_keys.c | 37 ++++++++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 11 deletions(-)drivers/input/keyboard/gpio_keys.c +26
-11@@ -26,6 +26,7 @@#include <linux/gpio_keys.h> #include <linux/workqueue.h> #include <linux/gpio.h> +#include <linux/gpio/consumer.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/of_gpio.h> @@ -35,6 +36,7 @@struct gpio_button_data {const struct gpio_keys_button *button;struct input_dev *input; +struct gpio_desc *gpiod;struct timer_list release_timer;unsigned int release_delay;/* in msecs, for IRQ-only buttons */ @@ -140,7 +142,7 @@ static void gpio_keys_disable_button(str*/ disable_irq (bdata->irq); -if (gpio_is_valid (bdata->button->gpio)) +if (bdata->gpiod)cancel_delayed_work_sync (&bdata->work);else del_timer_sync (&bdata->release_timer);@@ -358,19 +360,20 @@ static void gpio_keys_gpio_report_event(const struct gpio_keys_button *button = bdata->button;struct input_dev *input = bdata->input;unsigned int type = button->type ?:EV_KEY ; -int state =gpio_get_value_cansleep (button->gpio); +int state; + state =gpiod_get_value_cansleep (bdata->gpiod);if (state <0 ) { -dev_err (input->dev.parent,"failed to get gpio state\n" ); +dev_err (input->dev.parent, +"failed to get gpio state: %d\n" , state);return ; } - state = (state ?1 :0 ) ^ button->active_low;if (type ==EV_ABS ) {if (state)input_event (input, type, button->code, button->value); }else { -input_event (input, type, button->code, !!state); +input_event (input, type, button->code, state); }input_sync (input); }@@ -456,7 +459,7 @@ static void gpio_keys_quiesce_key(void * {struct gpio_button_data *bdata = data; -if (gpio_is_valid (bdata->button->gpio)) +if (bdata->gpiod)cancel_delayed_work_sync (&bdata->work);else del_timer_sync (&bdata->release_timer);@@ -478,18 +481,30 @@ static int gpio_keys_setup_key(struct pl bdata->button = button;spin_lock_init (&bdata->lock); +/* +* Legacy GPIO number, so request the GPIO here and +* convert it to descriptor. +*/ if (gpio_is_valid (button->gpio)) { +unsigned flags =GPIOF_IN ; + +if (button->active_low) + flags |=GPIOF_ACTIVE_LOW ; - error =devm_gpio_request_one (&pdev->dev, button->gpio, -GPIOF_IN , desc); + error =devm_gpio_request_one (&pdev->dev, button->gpio, flags, + desc);if (error <0 ) {dev_err (dev,"Failed to request GPIO %d, error %d\n" , button->gpio, error);return error; } + bdata->gpiod =gpio_to_desc (button->gpio); +if (!bdata->gpiod) +return -EINVAL ; +if (button->debounce_interval) { - error =gpio_set_debounce (button->gpio, + error =gpiod_set_debounce (bdata->gpiod, button->debounce_interval *1000 );/* use timer if gpiolib doesn't provide debounce */ if (error <0 )@@ -500,7 +515,7 @@ static int gpio_keys_setup_key(struct plif (button->irq) { bdata->irq = button->irq; }else { - irq =gpio_to_irq (button->gpio); + irq =gpiod_to_irq (bdata->gpiod);if (irq <0 ) { error = irq; dev_err(dev,@@ -575,7 +590,7 @@ static void gpio_keys_report_state(strucfor (i =0 ; i < ddata->pdata->nbuttons; i++) {struct gpio_button_data *bdata = &ddata->data[i]; -if (gpio_is_valid (bdata->button->gpio)) +if (bdata->gpiod)gpio_keys_gpio_report_event (bdata); }input_sync (input);
Signature · 1 line
Dmitry
Greg Kroah-Hartman
maintainerPATCH 113/152 amd-xgbe: Prepare for working with more than one type of phy
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: "Lendacky, Thomas" <[email protected]>
[ Upstream commit e57f7a3feaef0e9e196801f1625bca1337405421 ]
Prepare the code to be able to work with more than one type of phy by adding additional callable functions into the phy interface and removing phy specific settings/functions from non-phy related files.
--- drivers/net/ethernet/amd/xgbe/Makefile | 3 drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 58 - drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 6 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c | 19 drivers/net/ethernet/amd/xgbe/xgbe-main.c | 214 ++----- drivers/net/ethernet/amd/xgbe/xgbe-mdio.c | 543 +++++------------ drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c | 821 +++++++++++++++++++++++++++ drivers/net/ethernet/amd/xgbe/xgbe.h | 130 ++-- 8 files changed, 1137 insertions(+), 657 deletions(-) create mode 100644 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c
drivers/net/ethernet/amd/xgbe/Makefile +2 -1
@@ -2,7 +2,8 @@ obj-$(CONFIG_AMD_XGBE) += amd-xgbe.o amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \ xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \ - xgbe-ptp.o + xgbe-ptp.o \ + xgbe-phy-v1.o amd-xgbe-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o amd-xgbe-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o
drivers/net/ethernet/amd/xgbe/xgbe-dev.c +19 -39
79 lines not on this page · raw message
drivers/net/ethernet/amd/xgbe/xgbe-drv.c +3 -3
@@ -783,7 +783,7 @@ static void xgbe_free_rx_data(struct xgbDBGPR ("<--xgbe_free_rx_data\n" ); } -static int xgbe_phy_init (struct xgbe_prv_data *pdata) +static int xgbe_phy_reset (struct xgbe_prv_data *pdata) { pdata->phy_link =-1 ; pdata->phy_speed =SPEED_UNKNOWN ;
@@ -1297,8 +1297,8 @@ static int xgbe_open(struct net_device *DBGPR ("-->xgbe_open\n" ); -/* Initialize the phy */ - ret =xgbe_phy_init (pdata); +/* Reset the phy settings */ + ret =xgbe_phy_reset (pdata);if (ret)return ret;
drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c +1 -18
@@ -316,24 +316,7 @@ static int xgbe_set_settings(struct net_ }if (cmd->autoneg ==AUTONEG_DISABLE ) { -switch (speed) { -case SPEED_10000 : -break ; -case SPEED_2500 : -if (pdata->speed_set !=XGBE_SPEEDSET_2500_10000 ) { -netdev_err (netdev,"unsupported speed %u\n" , - speed); -return -EINVAL ; - } -break ; -case SPEED_1000 : -if (pdata->speed_set !=XGBE_SPEEDSET_1000_10000 ) { -netdev_err (netdev,"unsupported speed %u\n" , - speed); -return -EINVAL ; - } -break ; -default : +if (!pdata->phy_if.phy_valid_speed (pdata, speed)) {netdev_err (netdev,"unsupported speed %u\n" , speed);return -EINVAL ; }
drivers/net/ethernet/amd/xgbe/xgbe-main.c +62 -152
319 lines not on this page · raw message
drivers/net/ethernet/amd/xgbe/xgbe-mdio.c +162 -381
759 lines not on this page · raw message
drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c new file +821 -0
821 lines not on this page · raw message
drivers/net/ethernet/amd/xgbe/xgbe.h +67 -63
202 lines not on this page · raw message
Greg Kroah-Hartman
maintainerPATCH 114/152 ARM: davinci: PM: support da8xx DT platforms
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Kevin Hilman <[email protected]>
[ Upstream commit 7e431af8fa0b9ed9d74378c99514856211cb9db8 ]
Add PM support for DA850 device-tree boot.
--- arch/arm/mach-davinci/da8xx-dt.c | 1 + 1 file changed, 1 insertion(+)
arch/arm/mach-davinci/da8xx-dt.c +1 -0
@@ -46,6 +46,7 @@ static struct of_dev_auxdata da850_auxdastatic void __init da850_init_machine (void ) {of_platform_default_populate (NULL , da850_auxdata_lookup,NULL ); +davinci_pm_init (); }static const char *const da850_boards_compat[]__initconst = {
Greg Kroah-Hartman
maintainerPATCH 115/152 ARM: davinci: add skeleton for pdata-quirks
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Kevin Hilman <[email protected]>
[ Upstream commit 9c9b1bc25291e275b04f758f2549c81e092954f5 ]
Add skeleton pdata-quirks for davinci.
[[email protected]: move changes to build pdata-quirks.c and call
to pdata_quirks_init() to this patch]
--- arch/arm/mach-davinci/Makefile | 2 - arch/arm/mach-davinci/da8xx-dt.c | 1 arch/arm/mach-davinci/include/mach/common.h | 2 + arch/arm/mach-davinci/pdata-quirks.c | 39 ++++++++++++++++++++++++++++ 4 files changed, 43 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-davinci/pdata-quirks.c
arch/arm/mach-davinci/Makefile +1 -1
@@ -21,7 +21,7 @@ obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o # Board specific -obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o +obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
arch/arm/mach-davinci/da8xx-dt.c +1 -0
@@ -47,6 +47,7 @@ static void __init da850_init_machine(vo {of_platform_default_populate (NULL , da850_auxdata_lookup,NULL );davinci_pm_init (); +pdata_quirks_init (); }static const char *const da850_boards_compat[]__initconst = {
arch/arm/mach-davinci/include/mach/common.h +2 -0
@@ -102,6 +102,8 @@ int davinci_pm_init(void);static inline int davinci_pm_init (void ) {return 0 ; }#endif +void __init pdata_quirks_init (void ); +#define SRAM_SIZE SZ_128K#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
arch/arm/mach-davinci/pdata-quirks.c new file +39 -0
@@ -0,0 +1,39 @@ +/* +* Legacy platform_data quirks +* +* Copyright (C) 2016 BayLibre, Inc +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ +#include <linux/kernel.h> +#include <linux/of_platform.h> + +#include <mach/common.h> + +struct pdata_init { +const char *compatible; +void (*fn)(void ); +}; + +static void pdata_quirks_check (struct pdata_init *quirks) +{ +while (quirks->compatible) { +if (of_machine_is_compatible (quirks->compatible)) { +if (quirks->fn) + quirks->fn (); +break ; + } + quirks++; + } +} + +static struct pdata_init pdata_quirks[]__initdata = { + {/* sentinel */ }, +}; + +void __init pdata_quirks_init (void ) +{ +pdata_quirks_check (pdata_quirks); +}
Re: [PATCH 4.9 115/152] ARM: davinci: add skeleton for pdata-quirks
Quoted 8 lines · Greg Kroah-Hartman
4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Kevin Hilman <[email protected]>
[ Upstream commit
9c9b1bc25291e275b04f758f2549c81e092954f5]
Quoted 8 lines
Add skeleton pdata-quirks for davinci.
Signed-off-by Kevin Hilman <[email protected]>[[email protected]: move changes to build
pdata-quirks.cand call
topdata_quirks_init()to this patch]Signed-off-by Sekhar Nori <[email protected]>Signed-off-by Sasha Levin <[email protected]>Signed-off-by Greg Kroah-Hartman <[email protected]>
This does not add any useful feature or bug fix on its own. I don't think it should be backported to stable.
Thanks,
Sekhar
Greg Kroah-Hartman
maintainerRe: [PATCH 4.9 115/152] ARM: davinci: add skeleton for pdata-quirks
Quoted 18 lines · Sekhar Nori
Quoted 8 lines · Greg Kroah-Hartman
4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Kevin Hilman <[email protected]>
[ Upstream commit
9c9b1bc25291e275b04f758f2549c81e092954f5]Quoted 8 lines
Add skeleton pdata-quirks for davinci.
Signed-off-by Kevin Hilman <[email protected]>[[email protected]: move changes to build
pdata-quirks.cand call
topdata_quirks_init()to this patch]Signed-off-by Sekhar Nori <[email protected]>Signed-off-by Sasha Levin <[email protected]>Signed-off-by Greg Kroah-Hartman <[email protected]>
Quoted 2 lines
This does not add any useful feature or bug fix on its own. I don't think it should be backported to stable.
Yeah, that's really odd. It doesn't seem to do anything in Linus's tree either...
I'll drop it from the stable trees queues now, thanks.
greg k-h
Re: [PATCH 4.9 115/152] ARM: davinci: add skeleton for pdata-quirks
Quoted 19 lines · Greg Kroah-Hartman
Quoted 18 lines · Sekhar Nori
Quoted 16 lines · Greg Kroah-Hartman
4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Kevin Hilman <[email protected]>
[ Upstream commit
9c9b1bc25291e275b04f758f2549c81e092954f5]Add skeleton pdata-quirks for davinci.
Signed-off-by Kevin Hilman <[email protected]>[[email protected]: move changes to build
pdata-quirks.cand call
topdata_quirks_init()to this patch]Signed-off-by Sekhar Nori <[email protected]>Signed-off-by Sasha Levin <[email protected]>Signed-off-by Greg Kroah-Hartman <[email protected]>
Quoted 5 lines
Quoted 2 lines
This does not add any useful feature or bug fix on its own. I don't think it should be backported to stable.
Yeah, that's really odd. It doesn't seem to do anything in Linus's tree either...
We have built on top for this for v4.12 kernel. Those patches are present in latest linux-next.
Quoted 1 line
I'll drop it from the stable trees queues now, thanks.
Thanks!
Regards,
Sekhar
Greg Kroah-Hartman
maintainerPATCH 117/152 usb: host: xhci-plat: enable BROKEN_PED quirk if platform requested
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Felipe Balbi <[email protected]>
[ Upstream commit 21939f003ad09355d9c975735750bb22aa37d8de ]
In case 'quirk-broken-port-ped' property is passed in via device property, we should enable the corresponding BROKEN_PED quirk flag for XHCI core.
[[email protected]] Updated code from platform data to device property and added DT binding.
--- Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 + drivers/usb/host/xhci-plat.c | 3 +++ 2 files changed, 4 insertions(+)
Documentation/devicetree/bindings/usb/usb-xhci.txt +1 -0
@@ -26,6 +26,7 @@ Required properties: Optional properties: - clocks: reference to a clock - usb3-lpm-capable: determines if platform is USB3 LPM capable + - quirk-broken-port-ped: set if the controller has broken port disable mechanism Example: usb@f0931000 {
drivers/usb/host/xhci-plat.c +3 -0
@@ -223,6 +223,9 @@ static int xhci_plat_probe(struct platfoif (device_property_read_bool (&pdev->dev,"usb3-lpm-capable" )) xhci->quirks |=XHCI_LPM_SUPPORT ; +if (device_property_read_bool (&pdev->dev,"quirk-broken-port-ped" )) + xhci->quirks |=XHCI_BROKEN_PORT_PED ; + hcd->usb_phy =devm_usb_get_phy_by_phandle (&pdev->dev,"usb-phy" ,0 );if (IS_ERR (hcd->usb_phy)) { ret =PTR_ERR (hcd->usb_phy);
Greg Kroah-Hartman
maintainerPATCH 118/152 usb: dwc3: host: pass quirk-broken-port-ped property for known broken revisions
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Felipe Balbi <[email protected]>
[ Upstream commit e42a5dbb8a3d14f5a35bffa3bf7dcb87883f767a ]
dwc3 revisions <=3.00a have a limitation where Port Disable command doesn't work. Set the quirk-broken-port-ped property for such controllers so XHCI core can do the necessary workaround.
[[email protected]] Updated code from platform data to device property.
--- drivers/usb/dwc3/host.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-)
drivers/usb/dwc3/host.c +18 -3
@@ -21,11 +21,12 @@int dwc3_host_init (struct dwc3 *dwc) { -struct property_entry props[2 ]; +struct property_entry props[3 ];struct platform_device *xhci;int ret, irq;struct resource *res;struct platform_device *dwc3_pdev =to_platform_device (dwc->dev); +int prop_idx =0 ; irq =platform_get_irq_byname (dwc3_pdev,"host" );if (irq == -EPROBE_DEFER )
@@ -89,8 +90,22 @@ int dwc3_host_init(struct dwc3 *dwc)memset (props,0 ,sizeof (struct property_entry ) *ARRAY_SIZE (props)); -if (dwc->usb3_lpm_capable) { - props[0 ].name ="usb3-lpm-capable" ; +if (dwc->usb3_lpm_capable) + props[prop_idx++].name ="usb3-lpm-capable" ; + +/** +* WORKAROUND: dwc3 revisions <=3.00a have a limitation +* where Port Disable command doesn't work. +* +* The suggested workaround is that we avoid Port Disable +* completely. +* +* This following flag tells XHCI to do just that. +*/ +if (dwc->revision <=DWC3_REVISION_300A ) + props[prop_idx++].name ="quirk-broken-port-ped" ; + +if (prop_idx) { ret =platform_device_add_properties (xhci, props);if (ret) {dev_err (dwc->dev,"failed to add properties to xHCI\n" );
Greg Kroah-Hartman
maintainerPATCH 119/152 drm/mga: remove device_is_agp callback
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Daniel Vetter <[email protected]>
[ Upstream commit 858b2c1bf820ebfba89c5e2867ab882bdb5b2f5a ]
It's only for a device quirk, and we might as well do that in the load callback.
--- drivers/gpu/drm/mga/mga_dma.c | 20 +++++++++++++++++++- drivers/gpu/drm/mga/mga_drv.c | 37 ------------------------------------- 2 files changed, 19 insertions(+), 38 deletions(-)
drivers/gpu/drm/mga/mga_dma.c +19 -1
@@ -392,6 +392,24 @@ int mga_driver_load(struct drm_device *ddrm_mga_private_t *dev_priv;int ret; +/* There are PCI versions of the G450. These cards have the +* same PCI ID as the AGP G450, but have an additional PCI-to-PCI +* bridge chip. We detect these cards, which are not currently +* supported by this driver, by looking at the device ID of the +* bus the "card" is on. If vendor is 0x3388 (Hint Corp) and the +* device is 0x0021 (HB6 Universal PCI-PCI bridge), we reject the +* device. +*/ +if ((dev->pdev->device ==0x0525 ) && dev->pdev->bus->self + && (dev->pdev->bus->self->vendor ==0x3388 ) + && (dev->pdev->bus->self->device ==0x0021 ) + && dev->agp) { +/* FIXME: This should be quirked in the pci core, but oh well +* the hw probably stopped existing. */ +arch_phys_wc_del (dev->agp->agp_mtrr); +kfree (dev->agp); + dev->agp =NULL ; + } dev_priv =kzalloc (sizeof (drm_mga_private_t),GFP_KERNEL );if (!dev_priv)return -ENOMEM ;
@@ -698,7 +716,7 @@ static int mga_do_pci_dma_bootstrap(strustatic int mga_do_dma_bootstrap (struct drm_device *dev,drm_mga_dma_bootstrap_t *dma_bs) { -const int is_agp = (dma_bs->agp_mode !=0 ) &&drm_pci_device_is_agp (dev); +const int is_agp = (dma_bs->agp_mode !=0 ) && dev->agp;int err;drm_mga_private_t *const dev_priv = (drm_mga_private_t *) dev->dev_private;
drivers/gpu/drm/mga/mga_drv.c +0 -37
@@ -37,8 +37,6 @@#include <drm/drm_pciids.h> -static int mga_driver_device_is_agp (struct drm_device *dev); -static struct pci_device_id pciidlist[] = { mga_PCI_IDS };
@@ -66,7 +64,6 @@ static struct drm_driver driver = { .lastclose = mga_driver_lastclose, .set_busid = drm_pci_set_busid, .dma_quiescent = mga_driver_dma_quiescent, - .device_is_agp = mga_driver_device_is_agp, .get_vblank_counter = mga_get_vblank_counter, .enable_vblank = mga_enable_vblank, .disable_vblank = mga_disable_vblank,
@@ -107,37 +104,3 @@ module_exit(mga_exit);MODULE_AUTHOR (DRIVER_AUTHOR );MODULE_DESCRIPTION (DRIVER_DESC );MODULE_LICENSE ("GPL and additional rights" ); - -/** -* Determine if the device really is AGP or not. -* -* In addition to the usual tests performed by \c drm_device_is_agp, this -* function detects PCI G450 cards that appear to the system exactly like -* AGP G450 cards. -* -* \param dev The device to be tested. -* -* \returns -* If the device is a PCI G450, zero is returned. Otherwise 2 is returned. -*/ -static int mga_driver_device_is_agp (struct drm_device *dev) -{ -const struct pci_dev *const pdev = dev->pdev; - -/* There are PCI versions of the G450. These cards have the -* same PCI ID as the AGP G450, but have an additional PCI-to-PCI -* bridge chip. We detect these cards, which are not currently -* supported by this driver, by looking at the device ID of the -* bus the "card" is on. If vendor is 0x3388 (Hint Corp) and the -* device is 0x0021 (HB6 Universal PCI-PCI bridge), we reject the -* device. -*/ - -if ((pdev->device ==0x0525 ) && pdev->bus->self - && (pdev->bus->self->vendor ==0x3388 ) - && (pdev->bus->self->device ==0x0021 )) { -return 0 ; - } - -return 2 ; -}
Greg Kroah-Hartman
maintainerPATCH 120/152 ARM: dts: STiH407-family: set snps,dis_u3_susphy_quirk
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Patrice Chotard <[email protected]>
[ Upstream commit 8413299cb3933dade6186bbee8363f190032107e ]
Since v4.10-rc1, the following logs appears in loop :
[ 801.953836] usb usb6-port1: Cannot enable. Maybe the USB cable is bad? [ 801.960455] xhci-hcd xhci-hcd.0.auto: Cannot set link state. [ 801.966611] usb usb6-port1: cannot disable (err = -32) [ 806.083772] usb usb6-port1: Cannot enable. Maybe the USB cable is bad? [ 806.090370] xhci-hcd xhci-hcd.0.auto: Cannot set link state. [ 806.096494] usb usb6-port1: cannot disable (err = -32)
After analysis, xhci try to set link in U3 and returns an error. Using snps,dis_u3_susphy_quirk fix this issue.
--- arch/arm/boot/dts/stih407-family.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/boot/dts/stih407-family.dtsi +1 -0
@@ -680,6 +680,7 @@ phy-names = "usb2-phy", "usb3-phy"; phys = <&usb2_picophy0>, <&phy_port2 PHY_TYPE_USB3>; + snps,dis_u3_susphy_quirk; }; };
Greg Kroah-Hartman
maintainerPATCH 121/152 PCI: Add ACS quirk for Intel Union Point
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Alex Williamson <[email protected]>
[ Upstream commit 7184f5b451cf3dc61de79091d235b5d2bba2782d ]
Intel 200-series chipsets have the same errata as 100-series: the ACS capability doesn't follow the PCIe spec, the capability and control registers are dwords rather than words. Add PCIe root port device IDs to existing quirk.
--- drivers/pci/quirks.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-)
drivers/pci/quirks.c +24 -4
@@ -4151,15 +4151,35 @@ static int pci_quirk_intel_pch_acs(struc* * N.B. This doesn't fix what lspci shows. * +* The 100 series chipset specification update includes this as errata #23[3]. +* +* The 200 series chipset (Union Point) has the same bug according to the +* specification update (Intel 200 Series Chipset Family Platform Controller +* Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, +* Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this +* chipset include: +* +* 0xa290-0xa29f PCI Express Root port #{0-16} +* 0xa2e7-0xa2ee PCI Express Root port #{17-24} +* * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html +* [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html +* [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html +* [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html */ static bool pci_quirk_intel_spt_pch_acs_match (struct pci_dev *dev) { -return pci_is_pcie (dev) && -pci_pcie_type (dev) ==PCI_EXP_TYPE_ROOT_PORT && - ((dev->device & ~0xf ) ==0xa110 || - (dev->device >=0xa167 && dev->device <=0xa16a )); +if (!pci_is_pcie (dev) ||pci_pcie_type (dev) !=PCI_EXP_TYPE_ROOT_PORT ) +return false; + +switch (dev->device) { + case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ + case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ +return true; + } + +return false; }#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
Greg Kroah-Hartman
maintainerPATCH 122/152 PCI: xgene: Fix double free on init error
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Dan Carpenter <[email protected]>
[ Upstream commit 1ded56df3247d358390ae6dc09ccee620262ac5f ]
The "port" variable was allocated with devm_kzalloc() so if we free it with kfree() it will be freed twice. Also I changed it to propogate the error from devm_ioremap_resource() instead of returning -ENOMEM.
--- drivers/pci/host/pci-xgene.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-)
drivers/pci/host/pci-xgene.c +2 -5
@@ -246,14 +246,11 @@ static int xgene_pcie_ecam_init(struct p ret =xgene_get_csr_resource (adev, &csr);if (ret) {dev_err (dev,"can't get CSR resource\n" ); -kfree (port);return ret; } port->csr_base =devm_ioremap_resource (dev, &csr); -if (IS_ERR (port->csr_base)) { -kfree (port); -return -ENOMEM ; - } +if (IS_ERR (port->csr_base)) +return PTR_ERR (port->csr_base); port->cfg_base = cfg->win; port->version = ipversion;
Greg Kroah-Hartman
maintainerPATCH 123/152 rx51: broken build
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sean Young <[email protected]>
[ Upstream commit 922ee72da7c739157ed02ea04a5c100d19f67226 ]
As reported by kernel build test:
In file included from arch/arm/mach-omap2/pdata-quirks.c:15:0:
Quoted 1 line
Quoted 1 line
arch/arm/mach-omap2/pdata-quirks.c:536:49: error: 'rx51_lirc_data' undeclared here (not in a function)
OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_lirc_data),
^
include/linux/of_platform.h:52:21: note: in definition of macro 'OF_DEV_AUXDATA'
.platform_data = _pdata }
^~~~~~Since "a92def1 [media] ir-rx51: port to rc-core" the build fails on some arm configurations.
--- arch/arm/mach-omap2/pdata-quirks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/mach-omap2/pdata-quirks.c +1 -1
@@ -534,7 +534,7 @@ static struct of_dev_auxdata omap_auxdat &omap3_iommu_pdata),OF_DEV_AUXDATA ("ti,omap3-hsmmc" ,0x4809c000 ,"4809c000.mmc" , &mmc_pdata[0 ]),OF_DEV_AUXDATA ("ti,omap3-hsmmc" ,0x480b4000 ,"480b4000.mmc" , &mmc_pdata[1 ]), -OF_DEV_AUXDATA ("nokia,n900-ir" ,0 ,"n900-ir" , &rx51_lirc_data), +OF_DEV_AUXDATA ("nokia,n900-ir" ,0 ,"n900-ir" , &rx51_ir_data),/* Only on am3517 */ OF_DEV_AUXDATA ("ti,davinci_mdio" ,0x5c030000 ,"davinci_mdio.0" ,NULL ), OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
Greg Kroah-Hartman
maintainerPATCH 124/152 sata: ahci-da850: implement a workaround for the softreset quirk
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Bartosz Golaszewski <[email protected]>
[ Upstream commit f4d435f3265661d04e5290a0a0450e3a38898128 ]
There's an issue with the da850 SATA controller: if port multiplier support is compiled in, but we're connecting the drive directly to the SATA port on the board, the drive can't be detected.
To make SATA work on the da850-lcdk board: first try to softreset with pmp - if the operation fails with -EBUSY, retry without pmp.
--- drivers/ata/ahci_da850.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-)
drivers/ata/ahci_da850.c +32 -1
@@ -54,11 +54,42 @@ static void da850_sata_init(struct devicwritel (val, ahci_base +SATA_P0PHYCR_REG ); } +static int ahci_da850_softreset (struct ata_link *link, +unsigned int *class,unsigned long deadline) +{ +int pmp, ret; + + pmp =sata_srst_pmp (link); + +/* +* There's an issue with the SATA controller on da850 SoCs: if we +* enable Port Multiplier support, but the drive is connected directly +* to the board, it can't be detected. As a workaround: if PMP is +* enabled, we first call ahci_do_softreset() and pass it the result of +* sata_srst_pmp(). If this call fails, we retry with pmp = 0. +*/ + ret =ahci_do_softreset (link, class, pmp, deadline, ahci_check_ready); +if (pmp && ret == -EBUSY ) +return ahci_do_softreset (link, class,0 , + deadline, ahci_check_ready); + +return ret; +} + +static struct ata_port_operations ahci_da850_port_ops = { + .inherits = &ahci_platform_ops, + .softreset = ahci_da850_softreset, +/* +* No need to override .pmp_softreset - it's only used for actual +* PMP-enabled ports. +*/ +}; +static const struct ata_port_info ahci_da850_port_info = { .flags =AHCI_FLAG_COMMON , .pio_mask =ATA_PIO4 , .udma_mask =ATA_UDMA6 , - .port_ops = &ahci_platform_ops, + .port_ops = &ahci_da850_port_ops, };static struct scsi_host_template ahci_platform_sht = {
Greg Kroah-Hartman
maintainerPATCH 125/152 ACPI / button: Change default behavior to lid_init_state=open
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Lv Zheng <[email protected]>
[ Upstream commit 77e9a4aa9de10cc1418bf9a892366988802a8025 ]
More and more platforms need the button.lid_init_state=open quirk. This patch sets it the default behavior.
If a platform doesn't send lid open event or lid open event is lost due to the underlying system problems, then we can compare various combinations:
1. systemd/acpid is used to suspend system or not, systemd has a special logic forcing open event after resuming;
2. _LID returns a cached value or not.
The result is as follows:
1. lid_init_state=method
1. cached
1. resumed by lid:
(x) event=close
(x) systemd=suspends again
(x) acpid=suspends again
(x) state=close
2. resumed by other:
(o) event=close
(x) systemd=suspends again
(x) acpid=suspends again
(o) state=close
2. non-cached
1. resumed by lid:
(o) event=open
(o) systemd=resumes
(o) acpid=resumes
(o) state=open
2. resumed by other:
(o) event=close
(x) systemd=suspends again
(x) acpid=suspends again
(o) state=close
2. lid_init_state=open
1. cached
1. resumed by lid:
(o) event=open
(o) systemd=resumes
(o) acpid=resumes
(x) state=close
2. resumed by other:
(x) event=open
(o) systemd=resumes
(o) acpid=resumes
(o) state=close
2. non-cached
1. resumed by lid:
(o) event=open
(o) systemd=resumes
(o) acpid=resumes
(o) state=open
2. resumed by other:
(x) event=open
(o) systemd=resumes
(o) acpid=resumes
(o) state=close
3. lid_init_state=ignore
1. cached
1. resumed by lid:
(o) event=none
(x) systemd=suspends again
(o) acpid=resumes
(x) state=close
2. resumed by other:
(o) event=none
(x) systemd=suspends again
(o) acpid=resumes
(o) state=close
2. non-cached
1. resumed by lid:
(o) event=none
(x) systemd=suspends again
(o) acpid=resumes
(o) state=open
2. resumed by other:
(o) event=none
(x) systemd=suspends again
(o) acpid=resumes
(o) state=close
As a conclusion:
1. With systemd changed, lid_init_state=ignore has only one problem and the problem comes from an underlying issue, not userspace and kernel lid handling.
2. Without systemd changed, lid_init_state=open can be the default behavior as the pass ratio is not much worse than lid_init_state=ignore.
3. lid_init_state=method is buggy, we can have a separate patch to make it deprectated.
--- drivers/acpi/button.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/button.c +1 -1
@@ -113,7 +113,7 @@ struct acpi_button {static BLOCKING_NOTIFIER_HEAD (acpi_lid_notifier);static struct acpi_device *lid_device; -static u8 lid_init_state =ACPI_BUTTON_LID_INIT_METHOD ; +static u8 lid_init_state =ACPI_BUTTON_LID_INIT_OPEN ;static unsigned long lid_report_interval__read_mostly =500 ;module_param (lid_report_interval, ulong,0644 );
Greg Kroah-Hartman
maintainerPATCH 126/152 ASoC: rt5670: Add missing 10EC5072 ACPI ID
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Takashi Iwai <[email protected]>
[ Upstream commit d25280060835e1b2b84c242905da8334ab15c5b4 ]
rt5670 driver supports also RT5672 codec, but its ACPI ID is missing. This was found on Dell Wyse 3040 box.
--- sound/soc/codecs/rt5670.c | 1 + 1 file changed, 1 insertion(+)
sound/soc/codecs/rt5670.c +1 -0
@@ -2813,6 +2813,7 @@ MODULE_DEVICE_TABLE(i2c, rt5670_i2c_id);#ifdef CONFIG_ACPI static const struct acpi_device_id rt5670_acpi_match[] = { {"10EC5670" ,0 }, + {"10EC5672" ,0 }, { }, };MODULE_DEVICE_TABLE (acpi, rt5670_acpi_match);
Greg Kroah-Hartman
maintainerPATCH 127/152 ASoC: codecs: rt5670: add quirk for Lenovo Thinkpad 10
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pierre-Louis Bossart <[email protected]>
[ Upstream commit 93ffeaa8ee3f10a0628ad135b552a2497e0bef2c ]
the BIOS incorrectly reports this codec as 5640 but it is really a rt5670
--- sound/soc/codecs/rt5670.c | 1 + 1 file changed, 1 insertion(+)
sound/soc/codecs/rt5670.c +1 -0
@@ -2814,6 +2814,7 @@ MODULE_DEVICE_TABLE(i2c, rt5670_i2c_id);static const struct acpi_device_id rt5670_acpi_match[] = { {"10EC5670" ,0 }, {"10EC5672" ,0 }, + {"10EC5640" ,0 },/* quirk */ { }, };MODULE_DEVICE_TABLE (acpi, rt5670_acpi_match);
Greg Kroah-Hartman
maintainerPATCH 128/152 ASoC: Intel: Baytrail: add quirk for Lenovo Thinkpad 10
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pierre-Louis Bossart <[email protected]>
[ Upstream commit fd0138dc5d17c636477b371d99265c406437c583 ]
the BIOS reports this codec as RT5640 but it's a rt5670. Use the quirk mechanism to use the cht_bsw_rt5672 machine driver
--- sound/soc/intel/atom/sst/sst_acpi.c | 37 +++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-)
sound/soc/intel/atom/sst/sst_acpi.c +36 -1
@@ -400,6 +400,7 @@ static int sst_acpi_remove(struct platfostatic unsigned long cht_machine_id;#define CHT_SURFACE_MACH 1 +#define BYT_THINKPAD_10 2static int cht_surface_quirk_cb (const struct dmi_system_id *id) {
@@ -407,6 +408,23 @@ static int cht_surface_quirk_cb(const streturn 1 ; } +static int byt_thinkpad10_quirk_cb (const struct dmi_system_id *id) +{ + cht_machine_id =BYT_THINKPAD_10 ; +return 1 ; +} + + +static const struct dmi_system_id byt_table[] = { + { + .callback = byt_thinkpad10_quirk_cb, + .matches = { +DMI_MATCH (DMI_SYS_VENDOR ,"LENOVO" ), +DMI_MATCH (DMI_PRODUCT_NAME ,"20C3001VHH" ), + }, + }, + { } +};static const struct dmi_system_id cht_table[] = { {
@@ -424,6 +442,10 @@ static struct sst_acpi_mach cht_surface_"10EC5640" ,"cht-bsw-rt5645" ,"intel/fw_sst_22a8.bin" ,"cht-bsw" ,NULL , &chv_platform_data }; +static struct sst_acpi_mach byt_thinkpad_10 = { +"10EC5640" ,"cht-bsw-rt5672" ,"intel/fw_sst_0f28.bin" ,"cht-bsw" ,NULL , + &byt_rvp_platform_data }; +static struct sst_acpi_mach *cht_quirk (void *arg) {struct sst_acpi_mach *mach = arg;
@@ -436,8 +458,21 @@ static struct sst_acpi_mach *cht_quirk(vreturn mach; } +static struct sst_acpi_mach *byt_quirk (void *arg) +{ +struct sst_acpi_mach *mach = arg; + +dmi_check_system (byt_table); + +if (cht_machine_id ==BYT_THINKPAD_10 ) +return &byt_thinkpad_10; +else +return mach; +} + +static struct sst_acpi_mach sst_acpi_bytcr[] = { - {"10EC5640" ,"bytcr_rt5640" ,"intel/fw_sst_0f28.bin" ,"bytcr_rt5640" ,NULL , + {"10EC5640" ,"bytcr_rt5640" ,"intel/fw_sst_0f28.bin" ,"bytcr_rt5640" , byt_quirk, &byt_rvp_platform_data }, {"10EC5642" ,"bytcr_rt5640" ,"intel/fw_sst_0f28.bin" ,"bytcr_rt5640" ,NULL , &byt_rvp_platform_data },
Greg Kroah-Hartman
maintainerPATCH 129/152 ASoC: Intel: cht_bsw_rt5645: harden ACPI device detection
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pierre-Louis Bossart <[email protected]>
[ Upstream commit 42648c2270ca0c96935dfc5d0f5c4f8d2406cf75 ]
Fix classic issue of having multiple codecs listed in DSDT but a single one actually enabled. The previous code did not handle such errors and could also lead to uninitalized configurations
--- sound/soc/intel/boards/cht_bsw_rt5645.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)
sound/soc/intel/boards/cht_bsw_rt5645.c +12 -2
@@ -358,22 +358,32 @@ static int snd_cht_mc_probe(struct platfstruct sst_acpi_mach *mach;const char *i2c_name =NULL ;int dai_index =0 ; +bool found = false; drv =devm_kzalloc (&pdev->dev,sizeof (*drv),GFP_ATOMIC );if (!drv)return -ENOMEM ; + mach = (&pdev->dev)->platform_data; +for (i =0 ; i <ARRAY_SIZE (snd_soc_cards); i++) { -if (acpi_dev_found (snd_soc_cards[i].codec_id)) { +if (acpi_dev_found (snd_soc_cards[i].codec_id) && + (!strncmp (snd_soc_cards[i].codec_id, mach->id,8 ))) {dev_dbg (&pdev->dev,"found codec %s\n" , snd_soc_cards[i].codec_id); card = snd_soc_cards[i].soc_card; drv->acpi_card = &snd_soc_cards[i]; + found = true;break ; } } + +if (!found) { +dev_err (&pdev->dev,"No matching HID found in supported list\n" ); +return -ENODEV ; + } + card->dev = &pdev->dev; - mach = card->dev->platform_data;sprintf (drv->codec_name,"i2c-%s:00" , drv->acpi_card->codec_id);/* set correct codec name */
Greg Kroah-Hartman
maintainerPATCH 130/152 ASoC: Intel: cht_bsw_rt5645: add Baytrail MCLK support
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pierre-Louis Bossart <[email protected]>
[ Upstream commit a50477e55fff69e1028f25624ee9fc9182d59b1f ]
The existing code assumes a 19.2 MHz MCLK as the default hardware configuration. This is valid for CherryTrail but not for Baytrail.
Add explicit MCLK configuration to set the 19.2 clock on/off depending on DAPM events.
This is a prerequisite step to enable devices with Baytrail and RT5645 such as Asus X205TA
--- sound/soc/intel/boards/cht_bsw_rt5645.c | 84 +++++++++++++++++++++++++++----- 1 file changed, 71 insertions(+), 13 deletions(-)
sound/soc/intel/boards/cht_bsw_rt5645.c +71 -13
@@ -24,6 +24,9 @@#include <linux/acpi.h> #include <linux/platform_device.h> #include <linux/slab.h> +#include <asm/cpu_device_id.h> +#include <asm/platform_sst_audio.h> +#include <linux/clk.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/soc.h>
@@ -45,6 +48,7 @@ struct cht_mc_private {struct snd_soc_jack jack;struct cht_acpi_card *acpi_card;char codec_name[16 ]; +struct clk *mclk; };static inline struct snd_soc_dai *cht_get_codec_dai (struct snd_soc_card *card)
@@ -65,6 +69,7 @@ static int platform_clock_control(structstruct snd_soc_dapm_context *dapm = w->dapm;struct snd_soc_card *card = dapm->card;struct snd_soc_dai *codec_dai; +struct cht_mc_private *ctx =snd_soc_card_get_drvdata (card);int ret; codec_dai =cht_get_codec_dai (card);
@@ -73,19 +78,30 @@ static int platform_clock_control(structreturn -EIO ; } -if (!SND_SOC_DAPM_EVENT_OFF (event)) -return 0 ; +if (SND_SOC_DAPM_EVENT_ON (event)) { +if (ctx->mclk) { + ret =clk_prepare_enable (ctx->mclk); +if (ret <0 ) { +dev_err (card->dev, +"could not configure MCLK state" ); +return ret; + } + } + }else { +/* Set codec sysclk source to its internal clock because codec PLL will +* be off when idle and MCLK will also be off when codec is +* runtime suspended. Codec needs clock for jack detection and button +* press. MCLK is turned off with clock framework or ACPI. +*/ + ret =snd_soc_dai_set_sysclk (codec_dai,RT5645_SCLK_S_RCCLK , +48000 *512 ,SND_SOC_CLOCK_IN ); +if (ret <0 ) { +dev_err (card->dev,"can't set codec sysclk: %d\n" , ret); +return ret; + } -/* Set codec sysclk source to its internal clock because codec PLL will -* be off when idle and MCLK will also be off by ACPI when codec is -* runtime suspended. Codec needs clock for jack detection and button -* press. -*/ - ret =snd_soc_dai_set_sysclk (codec_dai,RT5645_SCLK_S_RCCLK , -0 ,SND_SOC_CLOCK_IN ); -if (ret <0 ) { -dev_err (card->dev,"can't set codec sysclk: %d\n" , ret); -return ret; +if (ctx->mclk) +clk_disable_unprepare (ctx->mclk); }return 0 ;
@@ -97,7 +113,7 @@ static const struct snd_soc_dapm_widgetSND_SOC_DAPM_MIC ("Int Mic" ,NULL ),SND_SOC_DAPM_SPK ("Ext Spk" ,NULL ),SND_SOC_DAPM_SUPPLY ("Platform Clock" ,SND_SOC_NOPM ,0 ,0 , - platform_clock_control, SND_SOC_DAPM_POST_PMD), + platform_clock_control, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), }; static const struct snd_soc_dapm_route cht_rt5645_audio_map[] = {
@@ -225,6 +241,26 @@ static int cht_codec_init(struct snd_socrt5645_set_jack_detect (codec, &ctx->jack, &ctx->jack, &ctx->jack); +if (ctx->mclk) { +/* +* The firmware might enable the clock at +* boot (this information may or may not +* be reflected in the enable clock register). +* To change the rate we must disable the clock +* first to cover these cases. Due to common +* clock framework restrictions that do not allow +* to disable a clock that has not been enabled, +* we need to enable the clock first. +*/ + ret =clk_prepare_enable (ctx->mclk); +if (!ret) +clk_disable_unprepare (ctx->mclk); + + ret =clk_set_rate (ctx->mclk,CHT_PLAT_CLK_3_HZ ); + +if (ret) +dev_err (runtime->dev,"unable to set MCLK rate\n" ); + }return ret; }
@@ -349,6 +385,18 @@ static struct cht_acpi_card snd_soc_cardstatic char cht_rt5640_codec_name[16 ];/* i2c-<HID>:00 with HID being 8 chars */ +static bool is_valleyview (void ) +{ +static const struct x86_cpu_id cpu_ids[] = { + {X86_VENDOR_INTEL ,6 ,55 },/* Valleyview, Bay Trail */ + {} + }; + +if (!x86_match_cpu (cpu_ids)) +return false; +return true; +} +static int snd_cht_mc_probe (struct platform_device *pdev) {int ret_val =0 ;
@@ -401,6 +449,16 @@ static int snd_cht_mc_probe(struct platf cht_dailink[dai_index].codec_name = cht_rt5640_codec_name; } +if (is_valleyview ()) { + drv->mclk =devm_clk_get (&pdev->dev,"pmc_plt_clk_3" ); +if (IS_ERR (drv->mclk)) { +dev_err (&pdev->dev, +"Failed to get MCLK from pmc_plt_clk_3: %ld\n" , +PTR_ERR (drv->mclk)); +return PTR_ERR (drv->mclk); + } + } +snd_soc_card_set_drvdata (card, drv); ret_val =devm_snd_soc_register_card (&pdev->dev, card);if (ret_val) {
Greg Kroah-Hartman
maintainerPATCH 131/152 ACPI: save NVS memory for Lenovo G50-45
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Zhang Rui <[email protected]>
[ Upstream commit cbc00c1310d34139a63946482b40a6b261a03fb9 ]
In commit 821d6f0359b0 (ACPI / sleep: Do not save NVS for new machines to accelerate S3), to optimize S3 suspend/resume speed, code is introduced to ignore NVS memory saving during S3 for all the platforms later than 2012.
But, Lenovo G50-45, a platform released in 2015, still needs NVS memory saving during S3. A quirk is introduced for this platform.
--- drivers/acpi/sleep.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
drivers/acpi/sleep.c +19 -0
@@ -130,6 +130,12 @@ void __init acpi_nvs_nosave_s3(void) nvs_nosave_s3 = true; } +static int __init init_nvs_save_s3 (const struct dmi_system_id *d) +{ + nvs_nosave_s3 = false; +return 0 ; +} +/* * ACPI 1.0 wants us to execute _PTS before suspending devices, so we allow the * user to request that behavior by using the 'acpi_old_suspend_ordering'
@@ -324,6 +330,19 @@ static struct dmi_system_id acpisleep_dm DMI_MATCH(DMI_PRODUCT_NAME, "K54HR"), }, }, +/* +* https://bugzilla.kernel.org/show_bug.cgi?id=189431 +* Lenovo G50-45 is a platform later than 2012, but needs nvs memory +* saving during S3. +*/ + { + .callback = init_nvs_save_s3, + .ident = "Lenovo G50-45", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_PRODUCT_NAME, "80E3"), + }, + }, {}, };
Greg Kroah-Hartman
maintainerPATCH 132/152 usb: musb: da8xx: Fix host mode suspend
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Alexandre Bailon <[email protected]>
[ Upstream commit 486fc20ac8391338a42b015801b846acda4db7b7 ]
On da8xx, VBUS is not maintained during suspend when musb is in host mode. On resume, all the connected devices will be disconnected and then will be enumerated again.
This happens because MUSB_DEVCTL is cleared during suspend.
Use the quirk MUSB_PRESERVE_SESSION to preseve MUSB_DEVCTL during suspend.
--- drivers/usb/musb/da8xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/usb/musb/da8xx.c +1 -1
@@ -434,7 +434,7 @@ static int da8xx_musb_exit(struct musb * }static const struct musb_platform_ops da8xx_ops = { - .quirks =MUSB_INDEXED_EP , + .quirks =MUSB_INDEXED_EP |MUSB_PRESERVE_SESSION , .init = da8xx_musb_init, .exit = da8xx_musb_exit,
Greg Kroah-Hartman
maintainerPATCH 134/152 HID: wacom: dont apply generic settings to old devices
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Ping Cheng <[email protected]>
[ Upstream commit e7deb1570a527d3c74be4e21a72b1b459605c501 ]
Non-generic devices have numbered_buttons set for both pen and touch interfaces by default. The actual number of buttons on the interface is normally manually decided later, which is different from what those HID generic devices are processed, where number of buttons are directly retrieved from HID descriptors.
This patch adds the missed HID_GENERIC check and moves the statement to wacom_setup_pad_input_capabilities since it's not a quirk anymore.
--- drivers/hid/wacom_wac.c | 3 +++ 1 file changed, 3 insertions(+)
drivers/hid/wacom_wac.c +3 -0
@@ -2896,6 +2896,9 @@ int wacom_setup_pad_input_capabilities(s {struct wacom_features *features = &wacom_wac->features; +if ((features->type ==HID_GENERIC ) && features->numbered_buttons >0 ) + features->device_type |=WACOM_DEVICETYPE_PAD ; +if (!(features->device_type &WACOM_DEVICETYPE_PAD ))return -ENODEV ;
Greg Kroah-Hartman
maintainerPATCH 135/152 arm: kernel: Add SMC structure parameter
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Andy Gross <[email protected]>
[ Upstream commit 680a0873e193bae666439f4b5e32c758e68f114c ]
This patch adds a quirk parameter to the arm_smccc_(smc/hvc) calls. The quirk structure allows for specialized SMC operations due to SoC specific requirements. The current arm_smccc_(smc/hvc) is renamed and macros are used instead to specify the standard arm_smccc_(smc/hvc) or the arm_smccc_(smc/hvc)_quirk function.
This patch and partial implementation was suggested by Will Deacon.
--- arch/arm/kernel/armksyms.c | 4 ++-- arch/arm/kernel/smccc-call.S | 14 ++++++++------ arch/arm64/kernel/arm64ksyms.c | 4 ++-- arch/arm64/kernel/asm-offsets.c | 7 +++++-- arch/arm64/kernel/smccc-call.S | 14 ++++++++------ include/linux/arm-smccc.h | 40 ++++++++++++++++++++++++++++++++-------- 6 files changed, 57 insertions(+), 26 deletions(-)
arch/arm/kernel/armksyms.c +2 -2
@@ -178,6 +178,6 @@ EXPORT_SYMBOL(__pv_offset);#endif #ifdef CONFIG_HAVE_ARM_SMCCC -EXPORT_SYMBOL (arm_smccc_smc); -EXPORT_SYMBOL (arm_smccc_hvc); +EXPORT_SYMBOL (__arm_smccc_smc); +EXPORT_SYMBOL (__arm_smccc_hvc);#endif
arch/arm/kernel/smccc-call.S +8 -6
@@ -46,17 +46,19 @@ UNWIND( .fnend) /* * void smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, * unsigned long a3, unsigned long a4, unsigned long a5, - * unsigned long a6, unsigned long a7, struct arm_smccc_res *res) + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, + * struct arm_smccc_quirk *quirk) */ -ENTRY(arm_smccc_smc) +ENTRY(__arm_smccc_smc) SMCCC SMCCC_SMC -ENDPROC(arm_smccc_smc) +ENDPROC(__arm_smccc_smc) /* * void smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, * unsigned long a3, unsigned long a4, unsigned long a5, - * unsigned long a6, unsigned long a7, struct arm_smccc_res *res) + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, + * struct arm_smccc_quirk *quirk) */ -ENTRY(arm_smccc_hvc) +ENTRY(__arm_smccc_hvc) SMCCC SMCCC_HVC -ENDPROC(arm_smccc_hvc) +ENDPROC(__arm_smccc_hvc)
arch/arm64/kernel/arm64ksyms.c +2 -2
@@ -73,5 +73,5 @@ NOKPROBE_SYMBOL(_mcount);#endif /* arm-smccc */ -EXPORT_SYMBOL (arm_smccc_smc); -EXPORT_SYMBOL (arm_smccc_hvc); +EXPORT_SYMBOL (__arm_smccc_smc); +EXPORT_SYMBOL (__arm_smccc_hvc);
arch/arm64/kernel/asm-offsets.c +5 -2
@@ -140,8 +140,11 @@ int main(void)DEFINE (SLEEP_STACK_DATA_SYSTEM_REGS , offsetof(struct sleep_stack_data , system_regs));DEFINE (SLEEP_STACK_DATA_CALLEE_REGS , offsetof(struct sleep_stack_data , callee_saved_regs));#endif -DEFINE (ARM_SMCCC_RES_X0_OFFS , offsetof(struct arm_smccc_res , a0)); -DEFINE (ARM_SMCCC_RES_X2_OFFS , offsetof(struct arm_smccc_res , a2)); +DEFINE (ARM_SMCCC_RES_X0_OFFS , offsetof(struct arm_smccc_res , a0)); +DEFINE (ARM_SMCCC_RES_X2_OFFS , offsetof(struct arm_smccc_res , a2)); +DEFINE (ARM_SMCCC_QUIRK_ID_OFFS , offsetof(struct arm_smccc_quirk , id)); +DEFINE (ARM_SMCCC_QUIRK_STATE_OFFS , offsetof(struct arm_smccc_quirk , state)); +BLANK ();DEFINE (HIBERN_PBE_ORIG , offsetof(struct pbe , orig_address));DEFINE (HIBERN_PBE_ADDR , offsetof(struct pbe , address));
arch/arm64/kernel/smccc-call.S +8 -6
@@ -27,17 +27,19 @@ /* * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, * unsigned long a3, unsigned long a4, unsigned long a5, - * unsigned long a6, unsigned long a7, struct arm_smccc_res *res) + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, + * struct arm_smccc_quirk *quirk) */ -ENTRY(arm_smccc_smc) +ENTRY(__arm_smccc_smc) SMCCC smc -ENDPROC(arm_smccc_smc) +ENDPROC(__arm_smccc_smc) /* * void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, * unsigned long a3, unsigned long a4, unsigned long a5, - * unsigned long a6, unsigned long a7, struct arm_smccc_res *res) + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, + * struct arm_smccc_quirk *quirk) */ -ENTRY(arm_smccc_hvc) +ENTRY(__arm_smccc_hvc) SMCCC hvc -ENDPROC(arm_smccc_hvc) +ENDPROC(__arm_smccc_hvc)
include/linux/arm-smccc.h +32 -8
@@ -72,33 +72,57 @@ struct arm_smccc_res { };/** -* arm_smccc_smc() - make SMC calls +* struct arm_smccc_quirk - Contains quirk information +* @id: quirk identification +* @state: quirk specific information +* @a6: Qualcomm quirk entry for returning post-smc call contents of a6 +*/ +struct arm_smccc_quirk { +int id; +union { +unsigned long a6; + } state; +}; + +/** +* __arm_smccc_smc() - make SMC calls * @a0-a7: arguments passed in registers 0 to 7 * @res: result values from registers 0 to 3 +* @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. * * This function is used to make SMC calls following SMC Calling Convention. * The content of the supplied param are copied to registers 0 to 7 prior * to the SMC instruction. The return values are updated with the content -* from register 0 to 3 on return from the SMC instruction. +* from register 0 to 3 on return from the SMC instruction. An optional +* quirk structure provides vendor specific behavior. */ -asmlinkage void arm_smccc_smc(unsigned long a0, unsigned long a1, +asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1,unsigned long a2,unsigned long a3,unsigned long a4,unsigned long a5,unsigned long a6,unsigned long a7, -struct arm_smccc_res *res); +struct arm_smccc_res *res,struct arm_smccc_quirk *quirk);/** -* arm_smccc_hvc() - make HVC calls +* __arm_smccc_hvc() - make HVC calls * @a0-a7: arguments passed in registers 0 to 7 * @res: result values from registers 0 to 3 * * This function is used to make HVC calls following SMC Calling * Convention. The content of the supplied param are copied to registers 0 * to 7 prior to the HVC instruction. The return values are updated with -* the content from register 0 to 3 on return from the HVC instruction. +* the content from register 0 to 3 on return from the HVC instruction. An +* optional quirk structure provides vendor specific behavior. */ -asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, +asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,unsigned long a2,unsigned long a3,unsigned long a4,unsigned long a5,unsigned long a6,unsigned long a7, -struct arm_smccc_res *res); +struct arm_smccc_res *res,struct arm_smccc_quirk *quirk); + +#define arm_smccc_smc (...) __arm_smccc_smc(__VA_ARGS__, NULL) + +#define arm_smccc_smc_quirk (...) __arm_smccc_smc(__VA_ARGS__) + +#define arm_smccc_hvc (...) __arm_smccc_hvc(__VA_ARGS__, NULL) + +#define arm_smccc_hvc_quirk (...) __arm_smccc_hvc(__VA_ARGS__)#endif /*__LINUX_ARM_SMCCC_H*/
Greg Kroah-Hartman
maintainerPATCH 136/152 firmware: qcom: scm: Fix interrupted SCM calls
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Andy Gross <[email protected]>
[ Upstream commit 82bcd087029f6056506ea929f11af02622230901 ]
This patch adds a Qualcomm specific quirk to the arm_smccc_smc call.
On Qualcomm ARM64 platforms, the SMC call can return before it has completed. If this occurs, the call can be restarted, but it requires using the returned session ID value from the interrupted SMC call.
The quirk stores off the session ID from the interrupted call in the quirk structure so that it can be used by the caller.
This patch folds in a fix given by Sricharan R:
https://lkml.org/lkml/2016/9/28/272
--- arch/arm64/kernel/smccc-call.S | 9 ++++++++- drivers/firmware/qcom_scm-64.c | 13 ++++++++++--- include/linux/arm-smccc.h | 11 ++++++++--- 3 files changed, 26 insertions(+), 7 deletions(-)
arch/arm64/kernel/smccc-call.S +8 -1
@@ -12,6 +12,7 @@ * */ #include <linux/linkage.h> +#include <linux/arm-smccc.h> #include <asm/asm-offsets.h> .macro SMCCC instr
@@ -20,7 +21,13 @@ ldr x4, [sp] stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS] stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS] - ret + ldr x4, [sp, #8] + cbz x4, 1f /* no quirk structure */ + ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS] + cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6 + b.ne 1f + str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS] +1: ret .cfi_endproc .endm
drivers/firmware/qcom_scm-64.c +10 -3
@@ -91,6 +91,7 @@ static int qcom_scm_call(struct device *dma_addr_t args_phys =0 ;void *args_virt =NULL ;size_t alloc_len; +struct arm_smccc_quirk quirk = {.id =ARM_SMCCC_QUIRK_QCOM_A6 };if (unlikely (arglen >N_REGISTER_ARGS )) { alloc_len =N_EXT_QCOM_SCM_ARGS *sizeof (u64);
@@ -131,10 +132,16 @@ static int qcom_scm_call(struct device * qcom_smccc_convention, ARM_SMCCC_OWNER_SIP, fn_id); + quirk.state.a6 =0 ; +do { -arm_smccc_smc (cmd, desc->arginfo, desc->args[0 ], - desc->args[1 ], desc->args[2 ], x5,0 ,0 , - res); +arm_smccc_smc_quirk (cmd, desc->arginfo, desc->args[0 ], + desc->args[1 ], desc->args[2 ], x5, + quirk.state.a6,0 , res, &quirk); + +if (res->a0 ==QCOM_SCM_INTERRUPTED ) + cmd = res->a0; + }while (res->a0 ==QCOM_SCM_INTERRUPTED );mutex_unlock (&qcom_scm_lock);
include/linux/arm-smccc.h +8 -3
@@ -14,9 +14,6 @@#ifndef __LINUX_ARM_SMCCC_H#define __LINUX_ARM_SMCCC_H -#include <linux/linkage.h> -#include <linux/types.h> -/* * This file provides common defines for ARM SMC Calling Convention as * specified in
@@ -60,6 +57,13 @@#define ARM_SMCCC_OWNER_TRUSTED_OS 50#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 +#define ARM_SMCCC_QUIRK_NONE 0 +#define ARM_SMCCC_QUIRK_QCOM_A6 1/* Save/restore register a6 */ + +#ifndef __ASSEMBLY__ + +#include <linux/linkage.h> +#include <linux/types.h> /** * struct arm_smccc_res - Result from SMC/HVC call * @a0-a3 result values from registers 0 to 3
@@ -125,4 +129,5 @@ asmlinkage void __arm_smccc_hvc(unsigned#define arm_smccc_hvc_quirk (...) __arm_smccc_hvc(__VA_ARGS__) +#endif /*__ASSEMBLY__*/ #endif /*__LINUX_ARM_SMCCC_H*/
Greg Kroah-Hartman
maintainerPATCH 137/152 drm/msm/adreno: move function declarations to header file
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Baoyou Xie <[email protected]>
[ Upstream commit a5725ab0497ad91a2df7c01a78bf1a0cc5be4526 ]
We get 2 warnings when building kernel with W=1:drivers/gpu/drm/msm/adreno/a3xx_gpu.c:535:17: warning: no previous prototype for 'a3xx_gpu_init' [-Wmissing-prototypes] drivers/gpu/drm/msm/adreno/a4xx_gpu.c:624:17: warning: no previous prototype for 'a4xx_gpu_init' [-Wmissing-prototypes]
In fact, both functions are declared in drivers/gpu/drm/msm/adreno/adreno_device.c, but should be declared in a header file. So this patch moves both function declarations to drivers/gpu/drm/msm/adreno/adreno_gpu.h.
--- drivers/gpu/drm/msm/adreno/adreno_device.c | 3 --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-)
drivers/gpu/drm/msm/adreno/adreno_device.c +0 -3
@@ -25,9 +25,6 @@ bool hang_debug = false;MODULE_PARM_DESC (hang_debug,"Dump registers when hang is detected (can be slow!)" );module_param_named (hang_debug, hang_debug, bool,0600 ); -struct msm_gpu *a3xx_gpu_init (struct drm_device *dev); -struct msm_gpu *a4xx_gpu_init (struct drm_device *dev); -static const struct adreno_info gpulist[] = { { .rev =ADRENO_REV (3 ,0 ,5 ,ANY_ID ),
drivers/gpu/drm/msm/adreno/adreno_gpu.h +3 -0
@@ -311,4 +311,7 @@ static inline void adreno_gpu_write(stru gpu_write(&gpu->base, reg - 1, data); } +struct msm_gpu *a3xx_gpu_init (struct drm_device *dev); +struct msm_gpu *a4xx_gpu_init (struct drm_device *dev); +#endif /* __ADRENO_GPU_H__ */
Greg Kroah-Hartman
maintainerPATCH 138/152 ARM: smccc: Update HVC comment to describe new quirk parameter
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Will Deacon <[email protected]>
[ Upstream commit 3046ec674d441562c6bb3e4284cd866743042ef3 ]
Commit 680a0873e193 ("arm: kernel: Add SMC structure parameter") added a new "quirk" parameter to the SMC and HVC SMCCC backends, but only updated the comment for the SMC version. This patch adds the new paramater to the comment describing the HVC version too.
--- include/linux/arm-smccc.h | 1 + 1 file changed, 1 insertion(+)
include/linux/arm-smccc.h +1 -0
@@ -109,6 +109,7 @@ asmlinkage void __arm_smccc_smc(unsigned* __arm_smccc_hvc() - make HVC calls * @a0-a7: arguments passed in registers 0 to 7 * @res: result values from registers 0 to 3 +* @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. * * This function is used to make HVC calls following SMC Calling * Convention. The content of the supplied param are copied to registers 0
Greg Kroah-Hartman
maintainerPATCH 139/152 PCI: Add Broadcom Northstar2 PAXC quirk for device class and MPSS
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jon Mason <[email protected]>
[ Upstream commit ce709f86501a013e941e9986cb072eae375ddf3e ]
The Broadcom Northstar2 SoC has a number of quirks for the PAXC (internal/fake) PCI bus. Specifically, the PCI config space is shared between the root port and the first PF (ie., PF0), and a number of fields are tied to zero (thus preventing them from being set). These cannot be "fixed" in device firmware, so we must fix them with a quirk.
--- drivers/pci/quirks.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
drivers/pci/quirks.c +21 -0
@@ -2240,6 +2240,27 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BPCI_DEVICE_ID_TIGON3_5719 , quirk_brcm_5719_limit_mrrs); +#ifdef CONFIG_PCIE_IPROC_PLATFORM +static void quirk_paxc_bridge (struct pci_dev *pdev) +{ +/* The PCI config space is shared with the PAXC root port and the first +* Ethernet device. So, we need to workaround this by telling the PCI +* code that the bridge is not an Ethernet device. +*/ +if (pdev->hdr_type ==PCI_HEADER_TYPE_BRIDGE ) + pdev->class =PCI_CLASS_BRIDGE_PCI <<8 ; + +/* MPSS is not being set properly (as it is currently 0). This is +* because that area of the PCI config space is hard coded to zero, and +* is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) +* so that the MPS can be set to the real max value. +*/ + pdev->pcie_mpss =2 ; +} +DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_BROADCOM ,0x16cd , quirk_paxc_bridge); +DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_BROADCOM ,0x16f0 , quirk_paxc_bridge); +#endif +/* Originally in EDAC sources for i82875P: * Intel tells BIOS developers to hide device 6 which * configures the overflow device access containing
Greg Kroah-Hartman
maintainerPATCH 140/152 PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Dongdong Liu <[email protected]>
[ Upstream commit 72f2ff0deb870145a5a2d24cd75b4f9936159a62 ]
The PCIe Root Port in Hip06/Hip07 SoCs advertises an MSI capability, but it cannot generate MSIs. It can transfer MSI/MSI-X from downstream devices, but does not support MSI/MSI-X itself.
Add a quirk to prevent use of MSI/MSI-X by the Root Port.
--- drivers/pci/quirks.c | 1 + include/linux/pci_ids.h | 2 ++ 2 files changed, 3 insertions(+)
drivers/pci/quirks.c +1 -0
@@ -1634,6 +1634,7 @@ static void quirk_pcie_mch(struct pci_deDECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_E7520_MCH , quirk_pcie_mch);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_E7320_MCH , quirk_pcie_mch);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_E7525_MCH , quirk_pcie_mch); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_HUAWEI ,0x1610 , quirk_pcie_mch);/*
include/linux/pci_ids.h +2 -0
@@ -2513,6 +2513,8 @@#define PCI_DEVICE_ID_KORENIX_JETCARDF2 0x1700#define PCI_DEVICE_ID_KORENIX_JETCARDF3 0x17ff +#define PCI_VENDOR_ID_HUAWEI 0x19e5 +#define PCI_VENDOR_ID_NETRONOME 0x19ee#define PCI_DEVICE_ID_NETRONOME_NFP3200 0x3200#define PCI_DEVICE_ID_NETRONOME_NFP3240 0x3240
Greg Kroah-Hartman
maintainerPATCH 141/152 mmc: sdhci-of-esdhc: remove default broken-cd for ARM
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: yangbo lu <[email protected]>
[ Upstream commit e9acc77dd046b22c7ebf70e35f68968978445f8b ]
Initially all QorIQ platforms were PowerPC architecture and they didn't support card detection except several platforms. The driver added the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION as default and this made broken-cd property in dts node didn't work. Now QorIQ platform turns to ARM architecture and most of them could support card detection. However it's a large number of dts trees that need to be fixed with broken-cd if we remove the default SDHCI_QUIRK_BROKEN_CARD_DETECTION in driver. And the users don't want to see this. So this patch is to remove this default quirk just for ARM and keep it for PowerPC.(Note, QorIQ PowerPC platform only has big-endian eSDHC while QorIQ ARM platform has big-endian or little-endian eSDHC) This makes broken-cd property work again for ARM.
--- drivers/mmc/host/sdhci-of-esdhc.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-)
drivers/mmc/host/sdhci-of-esdhc.c +10 -8
@@ -559,16 +559,19 @@ static const struct sdhci_ops sdhci_esdh };static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { - .quirks =ESDHC_DEFAULT_QUIRKS |SDHCI_QUIRK_BROKEN_CARD_DETECTION - |SDHCI_QUIRK_NO_CARD_NO_RESET - |SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC , + .quirks =ESDHC_DEFAULT_QUIRKS | +#ifdef CONFIG_PPC +SDHCI_QUIRK_BROKEN_CARD_DETECTION | +#endif +SDHCI_QUIRK_NO_CARD_NO_RESET | +SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC , .ops = &sdhci_esdhc_be_ops, };static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { - .quirks =ESDHC_DEFAULT_QUIRKS |SDHCI_QUIRK_BROKEN_CARD_DETECTION - |SDHCI_QUIRK_NO_CARD_NO_RESET - |SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC , + .quirks =ESDHC_DEFAULT_QUIRKS | +SDHCI_QUIRK_NO_CARD_NO_RESET | +SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC , .ops = &sdhci_esdhc_le_ops, };
@@ -623,8 +626,7 @@ static int sdhci_esdhc_probe(struct platof_device_is_compatible (np,"fsl,p5020-esdhc" ) ||of_device_is_compatible (np,"fsl,p4080-esdhc" ) ||of_device_is_compatible (np,"fsl,p1020-esdhc" ) || -of_device_is_compatible (np,"fsl,t1040-esdhc" ) || - of_device_is_compatible(np, "fsl,ls1021a-esdhc")) + of_device_is_compatible(np, "fsl,t1040-esdhc")) host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;if (of_device_is_compatible (np,"fsl,ls1021a-esdhc" ))
Greg Kroah-Hartman
maintainerPATCH 142/152 PCI: Sort the list of devices with D3 delay quirk by ID
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Andy Shevchenko <[email protected]>
[ Upstream commit cd3e2eb8905d14fe28a2fc75362b8ecec16f0fb6 ]
Sort the list of Intel devices that have no PCI D3 delay by ID. Add a comment for group of devices that had not been marked yet.
There is no functional change.
--- drivers/pci/quirks.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-)
drivers/pci/quirks.c +14 -12
@@ -3136,30 +3136,32 @@ static void quirk_remove_d3_delay(struct { dev->d3_delay =0 ; } -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x0c00 , quirk_remove_d3_delay); +/* C600 Series devices do not need 10ms d3_delay */ DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x0412 , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x0c00 , quirk_remove_d3_delay);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x0c0c , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c31 , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c3a , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c3d , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c2d , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c20 , quirk_remove_d3_delay); +/* Lynxpoint-H PCH devices do not need 10ms d3_delay */ +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c02 , quirk_remove_d3_delay);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c18 , quirk_remove_d3_delay);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c1c , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c20 , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c22 , quirk_remove_d3_delay);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c26 , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c2d , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c31 , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c3a , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c3d , quirk_remove_d3_delay);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c4e , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c02 , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x8c22 , quirk_remove_d3_delay);/* Intel Cherrytrail devices do not need 10ms d3_delay */ DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x2280 , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x2298 , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x229c , quirk_remove_d3_delay);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x22b0 , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x22b5 , quirk_remove_d3_delay); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x22b7 , quirk_remove_d3_delay);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x22b8 , quirk_remove_d3_delay);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x22d8 , quirk_remove_d3_delay);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x22dc , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x22b5 , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x22b7 , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x2298 , quirk_remove_d3_delay); -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,0x229c , quirk_remove_d3_delay);/* * Some devices may pass our check in pci_intx_mask_supported() if
Greg Kroah-Hartman
maintainerPATCH 143/152 PCI: Add ACS quirk for Qualcomm QDF2400 and QDF2432
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sinan Kaya <[email protected]>
[ Upstream commit 33be632b8443b6ac74aa293504f430604fb9abeb ]
The Qualcomm QDF2xxx root ports don't advertise an ACS capability, but they do provide ACS-like features to disable peer transactions and validate bus numbers in requests.
To be specific:
* Hardware supports source validation but it will report the issue as Completer Abort instead of ACS Violation.
* Hardware doesn't support peer-to-peer and each root port is a root complex with unique segment numbers.
* It is not possible for one root port to pass traffic to the other root port. All PCIe transactions are terminated inside the root port.
Add an ACS quirk for the QDF2400 and QDF2432 products.
--- drivers/pci/quirks.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
drivers/pci/quirks.c +23 -0
@@ -4161,6 +4161,26 @@ static int pci_quirk_intel_pch_acs(struc }/* +* These QCOM root ports do provide ACS-like features to disable peer +* transactions and validate bus numbers in requests, but do not provide an +* actual PCIe ACS capability. Hardware supports source validation but it +* will report the issue as Completer Abort instead of ACS Violation. +* Hardware doesn't support peer-to-peer and each root port is a root +* complex with unique segment numbers. It is not possible for one root +* port to pass traffic to another root port. All PCIe transactions are +* terminated inside the root port. +*/ +static int pci_quirk_qcom_rp_acs (struct pci_dev *dev,u16 acs_flags) +{ +u16 flags = (PCI_ACS_RR |PCI_ACS_CR |PCI_ACS_UF |PCI_ACS_SV ); +int ret = acs_flags & ~flags ?0 :1 ; + +dev_info (&dev->dev,"Using QCOM ACS Quirk (%d)\n" , ret); + +return ret; +} + +/* * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
@@ -4316,6 +4336,9 @@ static const struct pci_dev_acs_enabled/* I219 */ { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, +/* QCOM QDF2xxx root ports */ + { 0x17cb, 0x400, pci_quirk_qcom_rp_acs }, + { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },/* Intel PCH root ports */ { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
Greg Kroah-Hartman
maintainerPATCH 144/152 watchdog: s3c2410: Fix infinite interrupt in soft mode
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Krzysztof Kozlowski <[email protected]>
[ Upstream commit 0b445549ea6f91ffea78a976fe89b932db6e077a ]
In soft (no-reboot) mode, the driver self-pings watchdog upon expiration of an interrupt. However the interrupt itself was not cleared thus on first hit, the system enters infinite interrupt handling loop.
On Odroid U3 (Exynos4412), when booted with s3c2410_wdt.soft_noboot=1 argument the console is flooded:
# killall -9 watchdog [ 60.523760] s3c2410-wdt 10060000.watchdog: watchdog timer expired (irq) [ 60.536744] s3c2410-wdt 10060000.watchdog: watchdog timer expired (irq)
Fix this by writing something to the WTCLRINT register to clear the interrupt. The register WTCLRINT however appeared in S3C6410 so a new watchdog quirk and flavor are needed.
--- Documentation/devicetree/bindings/watchdog/samsung-wdt.txt | 9 +++-- drivers/watchdog/s3c2410_wdt.c | 21 +++++++++++-- 2 files changed, 23 insertions(+), 7 deletions(-)
Documentation/devicetree/bindings/watchdog/samsung-wdt.txt +5 -4
@@ -6,10 +6,11 @@ occurred. Required properties: - compatible : should be one among the following - (a) "samsung,s3c2410-wdt" for Exynos4 and previous SoCs - (b) "samsung,exynos5250-wdt" for Exynos5250 - (c) "samsung,exynos5420-wdt" for Exynos5420 - (c) "samsung,exynos7-wdt" for Exynos7 + - "samsung,s3c2410-wdt" for S3C2410 + - "samsung,s3c6410-wdt" for S3C6410, S5PV210 and Exynos4 + - "samsung,exynos5250-wdt" for Exynos5250 + - "samsung,exynos5420-wdt" for Exynos5420 + - "samsung,exynos7-wdt" for Exynos7 - reg : base physical address of the controller and length of memory mapped region.
drivers/watchdog/s3c2410_wdt.c +18 -3
@@ -46,6 +46,7 @@#define S3C2410_WTCON 0x00#define S3C2410_WTDAT 0x04#define S3C2410_WTCNT 0x08 +#define S3C2410_WTCLRINT 0x0c#define S3C2410_WTCNT_MAXCNT 0xffff
@@ -72,6 +73,7 @@#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c#define QUIRK_HAS_PMU_CONFIG (1 << 0)#define QUIRK_HAS_RST_STAT (1 << 1) +#define QUIRK_HAS_WTCLRINT_REG (1 << 2)/* These quirks require that we have a PMU register map */ #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
@@ -143,13 +145,18 @@ static const struct s3c2410_wdt_variant };#ifdef CONFIG_OF +static const struct s3c2410_wdt_variant drv_data_s3c6410 = { + .quirks =QUIRK_HAS_WTCLRINT_REG , +}; +static const struct s3c2410_wdt_variant drv_data_exynos5250 = { .disable_reg =EXYNOS5_WDT_DISABLE_REG_OFFSET , .mask_reset_reg =EXYNOS5_WDT_MASK_RESET_REG_OFFSET , .mask_bit =20 , .rst_stat_reg =EXYNOS5_RST_STAT_REG_OFFSET , .rst_stat_bit =20 , - .quirks =QUIRK_HAS_PMU_CONFIG |QUIRK_HAS_RST_STAT , + .quirks =QUIRK_HAS_PMU_CONFIG |QUIRK_HAS_RST_STAT \ + |QUIRK_HAS_WTCLRINT_REG , }; static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
@@ -158,7 +165,8 @@ static const struct s3c2410_wdt_variant .mask_bit = 0, .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, .rst_stat_bit = 9, - .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, + .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ + | QUIRK_HAS_WTCLRINT_REG, };static const struct s3c2410_wdt_variant drv_data_exynos7 = {
@@ -167,12 +175,15 @@ static const struct s3c2410_wdt_variant .mask_bit = 23, .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, .rst_stat_bit = 23, /* A57 WDTRESET */ - .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, + .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ + | QUIRK_HAS_WTCLRINT_REG, };static const struct of_device_id s3c2410_wdt_match[] = { { .compatible ="samsung,s3c2410-wdt" , .data = &drv_data_s3c2410 }, + { .compatible ="samsung,s3c6410-wdt" , + .data = &drv_data_s3c6410 }, { .compatible ="samsung,exynos5250-wdt" , .data = &drv_data_exynos5250 }, { .compatible ="samsung,exynos5420-wdt" ,
@@ -418,6 +429,10 @@ static irqreturn_t s3c2410wdt_irq(int irdev_info (wdt->dev,"watchdog timer expired (irq)\n" );s3c2410wdt_keepalive (&wdt->wdt_device); + +if (wdt->drv_data->quirks &QUIRK_HAS_WTCLRINT_REG ) +writel (0x1 , wdt->reg_base +S3C2410_WTCLRINT ); +return IRQ_HANDLED ; }
Greg Kroah-Hartman
maintainerPATCH 145/152 platform/x86: asus-wmi: Set specified XUSB2PR value for X550LB
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Kai-Chuan Hsieh <[email protected]>
[ Upstream commit 8023eff10e7b0327898f17f0b553d2e45c71cef3 ]
The bluetooth adapter Atheros AR3012 can't be enumerated and make the bluetooth function broken.
T: Bus=02 Lev=01 Prnt=01 Port=05 Cnt=02 Dev#= 5 Spd=12 MxCh= 0 D: Ver= 1.10 Cls=e0(wlcon) Sub=01 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=13d3 ProdID=3362 Rev=00.02 S: Manufacturer=Atheros Communications S: Product=Bluetooth USB Host Controller S: SerialNumber=Alaska Day 2006 C: #Ifs= 2 Cfg#= 1 Atr=e0 MxPwr=100mA I: If#= 0 Alt= 0 #EPs= 3 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb I: If#= 1 Alt= 0 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb
The error is:
usb 2-6: device not accepting address 7, error -62 usb usb2-port6: unable to enumerate USB device
It is caused by adapter's connected port is mapped to xHC controller, but the xHCI is not supported by the usb device.
The output of 'sudo lspci -nnxxx -s 00:14.0':
00:14.0 USB controller [0c03]: Intel Corporation 8 Series USB xHCI HC [8086:9c31] (rev 04) 00: 86 80 31 9c 06 04 90 02 04 30 03 0c 00 00 00 00
10: 04 00 a0 f7 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 1f 20
30: 00 00 00 00 70 00 00 00 00 00 00 00 0b 01 00 00
40: fd 01 36 80 89 c6 0f 80 00 00 00 00 00 00 00 00
50: 5f 2e ce 0f 00 00 00 00 00 00 00 00 00 00 00 00
60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 01 80 c2 c1 08 00 00 00 00 00 00 00 00 00 00 00
80: 05 00 87 00 0c a0 e0 fe 00 00 00 00 a1 41 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 0f 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 03 c0 30 00 00 00 00 00 03 0c 00 00 00 00 00 00
d0: f9 01 00 00 f9 01 00 00 0f 00 00 00 0f 00 00 00
e0: 00 08 00 00 00 00 00 00 00 00 00 00 d8 d8 00 00
f0: 00 00 00 00 00 00 00 00 b1 0f 04 08 00 00 00 00
By referencing Intel Platform Controller Hub(PCH) datasheet, the xHC USB 2.0 Port Routing(XUSB2PR) at offset 0xD0-0xD3h decides the setting of mapping the port to EHCI controller or xHC controller. And the port mapped to xHC will enable xHCI during bus resume.
The setting of disabling bluetooth adapter's connected port is 0x000001D9. The value can be obtained by few times 1 bit flip operation. The suited configuration should have the 'lsusb -t' result with bluetooth using ehci:
/: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/4p, 5000M
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/9p, 480M
|__ Port 5: Dev 2, If 0, Class=Video, Driver=uvcvideo, 480M
|__ Port 5: Dev 2, If 1, Class=Video, Driver=uvcvideo, 480M
/: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=ehci-pci/2p, 480M
|__ Port 1: Dev 2, If 0, Class=Hub, Driver=hub/8p, 480M
|__ Port 6: Dev 3, If 0, Class=Wireless, Driver=btusb, 12M
|__ Port 6: Dev 3, If 1, Class=Wireless, Driver=btusb, 12M--- drivers/platform/x86/asus-nb-wmi.c | 13 +++++++++++++ drivers/platform/x86/asus-wmi.c | 29 +++++++++++++++++++++++++++++ drivers/platform/x86/asus-wmi.h | 1 + 3 files changed, 43 insertions(+)
drivers/platform/x86/asus-nb-wmi.c +13 -0
@@ -116,6 +116,10 @@ static struct quirk_entry quirk_asus_ux3 .wmi_backlight_native = true, }; +static struct quirk_entry quirk_asus_x550lb = { + .xusb2pr =0x01D9 , +}; +static int dmi_matched (const struct dmi_system_id *dmi) { quirks = dmi->driver_data;
@@ -407,6 +411,15 @@ static const struct dmi_system_id asus_q }, .driver_data = &quirk_asus_ux303ub, }, + { + .callback = dmi_matched, + .ident = "ASUSTeK COMPUTER INC. X550LB", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), + DMI_MATCH(DMI_PRODUCT_NAME, "X550LB"), + }, + .driver_data = &quirk_asus_x550lb, + }, {}, };
drivers/platform/x86/asus-wmi.c +29 -0
@@ -156,6 +156,9 @@ MODULE_LICENSE("GPL");#define ASUS_FAN_CTRL_MANUAL 1#define ASUS_FAN_CTRL_AUTO 2 +#define USB_INTEL_XUSB2PR 0xD0 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 +struct bios_args {u32 arg0;u32 arg1;
@@ -1080,6 +1083,29 @@ exit:return result; } +static void asus_wmi_set_xusb2pr (struct asus_wmi *asus) +{ +struct pci_dev *xhci_pdev; +u32 orig_ports_available; +u32 ports_available = asus->driver->quirks->xusb2pr; + + xhci_pdev =pci_get_device (PCI_VENDOR_ID_INTEL , +PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI , +NULL ); + +if (!xhci_pdev) +return ; + +pci_read_config_dword (xhci_pdev,USB_INTEL_XUSB2PR , + &orig_ports_available); + +pci_write_config_dword (xhci_pdev,USB_INTEL_XUSB2PR , +cpu_to_le32 (ports_available)); + +pr_info ("set USB_INTEL_XUSB2PR old: 0x%04x, new: 0x%04x\n" , + orig_ports_available, ports_available); +} +/* * Hwmon device */
@@ -2087,6 +2113,9 @@ static int asus_wmi_add(struct platform_if (asus->driver->quirks->wmi_backlight_native)acpi_video_set_dmi_backlight_type (acpi_backlight_native); +if (asus->driver->quirks->xusb2pr) +asus_wmi_set_xusb2pr (asus); +if (acpi_video_get_backlight_type () == acpi_backlight_vendor) { err =asus_wmi_backlight_init (asus);if (err && err != -ENODEV )
drivers/platform/x86/asus-wmi.h +1 -0
@@ -53,6 +53,7 @@ struct quirk_entry {* and let the ACPI interrupt to send out the key event. */ int no_display_toggle; +u32 xusb2pr;bool (*i8042_filter)(unsigned char data,unsigned char str,struct serio *serio);
Greg Kroah-Hartman
maintainerPATCH 147/152 tools/power turbostat: decode Baytrail CC6 and MC6 demotion configuration
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Len Brown <[email protected]>
[ Upstream commit 71616c8e936a6dd541f0627d7bf4ff09971d8ccb ]
with --debug, see:
cpu0: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x00000000 (DISable-CC6-Demotion)
cpu0: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x00000000 (DISable-MC6-Demotion)
Note that the hardware default is to enable demotion, and Linux started clearing these registers in 3.17.
--- tools/power/x86/turbostat/turbostat.c | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)
tools/power/x86/turbostat/turbostat.c +42 -0
@@ -2951,6 +2951,27 @@ int has_snb_msrs(unsigned int family, un }/* +* SLV client has supporet for unique MSRs: +* +* MSR_CC6_DEMOTION_POLICY_CONFIG +* MSR_MC6_DEMOTION_POLICY_CONFIG +*/ + +int has_slv_msrs (unsigned int family,unsigned int model) +{ +if (!genuine_intel) +return 0 ; + +switch (model) { +case INTEL_FAM6_ATOM_SILVERMONT1 : +case INTEL_FAM6_ATOM_MERRIFIELD : +case INTEL_FAM6_ATOM_MOOREFIELD : +return 1 ; + } +return 0 ; +} + +/* * HSW adds support for additional MSRs: * * MSR_PKG_C8_RESIDENCY 0x00000630
@@ -3179,6 +3200,24 @@ void decode_misc_pwr_mgmt_msr(void) msr & (1 <<0 ) ?"DIS" :"EN" , msr & (1 << 1) ? "EN" : "DIS"); } +/* +* Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG +* +* This MSRs are present on Silvermont processors, +* Intel Atom processor E3000 series (Baytrail), and friends. +*/ +void decode_c6_demotion_policy_msr (void ) +{ +unsigned long long msr; + +if (!get_msr (base_cpu,MSR_CC6_DEMOTION_POLICY_CONFIG , &msr)) +fprintf (outf,"cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n" , + base_cpu, msr, msr & (1 <<0 ) ?"EN" :"DIS" ); + +if (!get_msr (base_cpu,MSR_MC6_DEMOTION_POLICY_CONFIG , &msr)) +fprintf (outf,"cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n" , + base_cpu, msr, msr & (1 <<0 ) ?"EN" :"DIS" ); +}void process_cpuid () {
@@ -3360,6 +3399,9 @@ void process_cpuid()if (debug)decode_misc_pwr_mgmt_msr (); +if (debug &&has_slv_msrs (family, model)) +decode_c6_demotion_policy_msr (); +rapl_probe (family, model);perf_limit_reasons_probe (family, model);
Greg Kroah-Hartman
maintainerPATCH 148/152 tools/power turbostat: dump Atom P-states correctly
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Len Brown <[email protected]>
[ Upstream commit 0f7887c49b0c454aef9936a6eadabe1c91b5af55 ]
Turbostat dumps MSR_TURBO_RATIO_LIMIT on Core Architecture. But Atom Architecture uses MSR_ATOM_CORE_RATIOS and MSR_ATOM_CORE_TURBO_RATIOS.
--- tools/power/x86/turbostat/turbostat.c | 103 +++++++++++++++++++++++++++------- 1 file changed, 82 insertions(+), 21 deletions(-)
tools/power/x86/turbostat/turbostat.c +82 -21
@@ -1470,6 +1470,54 @@ dump_nhm_turbo_ratio_limits(void) }static void +dump_atom_turbo_ratio_limits (void ) +{ +unsigned long long msr; +unsigned int ratio; + +get_msr (base_cpu,MSR_ATOM_CORE_RATIOS , &msr); +fprintf (outf,"cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n" , base_cpu, msr &0xFFFFFFFF ); + + ratio = (msr >>0 ) &0x3F ; +if (ratio) +fprintf (outf,"%d * %.1f = %.1f MHz minimum operating frequency\n" , + ratio, bclk, ratio * bclk); + + ratio = (msr >>8 ) &0x3F ; +if (ratio) +fprintf (outf,"%d * %.1f = %.1f MHz low frequency mode (LFM)\n" , + ratio, bclk, ratio * bclk); + + ratio = (msr >>16 ) &0x3F ; +if (ratio) +fprintf (outf,"%d * %.1f = %.1f MHz base frequency\n" , + ratio, bclk, ratio * bclk); + +get_msr (base_cpu,MSR_ATOM_CORE_TURBO_RATIOS , &msr); +fprintf (outf,"cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n" , base_cpu, msr &0xFFFFFFFF ); + + ratio = (msr >>24 ) &0x3F ; +if (ratio) +fprintf (outf,"%d * %.1f = %.1f MHz max turbo 4 active cores\n" , + ratio, bclk, ratio * bclk); + + ratio = (msr >>16 ) &0x3F ; +if (ratio) +fprintf (outf,"%d * %.1f = %.1f MHz max turbo 3 active cores\n" , + ratio, bclk, ratio * bclk); + + ratio = (msr >>8 ) &0x3F ; +if (ratio) +fprintf (outf,"%d * %.1f = %.1f MHz max turbo 2 active cores\n" , + ratio, bclk, ratio * bclk); + + ratio = (msr >>0 ) &0x3F ; +if (ratio) +fprintf (outf,"%d * %.1f = %.1f MHz max turbo 1 active core\n" , + ratio, bclk, ratio * bclk); +} + +static void dump_knl_turbo_ratio_limits (void ) {const unsigned int buckets_no =7 ;
@@ -2230,8 +2278,32 @@ int probe_nhm_msrs(unsigned int family, has_base_hz =1 ;return 1 ; } +/* +* SLV client has supporet for unique MSRs: +* +* MSR_CC6_DEMOTION_POLICY_CONFIG +* MSR_MC6_DEMOTION_POLICY_CONFIG +*/ + +int has_slv_msrs (unsigned int family,unsigned int model) +{ +if (!genuine_intel) +return 0 ; + +switch (model) { +case INTEL_FAM6_ATOM_SILVERMONT1 : +case INTEL_FAM6_ATOM_MERRIFIELD : +case INTEL_FAM6_ATOM_MOOREFIELD : +return 1 ; + } +return 0 ; +} +int has_nhm_turbo_ratio_limit (unsigned int family,unsigned int model) { +if (has_slv_msrs (family, model)) +return 0 ; +switch (model) {/* Nehalem compatible, but do not include turbo-ratio limit support */ case 0x2E :/* Nehalem-EX Xeon - Beckton */
@@ -2242,6 +2314,13 @@ int has_nhm_turbo_ratio_limit(unsigned ireturn 1 ; } } +int has_atom_turbo_ratio_limit (unsigned int family,unsigned int model) +{ +if (has_slv_msrs (family, model)) +return 1 ; + +return 0 ; +}int has_ivt_turbo_ratio_limit (unsigned int family,unsigned int model) {if (!genuine_intel)
@@ -2337,6 +2416,9 @@ dump_cstate_pstate_config_info(unsignedif (has_nhm_turbo_ratio_limit (family, model))dump_nhm_turbo_ratio_limits (); +if (has_atom_turbo_ratio_limit (family, model)) +dump_atom_turbo_ratio_limits (); +if (has_knl_turbo_ratio_limit (family, model))dump_knl_turbo_ratio_limits ();
@@ -2948,27 +3030,6 @@ int has_snb_msrs(unsigned int family, unreturn 1 ; }return 0 ; -} - -/* -* SLV client has supporet for unique MSRs: -* -* MSR_CC6_DEMOTION_POLICY_CONFIG -* MSR_MC6_DEMOTION_POLICY_CONFIG -*/ - -int has_slv_msrs (unsigned int family,unsigned int model) -{ -if (!genuine_intel) -return 0 ; - -switch (model) { -case INTEL_FAM6_ATOM_SILVERMONT1 : -case INTEL_FAM6_ATOM_MERRIFIELD : -case INTEL_FAM6_ATOM_MOOREFIELD : -return 1 ; - } -return 0 ; }/*
Greg Kroah-Hartman
maintainerPATCH 149/152 x86/reboot/quirks: Add ASUS EeeBook X205TA reboot quirk
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Matjaz Hegedic <[email protected]>
[ Upstream commit 90b28ded88dda8bea82b4a86923e73ba0746d884 ]
Without the parameter reboot=a, ASUS EeeBook X205TA will hang when it should reboot.
This adds the appropriate quirk, thus fixing the problem.
--- arch/x86/kernel/reboot.c | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/x86/kernel/reboot.c +8 -0
@@ -223,6 +223,14 @@ static struct dmi_system_id __initdata r DMI_MATCH(DMI_BOARD_NAME, "P4S800"), }, }, + { /* Handle problems with rebooting on ASUS EeeBook X205TA */ + .callback = set_acpi_reboot, + .ident = "ASUS EeeBook X205TA", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), + DMI_MATCH(DMI_PRODUCT_NAME, "X205TAW"), + }, + },/* Certec */ {/* Handle problems with rebooting on Certec BPC600 */
Greg Kroah-Hartman
maintainerPATCH 150/152 x86/reboot/quirks: Add ASUS EeeBook X205TA/W reboot quirk
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Matjaz Hegedic <[email protected]>
[ Upstream commit 3b3e78552d3077ec70d2640e629e07e3ab416a6a ]
Without the parameter reboot=a, ASUS EeeBook X205TA/W will hang when it should reboot. This adds the appropriate quirk, thus fixing the problem.
--- arch/x86/kernel/reboot.c | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/x86/kernel/reboot.c +8 -0
@@ -231,6 +231,14 @@ static struct dmi_system_id __initdata r DMI_MATCH(DMI_PRODUCT_NAME, "X205TAW"), }, }, + { /* Handle problems with rebooting on ASUS EeeBook X205TAW */ + .callback = set_acpi_reboot, + .ident = "ASUS EeeBook X205TAW", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), + DMI_MATCH(DMI_PRODUCT_NAME, "X205TAW"), + }, + },/* Certec */ {/* Handle problems with rebooting on Certec BPC600 */
Greg Kroah-Hartman
maintainerPATCH 151/152 usb-storage: Add ignore-residue quirk for Initio INIC-3619
In reply to Greg Kroah-Hartman4.9-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tobias Jakobi <[email protected]>
[ Upstream commit d595259fbb7a7afed241b1afb2c4fe4b47de47fa ]
This USB-SATA bridge chip is used in a StarTech enclosure for optical drives.
Without the quirk MakeMKV fails during the key exchange with an installed BluRay drive:
Quoted 2 lines
Error 'Scsi error - ILLEGAL REQUEST:COPY PROTECTION KEY EXCHANGE FAILURE - KEY NOT ESTABLISHED' occurred while issuing SCSI command AD010..080002400 to device 'SG:dev_11:2'
--- drivers/usb/storage/unusual_devs.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
drivers/usb/storage/unusual_devs.h +14 -0
@@ -2071,6 +2071,20 @@ UNUSUAL_DEV( 0x1370, 0x6828, 0x0110, 0x USB_SC_DEVICE, USB_PR_DEVICE, NULL, US_FL_IGNORE_RESIDUE ), +/* +* Reported by Tobias Jakobi <[email protected]> +* The INIC-3619 bridge is used in the StarTech SLSODDU33B +* SATA-USB enclosure for slimline optical drives. +* +* The quirk enables MakeMKV to properly exchange keys with +* an installed BD drive. +*/ +UNUSUAL_DEV (0x13fd ,0x3609 ,0x0209 ,0x0209 , +"Initio Corporation" , +"INIC-3619" , +USB_SC_DEVICE ,USB_PR_DEVICE ,NULL , +US_FL_IGNORE_RESIDUE ), +/* Reported by Qinglin Ye <[email protected]> */ UNUSUAL_DEV( 0x13fe, 0x3600, 0x0100, 0x0100, "Kingston",