ARM/dma: pl08x: pass reasonable memcpy settings
Subsystems (8)
PATCH 1/6 ARM/dma: pl08x: pass reasonable memcpy settings
We cannot use bits from configuration registers as API between platforms and driver like this, abstract it out to two enums and mimic the stuff passed as device tree data.
This is done to make it possible for the driver to generate the ccfg word on-the-fly so we can support more PL08x derivatives.
---
ARM SoC folks: I'd like your ACK on this eventually, it needs to go through the DMA engine tree with the patches following this one.
--- arch/arm/mach-lpc32xx/phy3250.c | 3 + arch/arm/mach-s3c64xx/pl080.c | 28 +++------ arch/arm/mach-spear/spear3xx.c | 14 ++--- arch/arm/mach-spear/spear6xx.c | 14 ++--- drivers/dma/amba-pl08x.c | 131 ++++++++++++++++++++++++++++------------ include/linux/amba/pl08x.h | 30 +++++++-- 6 files changed, 138 insertions(+), 82 deletions(-)
arch/arm/mach-lpc32xx/phy3250.c +3 -0
@@ -137,6 +137,9 @@ static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) }static struct pl08x_platform_data pl08x_pd = { +/* Some reasonable memcpy defaults */ + .memcpy_burst_size =PL08X_BURST_SZ_256 , + .memcpy_bus_width =PL08X_BUS_WIDTH_32_BITS , .slave_channels = &pl08x_slave_channels[0 ], .num_slave_channels =ARRAY_SIZE (pl08x_slave_channels), .get_xfer_signal = pl08x_get_signal,
arch/arm/mach-s3c64xx/pl080.c +8 -20
@@ -137,16 +137,10 @@ static const struct dma_slave_map s3c64xx_dma0_slave_map[] = { };struct pl08x_platform_data s3c64xx_dma0_plat_data = { - .memcpy_channel = { - .bus_id ="memcpy" , - .cctl_memcpy = - (PL080_BSIZE_4 <<PL080_CONTROL_SB_SIZE_SHIFT | -PL080_BSIZE_4 <<PL080_CONTROL_DB_SIZE_SHIFT | -PL080_WIDTH_32BIT <<PL080_CONTROL_SWIDTH_SHIFT | -PL080_WIDTH_32BIT <<PL080_CONTROL_DWIDTH_SHIFT | -PL080_CONTROL_PROT_BUFF |PL080_CONTROL_PROT_CACHE | -PL080_CONTROL_PROT_SYS ), - }, + .memcpy_burst_size =PL08X_BURST_SZ_4 , + .memcpy_bus_width =PL08X_BUS_WIDTH_32_BITS , + .memcpy_prot_buff = true, + .memcpy_prot_cache = true, .lli_buses =PL08X_AHB1 , .mem_buses =PL08X_AHB1 , .get_xfer_signal = pl08x_get_xfer_signal,
@@ -238,16 +232,10 @@ static const struct dma_slave_map s3c64xx_dma1_slave_map[] = { };struct pl08x_platform_data s3c64xx_dma1_plat_data = { - .memcpy_channel = { - .bus_id ="memcpy" , - .cctl_memcpy = - (PL080_BSIZE_4 <<PL080_CONTROL_SB_SIZE_SHIFT | -PL080_BSIZE_4 <<PL080_CONTROL_DB_SIZE_SHIFT | -PL080_WIDTH_32BIT <<PL080_CONTROL_SWIDTH_SHIFT | -PL080_WIDTH_32BIT <<PL080_CONTROL_DWIDTH_SHIFT | -PL080_CONTROL_PROT_BUFF |PL080_CONTROL_PROT_CACHE | -PL080_CONTROL_PROT_SYS ), - }, + .memcpy_burst_size =PL08X_BURST_SZ_4 , + .memcpy_bus_width =PL08X_BUS_WIDTH_32_BITS , + .memcpy_prot_buff = true, + .memcpy_prot_cache = true, .lli_buses =PL08X_AHB1 , .mem_buses =PL08X_AHB1 , .get_xfer_signal = pl08x_get_xfer_signal,
arch/arm/mach-spear/spear3xx.c +4 -10
@@ -44,16 +44,10 @@ struct pl022_ssp_controller pl022_plat_data = {/* dmac device registration */ struct pl08x_platform_data pl080_plat_data = { - .memcpy_channel = { - .bus_id ="memcpy" , - .cctl_memcpy = - (PL080_BSIZE_16 <<PL080_CONTROL_SB_SIZE_SHIFT | \ -PL080_BSIZE_16 <<PL080_CONTROL_DB_SIZE_SHIFT | \ -PL080_WIDTH_32BIT <<PL080_CONTROL_SWIDTH_SHIFT | \ -PL080_WIDTH_32BIT <<PL080_CONTROL_DWIDTH_SHIFT | \ -PL080_CONTROL_PROT_BUFF |PL080_CONTROL_PROT_CACHE | \ -PL080_CONTROL_PROT_SYS ), - }, + .memcpy_burst_size =PL08X_BURST_SZ_16 , + .memcpy_bus_width =PL08X_BUS_WIDTH_32_BITS , + .memcpy_prot_buff = true, + .memcpy_prot_cache = true, .lli_buses =PL08X_AHB1 , .mem_buses =PL08X_AHB1 , .get_xfer_signal = pl080_get_signal,
arch/arm/mach-spear/spear6xx.c +4 -10
@@ -322,16 +322,10 @@ static struct pl08x_channel_data spear600_dma_info[] = { };static struct pl08x_platform_data spear6xx_pl080_plat_data = { - .memcpy_channel = { - .bus_id ="memcpy" , - .cctl_memcpy = - (PL080_BSIZE_16 <<PL080_CONTROL_SB_SIZE_SHIFT | \ -PL080_BSIZE_16 <<PL080_CONTROL_DB_SIZE_SHIFT | \ -PL080_WIDTH_32BIT <<PL080_CONTROL_SWIDTH_SHIFT | \ -PL080_WIDTH_32BIT <<PL080_CONTROL_DWIDTH_SHIFT | \ -PL080_CONTROL_PROT_BUFF |PL080_CONTROL_PROT_CACHE | \ -PL080_CONTROL_PROT_SYS ), - }, + .memcpy_burst_size =PL08X_BURST_SZ_16 , + .memcpy_bus_width =PL08X_BUS_WIDTH_32_BITS , + .memcpy_prot_buff = true, + .memcpy_prot_cache = true, .lli_buses =PL08X_AHB1 , .mem_buses =PL08X_AHB1 , .get_xfer_signal = pl080_get_signal,
drivers/dma/amba-pl08x.c +93 -38
194 lines not on this page · raw message
include/linux/amba/pl08x.h +26 -4
@@ -47,8 +47,6 @@ enum {* devices with static assignments * @muxval: a number usually used to poke into some mux regiser to * mux in the signal to this channel -* @cctl_memcpy: options for the channel control register for memcpy -* *** not used for slave channels *** * @addr: source/target address in physical memory for this DMA channel, * can be the address of a FIFO register for burst requests for example. * This can be left undefined if the PrimeCell API is used for configuring
@@ -63,12 +61,28 @@ struct pl08x_channel_data {int min_signal;int max_signal;u32 muxval; -u32 cctl_memcpy;dma_addr_t addr;bool single;u8 periph_buses; }; +enum pl08x_burst_size { +PL08X_BURST_SZ_1 , +PL08X_BURST_SZ_4 , +PL08X_BURST_SZ_8 , +PL08X_BURST_SZ_16 , +PL08X_BURST_SZ_32 , +PL08X_BURST_SZ_64 , +PL08X_BURST_SZ_128 , +PL08X_BURST_SZ_256 , +}; + +enum pl08x_bus_width { +PL08X_BUS_WIDTH_8_BITS , +PL08X_BUS_WIDTH_16_BITS , +PL08X_BUS_WIDTH_32_BITS , +}; +/** * struct pl08x_platform_data - the platform configuration for the PL08x * PrimeCells.
@@ -76,6 +90,11 @@ struct pl08x_channel_data {* platform, all inclusive, including multiplexed channels. The available * physical channels will be multiplexed around these signals as they are * requested, just enumerate all possible channels. +* @num_slave_channels: number of elements in the slave channel array +* @memcpy_burst_size: the appropriate burst size for memcpy operations +* @memcpy_bus_width: memory bus width +* @memcpy_prot_buff: whether memcpy DMA is bufferable +* @memcpy_prot_cache: whether memcpy DMA is cacheable * @get_xfer_signal: request a physical signal to be used for a DMA transfer * immediately: if there is some multiplexing or similar blocking the use * of the channel the transfer can be denied by returning less than zero,
@@ -90,7 +109,10 @@ struct pl08x_channel_data {struct pl08x_platform_data {struct pl08x_channel_data *slave_channels;unsigned int num_slave_channels; -struct pl08x_channel_data memcpy_channel; +enum pl08x_burst_size memcpy_burst_size; +enum pl08x_bus_width memcpy_bus_width; +bool memcpy_prot_buff; +bool memcpy_prot_cache;int (*get_xfer_signal)(const struct pl08x_channel_data *);void (*put_xfer_signal)(const struct pl08x_channel_data *,int );u8 lli_buses;
Signature · 1 line
2.9.3
PATCH 2/6 dma: pl08x: Add Faraday FTDMAC020 to compatible list
This augments the PL08x bindings to include the Faraday Technology FTDMAC020 DMA engine, as it is clearly a derivative of the PL08x PrimeCell. Also specify that it needs the special peripheral ID specified to work properly.
---
Seeking a DT maintainer ACK on this.
--- Documentation/devicetree/bindings/dma/arm-pl08x.txt | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/dma/arm-pl08x.txt +7 -2
@@ -3,6 +3,11 @@ Required properties: - compatible: "arm,pl080", "arm,primecell"; "arm,pl081", "arm,primecell"; + "faraday,ftdmac020", "arm,primecell" +- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded + in the hardware and must be specified here as <0x0003b080>. This number + follows the PrimeCell standard numbering using the JEP106 vendor code 0x38 + for Faraday Technology. - reg: Address range of the PL08x registers - interrupt: The PL08x interrupt number - clocks: The clock running the IP core clock
@@ -20,8 +25,8 @@ Optional properties: - dma-requests: contains the total number of DMA requests supported by the DMAC - memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32 64, 128 or 256 bytes are legal values -- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal - values +- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal + values, the Faraday FTDMAC020 can also accept 64 bits Clients Required properties:
Signature · 1 line
2.9.3
Rob Herring
maintainerPATCH 2/6 dma: pl08x: Add Faraday FTDMAC020 to compatible list
Quoted 5 lines · Linus Walleij
This augments the PL08x bindings to include the Faraday Technology FTDMAC020 DMA engine, as it is clearly a derivative of the PL08x PrimeCell. Also specify that it needs the special peripheral ID specified to work properly.
Quoted 7 lines
Cc devicetree at vger.kernel.orgSigned-off-by Linus Walleij <[email protected]>---
Seeking a DT maintainer ACK on this.--- Documentation/devicetree/bindings/dma/arm-pl08x.txt | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
PATCH 3/6 dma: pl08x: Make slave engine optional
In reply to Linus WalleijIf the vendor data does not specify any signals, we do not have to support slave DMA. Make the registration of the slave DMA engine optional, so we can use this for the FTDMAC020 in the Gemini that only has memcpy support.
--- drivers/dma/amba-pl08x.c | 128 +++++++++++++++++++++++++++++------------------ 1 file changed, 78 insertions(+), 50 deletions(-)
drivers/dma/amba-pl08x.c +78 -50
@@ -253,8 +253,9 @@ struct pl08x_dma_chan {/** * struct pl08x_driver_data - the local state holder for the PL08x -* @slave: slave engine for this instance +* @slave: optional slave engine for this instance * @memcpy: memcpy engine for this instance +* @has_slave: the PL08x has a slave engine (routed signals) * @base: virtual memory base (remapped) for the PL08x * @adev: the corresponding AMBA (PrimeCell) bus entry * @vd: vendor data for this PL08x variant
@@ -269,6 +270,7 @@ struct pl08x_dma_chan {struct pl08x_driver_data {struct dma_device slave;struct dma_device memcpy; +bool has_slave;void __iomem *base;struct amba_device *adev;const struct vendor_data *vd;
@@ -705,7 +707,7 @@ static void pl08x_phy_free(struct pl08x_dma_chan *plchan)break ; } -if (!next) { +if (!next && pl08x->has_slave) {list_for_each_entry (p, &pl08x->slave.channels, vc.chan.device_node)if (p->state ==PL08X_CHAN_WAITING ) { next = p;
@@ -2085,12 +2087,15 @@ static int pl08x_debugfs_show(struct seq_file *s, void *data) pl08x_state_str(chan->state)); } -seq_printf (s,"\nPL08x virtual slave channels:\n" ); -seq_printf (s,"CHANNEL:\tSTATE:\n" ); -seq_printf (s,"--------\t------\n" ); -list_for_each_entry (chan, &pl08x->slave.channels, vc.chan.device_node) { -seq_printf (s,"%s\t\t%s\n" , chan->name, -pl08x_state_str (chan->state)); +if (pl08x->has_slave) { +seq_printf (s,"\nPL08x virtual slave channels:\n" ); +seq_printf (s,"CHANNEL:\tSTATE:\n" ); +seq_printf (s,"--------\t------\n" ); +list_for_each_entry (chan, &pl08x->slave.channels, + vc.chan.device_node) { +seq_printf (s,"%s\t\t%s\n" , chan->name, +pl08x_state_str (chan->state)); + } }return 0 ;
@@ -2128,6 +2133,10 @@ static struct dma_chan *pl08x_find_chan_id(struct pl08x_driver_data *pl08x, {struct pl08x_dma_chan *chan; +/* Trying to get a slave channel from something with no slave support */ +if (!pl08x->has_slave) +return NULL ; +list_for_each_entry (chan, &pl08x->slave.channels, vc.chan.device_node) {if (chan->signal == id)return &chan->vc.chan;
@@ -2265,20 +2274,24 @@ static int pl08x_of_probe(struct amba_device *adev,* for a device and have it's AHB interfaces set up at * translation time. */ - chanp =devm_kcalloc (&adev->dev, - pl08x->vd->signals, -sizeof (struct pl08x_channel_data ), -GFP_KERNEL ); -if (!chanp) -return -ENOMEM ; +if (pl08x->vd->signals) { + chanp =devm_kcalloc (&adev->dev, + pl08x->vd->signals, +sizeof (struct pl08x_channel_data ), +GFP_KERNEL ); +if (!chanp) +return -ENOMEM ; - pd->slave_channels = chanp; -for (i =0 ; i < pl08x->vd->signals; i++) { -/* chanp->periph_buses will be assigned at translation */ - chanp->bus_id =kasprintf (GFP_KERNEL ,"slave%d" , i); - chanp++; + pd->slave_channels = chanp; +for (i =0 ; i < pl08x->vd->signals; i++) { +/* +* chanp->periph_buses will be assigned at translation +*/ + chanp->bus_id =kasprintf (GFP_KERNEL ,"slave%d" , i); + chanp++; + } + pd->num_slave_channels = pl08x->vd->signals; } - pd->num_slave_channels = pl08x->vd->signals; pl08x->pd = pd;
@@ -2340,24 +2353,34 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) pl08x->memcpy.directions =BIT (DMA_MEM_TO_MEM ); pl08x->memcpy.residue_granularity =DMA_RESIDUE_GRANULARITY_SEGMENT ; -/* Initialize slave engine */ -dma_cap_set (DMA_SLAVE , pl08x->slave.cap_mask); -dma_cap_set (DMA_CYCLIC , pl08x->slave.cap_mask); - pl08x->slave.dev = &adev->dev; - pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; - pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; - pl08x->slave.device_tx_status = pl08x_dma_tx_status; - pl08x->slave.device_issue_pending = pl08x_issue_pending; - pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; - pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic; - pl08x->slave.device_config = pl08x_config; - pl08x->slave.device_pause = pl08x_pause; - pl08x->slave.device_resume = pl08x_resume; - pl08x->slave.device_terminate_all = pl08x_terminate_all; - pl08x->slave.src_addr_widths =PL80X_DMA_BUSWIDTHS ; - pl08x->slave.dst_addr_widths =PL80X_DMA_BUSWIDTHS ; - pl08x->slave.directions =BIT (DMA_DEV_TO_MEM ) |BIT (DMA_MEM_TO_DEV ); - pl08x->slave.residue_granularity =DMA_RESIDUE_GRANULARITY_SEGMENT ; +/* +* Initialize slave engine, if the block has no signals, that means +* we have no slave support. +*/ +if (vd->signals) { + pl08x->has_slave = true; +dma_cap_set (DMA_SLAVE , pl08x->slave.cap_mask); +dma_cap_set (DMA_CYCLIC , pl08x->slave.cap_mask); + pl08x->slave.dev = &adev->dev; + pl08x->slave.device_free_chan_resources = + pl08x_free_chan_resources; + pl08x->slave.device_prep_dma_interrupt = + pl08x_prep_dma_interrupt; + pl08x->slave.device_tx_status = pl08x_dma_tx_status; + pl08x->slave.device_issue_pending = pl08x_issue_pending; + pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; + pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic; + pl08x->slave.device_config = pl08x_config; + pl08x->slave.device_pause = pl08x_pause; + pl08x->slave.device_resume = pl08x_resume; + pl08x->slave.device_terminate_all = pl08x_terminate_all; + pl08x->slave.src_addr_widths =PL80X_DMA_BUSWIDTHS ; + pl08x->slave.dst_addr_widths =PL80X_DMA_BUSWIDTHS ; + pl08x->slave.directions = +BIT (DMA_DEV_TO_MEM ) |BIT (DMA_MEM_TO_DEV ); + pl08x->slave.residue_granularity = +DMA_RESIDUE_GRANULARITY_SEGMENT ; + }/* Get the platform data */ pl08x->pd =dev_get_platdata (&adev->dev);
@@ -2465,13 +2488,15 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) }/* Register slave channels */ - ret =pl08x_dma_init_virtual_channels (pl08x, &pl08x->slave, - pl08x->pd->num_slave_channels, true); -if (ret <0 ) { -dev_warn (&pl08x->adev->dev, -"%s failed to enumerate slave channels - %d\n" , - __func__, ret); - goto out_no_slave; +if (pl08x->has_slave) { + ret =pl08x_dma_init_virtual_channels (pl08x, &pl08x->slave, + pl08x->pd->num_slave_channels, true); +if (ret <0 ) { +dev_warn (&pl08x->adev->dev, +"%s failed to enumerate slave channels - %d\n" , + __func__, ret); + goto out_no_slave; + } } ret =dma_async_device_register (&pl08x->memcpy);
@@ -2482,12 +2507,14 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) goto out_no_memcpy_reg; } - ret =dma_async_device_register (&pl08x->slave); -if (ret) { -dev_warn (&pl08x->adev->dev, +if (pl08x->has_slave) { + ret =dma_async_device_register (&pl08x->slave); +if (ret) { +dev_warn (&pl08x->adev->dev,"%s failed to register slave as an async device - %d\n" , __func__, ret); - goto out_no_slave_reg; + goto out_no_slave_reg; + } }amba_set_drvdata (adev, pl08x);
@@ -2501,7 +2528,8 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) out_no_slave_reg:dma_async_device_unregister (&pl08x->memcpy); out_no_memcpy_reg: -pl08x_free_virtual_channels (&pl08x->slave); +if (pl08x->has_slave) +pl08x_free_virtual_channels (&pl08x->slave); out_no_slave:pl08x_free_virtual_channels (&pl08x->memcpy); out_no_memcpy:
Signature · 1 line
2.9.3
PATCH 4/6 dma: pl08x: Add support for Faraday Technology FTDMAC020
In reply to Linus WalleijAfter reading the specs for the Faraday Technology FTDMAC020 found in the Gemini platform, it becomes pretty evident that this is just another PL08x derivative, and should be handled like such by simply extending the existing PL08x driver to handle the quirks in this hardware.
This patch makes memcpy work and has been tested on the Gemini and also regression-tested on the Nomadik NHK15 using dmatest with 10 threads per channel without a hinch for hours.
I have not implemented slave DMA in those codepaths, because this device (Gemini) does not use slave DMA, and it seems like devices using FTDMAC020 for device DMA have a slightly different register layout so some real hardware is needed to proceed with this. I left some FIXME etc in the code for this.
I had to do some refactorings of some helper functions, but I have not split those into separate patches because these refactorings do not make much sense without the increased complexity of handling the FTDMAC020.
The DMA test would hang the platform on me on the Gemini after a few thousand iterations, however after turning of the caches the problem immediately disappeared and I could run the DMA engine with 10 threads pers physical channel for days in a row without a crash. I think there is no problem with the DMA driver: instead it is something fishy in the FA526 cache handling code that get pretty heavily exercised by the DMA engine and we need to go and fix that instead.
--- drivers/dma/Kconfig | 6 +- drivers/dma/amba-pl08x.c | 767 ++++++++++++++++++++++++++++++++++++--------- include/linux/amba/pl080.h | 83 ++++- 3 files changed, 698 insertions(+), 158 deletions(-)
drivers/dma/Kconfig +4 -2
@@ -62,8 +62,10 @@ config AMBA_PL08X select DMA_ENGINE select DMA_VIRTUAL_CHANNELS help - Platform has a PL08x DMAC device - which can provide DMA engine support + Say yes if your platform has a PL08x DMAC device which can + provide DMA engine support. This includes the original ARM + PL080 and PL081, Samsungs PL080 derivative and Faraday + Technology's FTDMAC020 PL080 derivative. config AMCC_PPC440SPE_ADMA tristate "AMCC PPC440SPe ADMA support"
drivers/dma/amba-pl08x.c +612 -155
1,074 lines not on this page · raw message
include/linux/amba/pl080.h +82 -1
101 lines not on this page · raw message
Signature · 1 line
2.9.3
PATCH 4/6 dma: pl08x: Add support for Faraday Technology FTDMAC020
Quoted 1 line · Linus Walleij
+#define
FTDMAC020_CH_CSR_FIFOTH_MSK(0x7<< 24)
IIUC we can have a GENMASK(27, 25), won't that be a bit better here and other places?
Quoted 1 line
+#define
FTDMAC020_CH_CSR_FIFOTH_SHIFT(24)
and you may use ffs(FTDMAC020_CH_CSR_FIFOTH_MSK) or keep a shift define
Quoted 69 lines
include/linux/amba/pl080.h +63
-0+#define FTDMAC020_CH_CSR_CHPR1_MSK (0x3 << 22) +#define FTDMAC020_CH_CSR_PROT3 BIT(21) +#define FTDMAC020_CH_CSR_PROT2 BIT(20) +#define FTDMAC020_CH_CSR_PROT1 BIT(19) +#define FTDMAC020_CH_CSR_SRC_SIZE_MSK (0x7 << 16) +#define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT (16) +#define FTDMAC020_CH_CSR_ABT BIT(15) +#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK (0x7 << 11) +#define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11) +#define FTDMAC020_CH_CSR_DST_WIDTH_MSK (0x7 << 8) +#define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT (8) +#define FTDMAC020_CH_CSR_MODE BIT(7) +/* 00 = increase, 01 = decrease, 10 = fix */ +#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK (0x3 << 5) +#define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT (5) +#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK (0x3 << 3) +#define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT (3) +#define FTDMAC020_CH_CSR_SRC_SEL BIT(2) +#define FTDMAC020_CH_CSR_DST_SEL BIT(1) +#define FTDMAC020_CH_CSR_EN BIT(0) + +/* FIFO threshold setting */ +#define FTDMAC020_CH_CSR_FIFOTH_1 (0x0) +#define FTDMAC020_CH_CSR_FIFOTH_2 (0x1) +#define FTDMAC020_CH_CSR_FIFOTH_4 (0x2) +#define FTDMAC020_CH_CSR_FIFOTH_8 (0x3) +#define FTDMAC020_CH_CSR_FIFOTH_16 (0x4) +/* The FTDMAC020 supports 64bit wide transfers */ +#define FTDMAC020_WIDTH_64BIT (0x3) +/* Address can be increased, decreased or fixed */ +#define FTDMAC020_CH_CSR_SRCAD_CTL_INC (0x0) +#define FTDMAC020_CH_CSR_SRCAD_CTL_DEC (0x1) +#define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED (0x2) + +#define FTDMAC020_CH_CFG_LLP_CNT_MASK (0xf << 16) +#define FTDMAC020_CH_CFG_LLP_CNT_SHIFT (16) +#define FTDMAC020_CH_CFG_BUSY BIT(8) +#define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2) +#define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1) +#define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0) + +/* Inside the LLIs, the applicable CSR fields are mapped differently */ +#define FTDMAC020_LLI_TC_MSK BIT(28) +#define FTDMAC020_LLI_SRC_WIDTH_MSK (0x7 << 25) +#define FTDMAC020_LLI_SRC_WIDTH_SHIFT (25) +#define FTDMAC020_LLI_DST_WIDTH_MSK (0x7 << 22) +#define FTDMAC020_LLI_DST_WIDTH_SHIFT (22) +#define FTDMAC020_LLI_SRCAD_CTL_MSK (0x3 << 20) +#define FTDMAC020_LLI_SRCAD_CTL_SHIFT (20) +#define FTDMAC020_LLI_DSTAD_CTL_MSK (0x3 << 18) +#define FTDMAC020_LLI_DSTAD_CTL_SHIFT (18) +#define FTDMAC020_LLI_SRC_SEL BIT(17) +#define FTDMAC020_LLI_DST_SEL BIT(16) +#define FTDMAC020_LLI_TRANSFER_SIZE_MASK (0xfff << 0) +#define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT (0) + +#define FTDMAC020_CFG_LLP_CNT_MASK (0x0f << 16) +#define FTDMAC020_CFG_LLP_CNT_SHIFT (16) +#define FTDMAC020_CFG_BUSY BIT(8) +#define FTDMAC020_CFG_INT_ABT_MSK BIT(2) +#define FTDMAC020_CFG_INT_ERR_MSK BIT(1) +#define FTDMAC020_CFG_INT_TC_MSK BIT(0) +/* DMA linked list chain structure */ struct pl080_lli {Signature · 1 line
2.9.3
Signature · 1 line
~Vinod
PATCH 4/6 dma: pl08x: Add support for Faraday Technology FTDMAC020
Quoted 6 lines · Vinod Koul
Quoted 1 line · Linus Walleij
+#define
FTDMAC020_CH_CSR_FIFOTH_MSK(0x7<< 24)IIUC we can have a
GENMASK(27, 25), won't that be a bit better here and other places?
I will send an additional patch at the end of the series switching *all* of these to use GENMASK() so we keep it to one technical step per patch, OK?
Quoted 3 lines
Quoted 1 line
+#define
FTDMAC020_CH_CSR_FIFOTH_SHIFT(24)and you may use
ffs(FTDMAC020_CH_CSR_FIFOTH_MSK)or keep a shift define
I'm more convenient with the shift at least here.
ffs(DEFINE) makes me thin ffs() is a function invoked all the time even if I know very well the compiler will mangle it into a constant... just confusing for my perception.
Yours,
Linus Walleij
PATCH 4/6 dma: pl08x: Add support for Faraday Technology FTDMAC020
Quoted 11 lines · Linus Walleij
Quoted 6 lines · Vinod Koul
Quoted 1 line · Linus Walleij
+#define
FTDMAC020_CH_CSR_FIFOTH_MSK(0x7<< 24)IIUC we can have a
GENMASK(27, 25), won't that be a bit better here and other places?I will send an additional patch at the end of the series switching *all* of these to use
GENMASK()so we keep it to one technical step per patch, OK?
Sounds good to me
Quoted 10 lines
Quoted 4 lines
Quoted 2 lines
+#define
FTDMAC020_CH_CSR_FIFOTH_SHIFT(24)and you may use
ffs(FTDMAC020_CH_CSR_FIFOTH_MSK)or keep a shift defineI'm more convenient with the shift at least here.
ffs(DEFINE) makes me thin
ffs()is a function invoked all the time even if I know very well the compiler will mangle it into a constant... just confusing for my perception.
Perhaps we should have a SHIFT_MACRO(x) which would give us the shifted value from a mask value :)
Signature · 1 line
~Vinod
PATCH 5/6 ARM: gemini: select ARM_AMBA
In reply to Linus WalleijThis selects the ARM_AMBA PrimeCell bus for the Gemini so we can use the PL08x DMA engine derivative FTDMAC020 through the combined PL08x driver.
---
Vinod: this is just for context, this patch will be directed through the ARM SoC tree once the rest is done.
--- arch/arm/mach-gemini/Kconfig | 1 + 1 file changed, 1 insertion(+)
arch/arm/mach-gemini/Kconfig +1 -0
@@ -1,6 +1,7 @@ menuconfig ARCH_GEMINI bool "Cortina Systems Gemini" depends on ARCH_MULTI_V4 + select ARM_AMBA select ARM_APPENDED_DTB # Old Redboot bootloaders deployed select FARADAY_FTINTC010 select FTTMR010_TIMER
Signature · 1 line
2.9.3
PATCH 6/6 ARM: dts: Add Gemini DMA controller
In reply to Linus WalleijThis adds the Faraday Technology FTDMAC020 DMA controller to the Gemini SoC DTSI file. It is only used for memcpy work so we can activate it for all users of the chipset.
To make the PrimeCell bus work properly we need to add a summy PCLK clock, as the generic clock framework always gets compiled in on multiplatform builds.
---
Vinod: this is just for context, this patch will be directed through the ARM SoC tree once the rest is done.
--- arch/arm/boot/dts/gemini.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
arch/arm/boot/dts/gemini.dtsi +22 -0
@@ -8,6 +8,12 @@ #include <dt-bindings/gpio/gpio.h> / { + pclk: pclk at 0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + soc { #address-cells = <1>; #size-cells = <1>;
@@ -186,5 +192,21 @@ syscon = <&syscon>; status = "disabled"; }; + + dma-controller at 67000000 { + compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; + /* Faraday Technology FTDMAC020 variant */ + arm,primecell-periphid = <0x0003b080>; + reg = <0x67000000 0x1000>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + /* Bus interface AHB1 (AHB0) is totally tilted */ + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; }; };
Signature · 1 line
2.9.3
PATCH 1/6 ARM/dma: pl08x: pass reasonable memcpy settings
In reply to Linus WalleijQuoted 4 lines · Linus Walleij
We cannot use bits from configuration registers as API between platforms and driver like this, abstract it out to two enums and mimic the stuff passed as device tree data.
Quoted 8 lines
This is done to make it possible for the driver to generate the ccfg word on-the-fly so we can support more PL08x derivatives.
Cc arm at kernel.orgSigned-off-by Linus Walleij <[email protected]>---
ARM SoC folks: I'd like your ACK on this eventually, it needs to go through the DMA engine tree with the patches following this one.
-Olof
PATCH 1/6 ARM/dma: pl08x: pass reasonable memcpy settings
Quoted 8 lines · Olof Johansson
Quoted 7 lines · Linus Walleij
We cannot use bits from configuration registers as API between platforms and driver like this, abstract it out to two enums and mimic the stuff passed as device tree data.
This is done to make it possible for the driver to generate the ccfg word on-the-fly so we can support more PL08x derivatives.
Quoted 7 lines
Quoted 5 lines
Cc arm at kernel.orgSigned-off-by Linus Walleij <[email protected]>---
ARM SoC folks: I'd like your ACK on this eventually, it needs to go through the DMA engine tree with the patches following this one.Acked-by Olof Johansson <[email protected]>
Very nice cleanup!