arm64: marvell: add cryptographic engine support for 7k/8k
Subsystems (3)
v2 cover arm64: marvell: add cryptographic engine support for 7k/8k
Hi all,
This series adds support for the Inside Secure SafeXcel EIP197 cryptographic engine which can be found on Marvell Armada 7k and 8k boards. A new cryptographic engine driver is added, as well as the relevant device tree definition for the Armada 7040 DB and 8040 DB boards.
This driver needs two firmwares to work correctly. These firmware are usually used for more advanced operations than the ones supported (as of now), but we still need them to pass the data to the internal cryptographic engine.
This series was tested in various ways on both the Armada 7040 DB and the Armada 8040 DB: using the crypto framework self tests, using tcrypt and while performing various transfers with iperf on top of IPsec.
This series is based on top of v4.11-rc1, and is available on a branch (which also contains the PPv2 support for 7k/8k, to ease the process of testing IPsec): https://github.com/atenart/linux v4.11-rc1/7k8k-crypto I can rebase if needed. Patches adding device tree nodes and modifying the arm64 defconfig have been applied to the mvebu tree already.
I'd like to thank Ofer Heifetz and Igal Liberman who helped me to do this driver by adding functionalities, optimizing functions and testing (a lot).
Thanks,
Antoine
Since v1:
- Fixed two compilation issues reported by Kbuild.
- Removed all dma_to_phys() calls and used the dma addresses instead.
- Added a call to dma_set_mask_and_coherent() before calling any DMA API helper.
- Removed some DMA free functions to avoid double-freeing.
- Do not rely on sg_nents_for_len() to get the number of sg anymore.
- Added a dedicated kmalloc'ed cache to use for dma_map_single().
Antoine Tenart (3):
Documentation/bindings: Document the SafeXel cryptographic engine
driver
crypto: inside-secure: add SafeXcel EIP197 crypto engine driver
MAINTAINERS: add a maintainer for the Inside Secure crypto driver
.../bindings/crypto/inside-secure-safexcel.txt | 27 + MAINTAINERS | 6 + drivers/crypto/Kconfig | 17 + drivers/crypto/Makefile | 1 + drivers/crypto/inside-secure/Makefile | 2 + drivers/crypto/inside-secure/safexcel.c | 940 +++++++++++++++++ drivers/crypto/inside-secure/safexcel.h | 579 +++++++++++ drivers/crypto/inside-secure/safexcel_cipher.c | 555 ++++++++++ drivers/crypto/inside-secure/safexcel_hash.c | 1060 ++++++++++++++++++++ drivers/crypto/inside-secure/safexcel_ring.c | 157 +++ 10 files changed, 3344 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt create mode 100644 drivers/crypto/inside-secure/Makefile create mode 100644 drivers/crypto/inside-secure/safexcel.c create mode 100644 drivers/crypto/inside-secure/safexcel.h create mode 100644 drivers/crypto/inside-secure/safexcel_cipher.c create mode 100644 drivers/crypto/inside-secure/safexcel_hash.c create mode 100644 drivers/crypto/inside-secure/safexcel_ring.c
Signature · 1 line
2.11.0
PATCH v2 1/3 Documentation/bindings: Document the SafeXel cryptographic engine driver
The Inside Secure Safexcel cryptographic engine is found on some Marvell SoCs (7k/8k). Document the bindings used by its driver.
--- .../bindings/crypto/inside-secure-safexcel.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt
Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt new file +27 -0
@@ -0,0 +1,27 @@ +Inside Secure SafeXcel cryptographic engine + +Required properties: +- compatible: Should be "inside-secure,safexcel-eip197". +- reg: Base physical address of the engine and length of memory mapped region. +- interrupts: Interrupt numbers for the rings and engine. +- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem". + +Optional properties: +- clocks: Reference to the crypto engine clock. + +Example: + + crypto: crypto at 800000 { + compatible = "inside-secure,safexcel-eip197"; + reg = <0x800000 0x200000>; + interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", + "eip"; + clocks = <&cpm_syscon0 1 26>; + status = "disabled"; + };
Signature · 1 line
2.11.0
PATCH v2 2/3 crypto: inside-secure: add SafeXcel EIP197 crypto engine driver
In reply to Antoine TenartAdd support for Inside Secure SafeXcel EIP197 cryptographic engine, which can be found on Marvell Armada 7k and 8k boards. This driver currently implements: ecb(aes), cbc(aes), sha1, sha224, sha256 and hmac(sah1) algorithms.
Two firmwares are needed for this engine to work. Their are mostly used for more advanced operations than the ones supported (as of now), but we still need them to pass the data to the internal cryptographic engine.
--- drivers/crypto/Kconfig | 17 + drivers/crypto/Makefile | 1 + drivers/crypto/inside-secure/Makefile | 2 + drivers/crypto/inside-secure/safexcel.c | 940 +++++++++++++++++++++ drivers/crypto/inside-secure/safexcel.h | 579 +++++++++++++ drivers/crypto/inside-secure/safexcel_cipher.c | 555 +++++++++++++ drivers/crypto/inside-secure/safexcel_hash.c | 1060 ++++++++++++++++++++++++ drivers/crypto/inside-secure/safexcel_ring.c | 157 ++++ 8 files changed, 3311 insertions(+) create mode 100644 drivers/crypto/inside-secure/Makefile create mode 100644 drivers/crypto/inside-secure/safexcel.c create mode 100644 drivers/crypto/inside-secure/safexcel.h create mode 100644 drivers/crypto/inside-secure/safexcel_cipher.c create mode 100644 drivers/crypto/inside-secure/safexcel_hash.c create mode 100644 drivers/crypto/inside-secure/safexcel_ring.c
drivers/crypto/Kconfig +17 -0
@@ -619,4 +619,21 @@ config CRYPTO_DEV_BCM_SPU Secure Processing Unit (SPU). The SPU driver registers ablkcipher, ahash, and aead algorithms with the kernel cryptographic API. +config CRYPTO_DEV_SAFEXCEL + tristate "Inside Secure's SafeXcel cryptographic engine driver" + depends on HAS_DMA && OF + depends on (ARM64 && ARCH_MVEBU) || (COMPILE_TEST && 64BIT) + select CRYPTO_AES + select CRYPTO_BLKCIPHER + select CRYPTO_HASH + select CRYPTO_HMAC + select CRYPTO_SHA1 + select CRYPTO_SHA256 + select CRYPTO_SHA512 + help + This driver interfaces with the SafeXcel EIP-197 cryptographic engine + designed by Inside Secure. Select this if you want to use CBC/ECB + chain mode, AES cipher mode and SHA1/SHA224/SHA256/SHA512 hash + algorithms. + endif # CRYPTO_HW
drivers/crypto/Makefile +1 -0
@@ -36,3 +36,4 @@ obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/ obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/ obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/ +obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
drivers/crypto/inside-secure/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += crypto_safexcel.o +crypto_safexcel-objs := safexcel.o safexcel_ring.o safexcel_cipher.o safexcel_hash.o
drivers/crypto/inside-secure/safexcel.c new file +940 -0
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drivers/crypto/inside-secure/safexcel.h new file +579 -0
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drivers/crypto/inside-secure/safexcel_cipher.c new file +555 -0
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drivers/crypto/inside-secure/safexcel_hash.c new file +1060 -0
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drivers/crypto/inside-secure/safexcel_ring.c new file +157 -0
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Signature · 1 line
2.11.0
Part of the diff is not shown here. View the raw message.
PATCH v2 2/3 crypto: inside-secure: add SafeXcel EIP197 crypto engine driver
Hello
I have some minor comment below
Quoted 35 lines · Antoine Tenart
Add support for Inside Secure SafeXcel EIP197 cryptographic engine, which can be found on Marvell Armada 7k and 8k boards. This driver currently implements: ecb(aes), cbc(aes), sha1, sha224, sha256 and hmac(sah1) algorithms.
Two firmwares are needed for this engine to work. Their are mostly used for more advanced operations than the ones supported (as of now), but we still need them to pass the data to the internal cryptographic engine.
Signed-off-by Antoine Tenart <[email protected]>--- drivers/crypto/Kconfig | 17 + drivers/crypto/Makefile | 1 + drivers/crypto/inside-secure/Makefile | 2 + drivers/crypto/inside-secure/safexcel.c | 940 +++++++++++++++++++++ drivers/crypto/inside-secure/safexcel.h | 579 +++++++++++++ drivers/crypto/inside-secure/safexcel_cipher.c | 555 +++++++++++++ drivers/crypto/inside-secure/safexcel_hash.c | 1060 ++++++++++++++++++++++++ drivers/crypto/inside-secure/safexcel_ring.c | 157 ++++ 8 files changed, 3311 insertions(+) create mode 100644 drivers/crypto/inside-secure/Makefile create mode 100644 drivers/crypto/inside-secure/safexcel.c create mode 100644 drivers/crypto/inside-secure/safexcel.h create mode 100644 drivers/crypto/inside-secure/safexcel_cipher.c create mode 100644 drivers/crypto/inside-secure/safexcel_hash.c create mode 100644 drivers/crypto/inside-secure/safexcel_ring.cdrivers/crypto/Kconfig +0
-0@@ -619,4 +619,21 @@ config CRYPTO_DEV_BCM_SPU Secure Processing Unit (SPU). The SPU driver registers ablkcipher, ahash, and aead algorithms with the kernel cryptographic API.
[...]
drivers/crypto/Kconfig
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drivers/crypto/Kconfig +3
-0+ /* + * Result Descriptor Ring prepare + */
This is not preferred comment format for one line
[...]
drivers/crypto/Kconfig
Quoted 9 lines
drivers/crypto/Kconfig +9
-0+static int safexcel_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct safexcel_crypto_priv *priv; + int i, ret; + + priv = devm_kzalloc(dev, sizeof(struct safexcel_crypto_priv), + GFP_KERNEL);
sizeof(priv) is preferred as asked by checkpatch
[...]
drivers/crypto/Kconfig
Quoted 2 lines
drivers/crypto/Kconfig +2
-0+ ring_irq = devm_kzalloc(dev, sizeof(struct safexcel_ring_irq_data), + GFP_KERNEL);
same comment here
[...]
Quoted 6 lines
drivers/crypto/Kconfig +6
-0+#define EIP197_ALG_ARC4 BIT(7) +#define EIP197_ALG_AES_ECB BIT(8) +#define EIP197_ALG_AES_CBC BIT(9) +#define EIP197_ALG_AES_CTR_ICM BIT(10) +#define EIP197_ALG_AES_OFB BIT(11) +#define EIP197_ALG_AES_CFB BIT(12)
drivers/crypto/Kconfig
Quoted 10 lines
drivers/crypto/Kconfig +10
-0+#define EIP197_ALG_DES_ECB BIT(13) +#define EIP197_ALG_DES_CBC BIT(14) +#define EIP197_ALG_DES_OFB BIT(16) +#define EIP197_ALG_DES_CFB BIT(17) +#define EIP197_ALG_3DES_ECB BIT(18) +#define EIP197_ALG_3DES_CBC BIT(19) +#define EIP197_ALG_3DES_OFB BIT(21) +#define EIP197_ALG_3DES_CFB BIT(22) +#define EIP197_ALG_MD5 BIT(24) +#define EIP197_ALG_HMAC_MD5 BIT(25)
Does MD5, DES and 3DES will be added later ?
[...]
Quoted 7 lines
drivers/crypto/Kconfig +7
-0+static const u8 sha1_zero_digest[SHA1_DIGEST_SIZE] = { + 0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d, 0x32, 0x55, + 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90, 0xaf, 0xd8, 0x07, 0x09, +}; + +static const u8 sha224_zero_digest[SHA224_DIGEST_SIZE] = { + 0xd1, 0x4a, 0x02, 0x8c, 0x2a, 0x3a, 0x2b, 0xc9, 0x47, 0x61,
drivers/crypto/Kconfig
Quoted 10 lines
drivers/crypto/Kconfig +10
-0+ 0x02, 0xbb, 0x28, 0x82, 0x34, 0xc4, 0x15, 0xa2, 0xb0, 0x1f, + 0x82, 0x8e, 0xa6, 0x2a, 0xc5, 0xb3, 0xe4, 0x2f +}; + +static const u8 sha256_zero_digest[SHA256_DIGEST_SIZE] = { + 0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14, 0x9a, 0xfb, + 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24, 0x27, 0xae, 0x41, 0xe4, + 0x64, 0x9b, 0x93, 0x4c, 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, + 0xb8, 0x55 +};
Thoses structures are already defined in crypto (sha1_zero_message_hash, etc...) You can use it since you select SHAxxx in Kconfig
[...]
Quoted 20 lines
drivers/crypto/Kconfig +20
-0+static int safexcel_hmac_init_pad(struct ahash_request *areq, + unsigned int blocksize, const u8 *key, + unsigned int keylen, u8 *ipad, u8 *opad) +{ + struct safexcel_ahash_result result; + struct scatterlist sg; + int ret, i; + u8 *keydup; + + if (keylen <= blocksize) { + memcpy(ipad, key, keylen); + } else { + keydup = kmemdup(key, keylen, GFP_KERNEL); + if (!keydup) + return -ENOMEM; + + ahash_request_set_callback(areq, CRYPTO_TFM_REQ_MAY_BACKLOG, + safexcel_ahash_complete, &result); + sg_init_one(&sg, keydup, keylen); + ahash_request_set_crypt(areq, &sg, ipad, keylen);
drivers/crypto/Kconfig
Quoted 10 lines
drivers/crypto/Kconfig +10
-0+ init_completion(&result.completion); + + ret = crypto_ahash_digest(areq); + if (ret == -EINPROGRESS) { + wait_for_completion_interruptible(&result.completion); + ret = result.error; + } + + /* Avoid leaking */ + memset(keydup, 0, keylen);
It is safer to use memzero_explicit
Quoted 4 lines
drivers/crypto/Kconfig +4
-0+ kfree(keydup); + + if (ret) + return ret;
drivers/crypto/Kconfig
Quoted 10 lines
drivers/crypto/Kconfig +10
-0+ + keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(areq)); + } + + memset(ipad + keylen, 0, blocksize - keylen); + memcpy(opad, ipad, blocksize); + + for (i = 0; i < blocksize; i++) { + ipad[i] ^= 0x36; + opad[i] ^= 0x5c;
What are these constant ?
[...]
drivers/crypto/Kconfig
Quoted 8 lines
drivers/crypto/Kconfig +8
-0+static int safexcel_hmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen) +{ + struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm)); + struct safexcel_ahash_export_state istate, ostate; + int ret, i; + + ret = safexcel_hmac_setkey("safexcel-sha1", key, keylen, &istate, &ostate);
Perhaps you could use the algname instead of "safexcel-sha1"
drivers/crypto/Kconfig
Quoted 5 lines
drivers/crypto/Kconfig +5
-0+ if (ret) + return ret; + + memcpy(ctx->ipad, &istate.state, SHA1_DIGEST_SIZE); + memcpy(ctx->opad, &ostate.state, SHA1_DIGEST_SIZE);
Perhaps you could the digest_size from alg_template
[...]
Quoted 9 lines
drivers/crypto/Kconfig +9
-0+struct safexcel_alg_template safexcel_alg_sha256 = { + .type = SAFEXCEL_ALG_TYPE_AHASH, + .alg.ahash = { + .init = safexcel_sha256_init, + .update = safexcel_ahash_update, + .final = safexcel_ahash_final, + .finup = safexcel_ahash_finup, + .digest = safexcel_sha256_digest, + .export = safexcel_ahash_export,
drivers/crypto/Kconfig
Quoted 10 lines
drivers/crypto/Kconfig +10
-0+ .import = safexcel_ahash_import, + .halg = { + .digestsize = SHA256_DIGEST_SIZE, + .statesize = sizeof(struct safexcel_ahash_export_state), + .base = { + .cra_name = "sha256", + .cra_driver_name = "safexcel-sha256", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY,
Why do use CRYPTO_ALG_KERN_DRIVER_ONLY ?
Regards
Corentin Labbe
PATCH v2 2/3 crypto: inside-secure: add SafeXcel EIP197 crypto engine driver
Hi Corentin,
Quoted 2 lines · Corentin Labbe
I have some minor comment below
[?]
Quoted 5 lines
drivers/crypto/inside-secure/safexcel.c line 387
Quoted 3 lines
drivers/crypto/inside-secure/safexcel.c new file +3
-0+/* +* Result Descriptor Ring prepare +*/ This is not preferred comment format for one line
Sure.
Quoted 15 lines
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drivers/crypto/inside-secure/safexcel.c line 795
Quoted 9 lines
drivers/crypto/inside-secure/safexcel.c new file +9
-0+static int safexcel_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +struct resource *res; +struct safexcel_crypto_priv *priv; +int i, ret; + + priv =devm_kzalloc (dev,sizeof (struct safexcel_crypto_priv ), +GFP_KERNEL );sizeof(priv) is preferred as asked by checkpatch
Quoted 5 lines
[...]
drivers/crypto/inside-secure/safexcel.c line 848
Quoted 2 lines
drivers/crypto/inside-secure/safexcel.c new file +2
-0+ ring_irq =devm_kzalloc (dev,sizeof (struct safexcel_ring_irq_data ), +GFP_KERNEL );same comment here
Sure.
Quoted 11 lines
[...]
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drivers/crypto/inside-secure/safexcel.h new file +10
-0+#define EIP197_ALG_ARC4 BIT(7) +#define EIP197_ALG_AES_ECB BIT(8) +#define EIP197_ALG_AES_CBC BIT(9) +#define EIP197_ALG_AES_CTR_ICM BIT(10) +#define EIP197_ALG_AES_OFB BIT(11) +#define EIP197_ALG_AES_CFB BIT(12) +#define EIP197_ALG_DES_ECB BIT(13) +#define EIP197_ALG_DES_CBC BIT(14) +#define EIP197_ALG_DES_OFB BIT(16) +#define EIP197_ALG_DES_CFB BIT(17)
Quoted 8 lines
drivers/crypto/inside-secure/safexcel.h line 224
Quoted 6 lines
drivers/crypto/inside-secure/safexcel.h new file +6
-0+#define EIP197_ALG_3DES_ECB BIT(18) +#define EIP197_ALG_3DES_CBC BIT(19) +#define EIP197_ALG_3DES_OFB BIT(21) +#define EIP197_ALG_3DES_CFB BIT(22) +#define EIP197_ALG_MD5 BIT(24) +#define EIP197_ALG_HMAC_MD5 BIT(25)Does MD5, DES and 3DES will be added later ?
They might be added yes. And as these bits describe a register used to configure the engine it's nice to have a proper definition of what all combinations do.
Quoted 13 lines
[...]
Quoted 12 lines
drivers/crypto/inside-secure/safexcel_hash.c new file +12
-0+static const u8 sha1_zero_digest[SHA1_DIGEST_SIZE ] = { +0xda ,0x39 ,0xa3 ,0xee ,0x5e ,0x6b ,0x4b ,0x0d ,0x32 ,0x55 , +0xbf ,0xef ,0x95 ,0x60 ,0x18 ,0x90 ,0xaf ,0xd8 ,0x07 ,0x09 , +}; + +static const u8 sha224_zero_digest[SHA224_DIGEST_SIZE ] = { +0xd1 ,0x4a ,0x02 ,0x8c ,0x2a ,0x3a ,0x2b ,0xc9 ,0x47 ,0x61 , +0x02 ,0xbb ,0x28 ,0x82 ,0x34 ,0xc4 ,0x15 ,0xa2 ,0xb0 ,0x1f , +0x82 ,0x8e ,0xa6 ,0x2a ,0xc5 ,0xb3 ,0xe4 ,0x2f +}; + +static const u8 sha256_zero_digest[SHA256_DIGEST_SIZE ] = {
Quoted 8 lines
drivers/crypto/inside-secure/safexcel_hash.c line 69
Quoted 5 lines
drivers/crypto/inside-secure/safexcel_hash.c new file +5
-0+0xe3 ,0xb0 ,0xc4 ,0x42 ,0x98 ,0xfc ,0x1c ,0x14 ,0x9a ,0xfb , +0xf4 ,0xc8 ,0x99 ,0x6f ,0xb9 ,0x24 ,0x27 ,0xae ,0x41 ,0xe4 , +0x64 ,0x9b ,0x93 ,0x4c ,0xa4 ,0x95 ,0x99 ,0x1b ,0x78 ,0x52 , +0xb8 ,0x55 +};Thoses structures are already defined in crypto (
sha1_zero_message_hash, etc...) You can use it since you select SHAxxx inKconfig
That's right, I'll use these definitions instead.
Quoted 25 lines
[...]
Quoted 24 lines
drivers/crypto/inside-secure/safexcel_hash.c new file +24
-0+static int safexcel_hmac_init_pad (struct ahash_request *areq, +unsigned int blocksize,const u8 *key, +unsigned int keylen,u8 *ipad,u8 *opad) +{ +struct safexcel_ahash_result result; +struct scatterlist sg; +int ret, i; +u8 *keydup; + +if (keylen <= blocksize) { +memcpy (ipad, key, keylen); + }else { + keydup =kmemdup (key, keylen,GFP_KERNEL ); +if (!keydup) +return -ENOMEM ; + +ahash_request_set_callback (areq,CRYPTO_TFM_REQ_MAY_BACKLOG , + safexcel_ahash_complete, &result); +sg_init_one (&sg, keydup, keylen); +ahash_request_set_crypt (areq, &sg, ipad, keylen); +init_completion (&result.completion); + + ret =crypto_ahash_digest (areq); +if (ret == -EINPROGRESS ) {
Quoted 8 lines
drivers/crypto/inside-secure/safexcel_hash.c line 779
Quoted 6 lines
drivers/crypto/inside-secure/safexcel_hash.c new file +6
-0+wait_for_completion_interruptible (&result.completion); + ret = result.error; + } + +/* Avoid leaking */ +memset (keydup,0 , keylen);It is safer to use
memzero_explicit
Good to know, I'll update.
Quoted 8 lines
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drivers/crypto/inside-secure/safexcel_hash.c new file +8
-0+kfree (keydup); + +if (ret) +return ret; + + keylen =crypto_ahash_digestsize (crypto_ahash_reqtfm (areq)); + } +
Quoted 8 lines
drivers/crypto/inside-secure/safexcel_hash.c line 793
Quoted 6 lines
drivers/crypto/inside-secure/safexcel_hash.c new file +6
-0+memset (ipad + keylen,0 , blocksize - keylen); +memcpy (opad, ipad, blocksize); + +for (i =0 ; i < blocksize; i++) { + ipad[i] ^=0x36 ; + opad[i] ^=0x5c ;What are these constant ?
They are defined in the HMAC RFC, as ipad and opad values. See
https://www.ietf.org/rfc/rfc2104.txt.
Quoted 11 lines
[...]
drivers/crypto/inside-secure/safexcel_hash.c line 890
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drivers/crypto/inside-secure/safexcel_hash.c new file +8
-0+static int safexcel_hmac_sha1_setkey (struct crypto_ahash *tfm,const u8 *key, +unsigned int keylen) +{ +struct safexcel_ahash_ctx *ctx =crypto_tfm_ctx (crypto_ahash_tfm (tfm)); +struct safexcel_ahash_export_state istate, ostate; +int ret, i; + + ret =safexcel_hmac_setkey ("safexcel-sha1" , key, keylen, &istate, &ostate);Perhaps you could use the algname instead of "safexcel-sha1"
No we can't (as of now), because using the SHA implementation of this driver for partial hashes require special treatments (which we do).
Quoted 7 lines
drivers/crypto/inside-secure/safexcel_hash.c line 895
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drivers/crypto/inside-secure/safexcel_hash.c new file +5
-0+if (ret) +return ret; + +memcpy (ctx->ipad, &istate.state,SHA1_DIGEST_SIZE ); +memcpy (ctx->opad, &ostate.state,SHA1_DIGEST_SIZE );Perhaps you could the
digest_sizefromalg_template
Well, this HMAC setkey function is dedicated to SHA1 for other reasons than only this digest size. So why bother retrieving something which we know is already fixed?
Quoted 14 lines
[...]
Quoted 13 lines
drivers/crypto/inside-secure/safexcel_hash.c new file +13
-0+struct safexcel_alg_template safexcel_alg_sha256 = { + .type =SAFEXCEL_ALG_TYPE_AHASH , + .alg.ahash = { + .init = safexcel_sha256_init, + .update = safexcel_ahash_update, + .final = safexcel_ahash_final, + .finup = safexcel_ahash_finup, + .digest = safexcel_sha256_digest, + .export = safexcel_ahash_export, + .import = safexcel_ahash_import, + .halg = { + .digestsize =SHA256_DIGEST_SIZE , + .statesize =sizeof (struct safexcel_ahash_export_state ),
Quoted 8 lines
drivers/crypto/inside-secure/safexcel_hash.c line 989
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drivers/crypto/inside-secure/safexcel_hash.c new file +6
-0+ .base = { + .cra_name = "sha256", + .cra_driver_name = "safexcel-sha256", + .cra_priority = 300, + .cra_flags =CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY,Why do use
CRYPTO_ALG_KERN_DRIVER_ONLY?
See http://lxr.free-electrons.com/source/include/linux/crypto.h#L97.
Thanks,
Antoine
Signature · 10 lines
Antoine T?nart, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170421/11564af3/attachment-0001.sig>
PATCH v2 2/3 crypto: inside-secure: add SafeXcel EIP197 crypto engine driver
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drivers/crypto/inside-secure/safexcel_hash.c line 793
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drivers/crypto/inside-secure/safexcel_hash.c new file +6
-0+memset (ipad + keylen,0 , blocksize - keylen); +memcpy (opad, ipad, blocksize); + +for (i =0 ; i < blocksize; i++) { + ipad[i] ^=0x36 ; + opad[i] ^=0x5c ;What are these constant ?
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They are defined in the HMAC RFC, as ipad and opad values. See
https://www.ietf.org/rfc/rfc2104.txt.
Since many driver use them, I think defining them in include/ should be done (HMAC_IPAD/HMAC_OPAD) I will send a patch for it.
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[...]
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drivers/crypto/inside-secure/safexcel_hash.c new file +13
-0+struct safexcel_alg_template safexcel_alg_sha256 = { + .type =SAFEXCEL_ALG_TYPE_AHASH , + .alg.ahash = { + .init = safexcel_sha256_init, + .update = safexcel_ahash_update, + .final = safexcel_ahash_final, + .finup = safexcel_ahash_finup, + .digest = safexcel_sha256_digest, + .export = safexcel_ahash_export, + .import = safexcel_ahash_import, + .halg = { + .digestsize =SHA256_DIGEST_SIZE , + .statesize =sizeof (struct safexcel_ahash_export_state ),Quoted 8 lines
drivers/crypto/inside-secure/safexcel_hash.c line 989
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drivers/crypto/inside-secure/safexcel_hash.c new file +6
-0+ .base = { + .cra_name = "sha256", + .cra_driver_name = "safexcel-sha256", + .cra_priority = 300, + .cra_flags =CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY,Why do use
CRYPTO_ALG_KERN_DRIVER_ONLY?
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See http://lxr.free-electrons.com/source/include/linux/crypto.h#L97.
Sorry, I had understood that flag as "do not let userspace use me". Anyway, this flag is totally ignored by the cryptoAPI.
PATCH v2 2/3 crypto: inside-secure: add SafeXcel EIP197 crypto engine driver
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drivers/crypto/inside-secure/safexcel_hash.c line 793
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drivers/crypto/inside-secure/safexcel_hash.c new file +6
-0+memset (ipad + keylen,0 , blocksize - keylen); +memcpy (opad, ipad, blocksize); + +for (i =0 ; i < blocksize; i++) { + ipad[i] ^=0x36 ; + opad[i] ^=0x5c ;What are these constant ?
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They are defined in the HMAC RFC, as ipad and opad values. See
https://www.ietf.org/rfc/rfc2104.txt.Since many driver use them, I think defining them in
include/should be done (HMAC_IPAD/HMAC_OPAD) I will send a patch for it.
OK, I'll send a following up patch on this driver when your series is merged.
Antoine
Signature · 10 lines
Antoine T?nart, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170421/76266910/attachment.sig>
PATCH v2 3/3 MAINTAINERS: add a maintainer for the Inside Secure crypto driver
In reply to Antoine TenartA new cryptographic engine driver was added in drivers/crypto/inside-secure. Add myself as a maintainer for this driver.
--- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+)
MAINTAINERS +6 -0
@@ -6487,6 +6487,12 @@ F: Documentation/input/multi-touch-protocol.txt F: drivers/input/input-mt.c K: \b(ABS|SYN)_MT_ +INSIDE SECURE CRYPTO DRIVER +M: Antoine Tenart <[email protected]> +F: drivers/crypto/inside-secure/ +S: Maintained +L: linux-crypto at vger.kernel.org + INTEL ASoC BDW/HSW DRIVERS M: Jie Yang <[email protected]> L: alsa-devel at alsa-project.org (moderated for non-subscribers)
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2.11.0