devicetree simple-battery and client in bq27xxx_battery

From: Liam Breck <[email protected]>

Add these to enable read/write of chip data memory RAM/NVM/flash:
bq27xxx_battery_seal()
bq27xxx_battery_unseal() bq27xxx_battery_set_cfgupdate() bq27xxx_battery_read_dm_block() bq27xxx_battery_write_dm_block() bq27xxx_battery_checksum_dm_block()

Signed-off-by Matt Ranostay <[email protected]>

Signed-off-by Liam Breck <[email protected]>

---
 drivers/power/supply/bq27xxx_battery.c | 253 +++++++++++++++++++++++++++++++++
 include/linux/power/bq27xxx_battery.h  |   1 +
 2 files changed, 254 insertions(+)

drivers/power/supply/bq27xxx_battery.c +146 -0

index a11dfad..8ab184c 100644
@@ -5,6 +5,7 @@
  * Copyright (C) 2008 Eurotech S.p.A. <[email protected]>
  * Copyright (C) 2010-2011 Lars-Peter Clausen <[email protected]>
  * Copyright (C) 2011 Pali Rohár <[email protected]>
+ * Copyright (C) 2017 Liam Breck <[email protected]>
  *
  * Based on a previous work by Copyright (C) 2008 Texas Instruments, Inc.
  *

@@ -65,6 +66,7 @@
 #define BQ27XXX_FLAG_DSC	BIT(0)
 #define BQ27XXX_FLAG_SOCF	BIT(1) /* State-of-Charge threshold final */
 #define BQ27XXX_FLAG_SOC1	BIT(2) /* State-of-Charge threshold 1 */
+#define BQ27XXX_FLAG_CFGUP	BIT(4)
 #define BQ27XXX_FLAG_FC		BIT(9)
 #define BQ27XXX_FLAG_OTD	BIT(14)
 #define BQ27XXX_FLAG_OTC	BIT(15)

@@ -78,6 +80,12 @@
 #define BQ27000_FLAG_FC		BIT(5)
 #define BQ27000_FLAG_CHGS	BIT(7) /* Charge state flag */
 
+/* control register params */
+#define BQ27XXX_SEALED			0x20
+#define BQ27XXX_SET_CFGUPDATE		0x13
+#define BQ27XXX_SOFT_RESET		0x42
+#define BQ27XXX_RESET			0x41
+
 #define BQ27XXX_RS			(20) /* Resistor sense mOhm */
 #define BQ27XXX_POWER_CONSTANT		(29200) /* 29.2 µV^2 * 1000 */
 #define BQ27XXX_CURRENT_CONSTANT	(3570) /* 3.57 µV * 1000 */

@@ -108,9 +116,21 @@ enum bq27xxx_reg_index {
 	BQ27XXX_REG_SOC,	/* State-of-Charge */
 	BQ27XXX_REG_DCAP,	/* Design Capacity */
 	BQ27XXX_REG_AP,		/* Average Power */
+	BQ27XXX_DM_CTRL,	/* Block Data Control */
+	BQ27XXX_DM_CLASS,	/* Data Class */
+	BQ27XXX_DM_BLOCK,	/* Data Block */
+	BQ27XXX_DM_DATA,	/* Block Data */
+	BQ27XXX_DM_CKSUM,	/* Block Data Checksum */
 	BQ27XXX_REG_MAX,	/* sentinel */
 };
 
+#define BQ27XXX_DM_REG_ROWS \
+	[BQ27XXX_DM_CTRL] = 0x61,  \
+	[BQ27XXX_DM_CLASS] = 0x3e, \
+	[BQ27XXX_DM_BLOCK] = 0x3f, \
+	[BQ27XXX_DM_DATA] = 0x40,  \
+	[BQ27XXX_DM_CKSUM] = 0x60
+
 /* Register mappings */
 static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 	[BQ27000] = {

@@ -131,6 +151,11 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x0b,
 		[BQ27XXX_REG_DCAP] = 0x76,
 		[BQ27XXX_REG_AP] = 0x24,
+		[BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
+		[BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
+		[BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
+		[BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
+		[BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
 	},
 	[BQ27010] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -150,6 +175,11 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x0b,
 		[BQ27XXX_REG_DCAP] = 0x76,
 		[BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+		[BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
+		[BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
+		[BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
+		[BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
+		[BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
 	},
 	[BQ2750X] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -169,6 +199,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x2c,
 		[BQ27XXX_REG_DCAP] = 0x3c,
 		[BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ2751X] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -188,6 +219,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x20,
 		[BQ27XXX_REG_DCAP] = 0x2e,
 		[BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27500] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -207,6 +239,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x2c,
 		[BQ27XXX_REG_DCAP] = 0x3c,
 		[BQ27XXX_REG_AP] = 0x24,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27510G1] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -226,6 +259,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x2c,
 		[BQ27XXX_REG_DCAP] = 0x3c,
 		[BQ27XXX_REG_AP] = 0x24,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27510G2] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -245,6 +279,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x2c,
 		[BQ27XXX_REG_DCAP] = 0x3c,
 		[BQ27XXX_REG_AP] = 0x24,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27510G3] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -264,6 +299,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x20,
 		[BQ27XXX_REG_DCAP] = 0x2e,
 		[BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27520G1] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -283,6 +319,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x2c,
 		[BQ27XXX_REG_DCAP] = 0x3c,
 		[BQ27XXX_REG_AP] = 0x24,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27520G2] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -302,6 +339,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x2c,
 		[BQ27XXX_REG_DCAP] = 0x3c,
 		[BQ27XXX_REG_AP] = 0x24,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27520G3] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -321,6 +359,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x2c,
 		[BQ27XXX_REG_DCAP] = 0x3c,
 		[BQ27XXX_REG_AP] = 0x24,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27520G4] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -340,6 +379,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x20,
 		[BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
 		[BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27530] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -359,6 +399,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x2c,
 		[BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
 		[BQ27XXX_REG_AP] = 0x24,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27541] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -378,6 +419,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x2c,
 		[BQ27XXX_REG_DCAP] = 0x3c,
 		[BQ27XXX_REG_AP] = 0x24,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27545] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -397,6 +439,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x2c,
 		[BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
 		[BQ27XXX_REG_AP] = 0x24,
+		BQ27XXX_DM_REG_ROWS,
 	},
 	[BQ27421] = {
 		[BQ27XXX_REG_CTRL] = 0x00,

@@ -416,6 +459,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
 		[BQ27XXX_REG_SOC] = 0x1c,
 		[BQ27XXX_REG_DCAP] = 0x3c,
 		[BQ27XXX_REG_AP] = 0x18,
+		BQ27XXX_DM_REG_ROWS,
 	},
 };
 

@@ -757,6 +801,28 @@ static struct {
 static DEFINE_MUTEX(bq27xxx_list_lock);
 static LIST_HEAD(bq27xxx_battery_devices);
 
+#define BQ27XXX_MSLEEP(i) usleep_range((i)*1000, (i)*1000+500)
+
+#define BQ27XXX_DM_SZ	32
+
+/**
+ * struct bq27xxx_dm_buf - chip data memory buffer
+ * @class: data memory subclass_id
+ * @block: data memory block number
+ * @data: data from/for the block
+ * @has_data: true if data has been filled by read
+ * @dirty: true if data has changed since last read/write
+ *
+ * Encapsulates info required to manage chip data memory blocks.
+ */
+struct bq27xxx_dm_buf {
+	u8 class;
+	u8 block;
+	u8 data[BQ27XXX_DM_SZ];
+	bool has_data, dirty;
+};
+
+
 static int poll_interval_param_set(const char *val, const struct kernel_param *kp)
 {
 	struct bq27xxx_device_info *di;

@@ -864,6 +930,193 @@ static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in
 	return ret;
 }
 
+static int bq27xxx_battery_seal(struct bq27xxx_device_info *di)
+{
+	int ret;
+
+	ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, BQ27XXX_SEALED, false);
+	if (ret < 0) {
+		dev_err(di->dev, "bus error on seal: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int bq27xxx_battery_unseal(struct bq27xxx_device_info *di)
+{
+	int ret;
+
+	if (di->unseal_key == 0) {
+		dev_err(di->dev, "unseal failed due to missing key\n");
+		return -EINVAL;
+	}
+
+	ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)(di->unseal_key >> 16), false);
+	if (ret < 0)
+		goto out;
+
+	ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)di->unseal_key, false);
+	if (ret < 0)
+		goto out;
+
+	return 0;
+
+out:
+	dev_err(di->dev, "bus error on unseal: %d\n", ret);
+	return ret;
+}
+
+static u8 bq27xxx_battery_checksum_dm_block(struct bq27xxx_dm_buf *buf)
+{
+	u16 sum = 0;
+	int i;
+
+	for (i = 0; i < BQ27XXX_DM_SZ; i++)
+		sum += buf->data[i];
+	sum &= 0xff;
+
+	return 0xff - sum;
+}
+
+static int bq27xxx_battery_read_dm_block(struct bq27xxx_device_info *di,
+					 struct bq27xxx_dm_buf *buf)
+{
+	int ret;
+
+	buf->has_data = false;
+
+	ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
+	if (ret < 0)
+		goto out;
+
+	ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
+	if (ret < 0)
+		goto out;
+
+	BQ27XXX_MSLEEP(1);
+
+	ret = bq27xxx_read_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
+	if (ret < 0)
+		goto out;
+
+	ret = bq27xxx_read(di, BQ27XXX_DM_CKSUM, true);
+	if (ret < 0)
+		goto out;
+
+	if ((u8)ret != bq27xxx_battery_checksum_dm_block(buf)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	buf->has_data = true;

drivers/power/supply/bq27xxx_battery.c +26 -0

+{
+	const int limit = 100;
+	int ret, try = limit;
+
+	ret = bq27xxx_write(di, BQ27XXX_REG_CTRL,
+			    state ? BQ27XXX_SET_CFGUPDATE : BQ27XXX_SOFT_RESET,
+			    false);
+	if (ret < 0)
+		goto out;
+
+	do {
+		BQ27XXX_MSLEEP(25);
+		ret = di->bus.read(di, di->regs[BQ27XXX_REG_FLAGS], false);
+		if (ret < 0)
+			goto out;
+	} while ((ret & BQ27XXX_FLAG_CFGUP) != state && --try);
+
+	if (!try) {
+		dev_err(di->dev, "timed out waiting for cfgupdate flag %d\n", !!state);
+		return -EINVAL;
+	}
+
+	if (limit-try > 3)
+		dev_warn(di->dev, "cfgupdate %d, retries %d\n", !!state, limit-try);
+
+	return 0;

drivers/power/supply/bq27xxx_battery.c +30 -0

+	int ret;
+
+	if (!buf->dirty)
+		return 0;
+
+	if (cfgup) {
+		ret = bq27xxx_battery_set_cfgupdate(di, BQ27XXX_FLAG_CFGUP);
+		if (ret < 0)
+			return ret;
+	}
+
+	ret = bq27xxx_write(di, BQ27XXX_DM_CTRL, 0, true);
+	if (ret < 0)
+		goto out;
+
+	ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
+	if (ret < 0)
+		goto out;
+
+	ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
+	if (ret < 0)
+		goto out;
+
+	BQ27XXX_MSLEEP(1);
+
+	ret = bq27xxx_write_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
+	if (ret < 0)
+		goto out;
+
+	ret = bq27xxx_write(di, BQ27XXX_DM_CKSUM,

drivers/power/supply/bq27xxx_battery.c +21 -0

+	if (cfgup) {
+		BQ27XXX_MSLEEP(1);
+		ret = bq27xxx_battery_set_cfgupdate(di, 0);
+		if (ret < 0)
+			return ret;
+	} else {
+		BQ27XXX_MSLEEP(100); /* flash DM updates in <100ms */
+	}
+
+	buf->dirty = false;
+
+	return 0;
+
+out:
+	if (cfgup)
+		bq27xxx_battery_set_cfgupdate(di, 0);
+
+	dev_err(di->dev, "bus error writing chip memory: %d\n", ret);
+	return ret;
+}
+
 /*
  * Return the battery State-of-Charge
  * Or < 0 if something fails.

include/linux/power/bq27xxx_battery.h +1 -0

index c3369fa..b1defb8 100644
@@ -64,6 +64,7 @@ struct bq27xxx_device_info {
 	int id;
 	enum bq27xxx_chip chip;
 	const char *name;
+	u32 unseal_key;
 	struct bq27xxx_access_methods bus;
 	struct bq27xxx_reg_cache cache;
 	int charge_design_full;

Quoted 326 lines · Liam Breck

From: Liam Breck <[email protected]>

Add these to enable read/write of chip data memory RAM/NVM/flash:
bq27xxx_battery_seal()
bq27xxx_battery_unseal() bq27xxx_battery_set_cfgupdate() bq27xxx_battery_read_dm_block() bq27xxx_battery_write_dm_block() bq27xxx_battery_checksum_dm_block()

Signed-off-by Matt Ranostay <[email protected]>

Signed-off-by Liam Breck <[email protected]>

---
 drivers/power/supply/bq27xxx_battery.c | 253 +++++++++++++++++++++++++++++++++
 include/linux/power/bq27xxx_battery.h  |   1 +
 2 files changed, 254 insertions(+)

drivers/power/supply/bq27xxx_battery.c +151 -0

index a11dfad..8ab184c 100644
@@ -5,6 +5,7 @@
  * Copyright (C) 2008 Eurotech S.p.A. <[email protected]>
  * Copyright (C) 2010-2011 Lars-Peter Clausen <[email protected]>
  * Copyright (C) 2011 Pali Rohár <[email protected]>
+ * Copyright (C) 2017 Liam Breck <[email protected]>
  *
  * Based on a previous work by Copyright (C) 2008 Texas Instruments, Inc.
  *

@@ -65,6 +66,7 @@
 #define BQ27XXX_FLAG_DSC     BIT(0)
 #define BQ27XXX_FLAG_SOCF    BIT(1) /* State-of-Charge threshold final */
 #define BQ27XXX_FLAG_SOC1    BIT(2) /* State-of-Charge threshold 1 */
+#define BQ27XXX_FLAG_CFGUP   BIT(4)
 #define BQ27XXX_FLAG_FC              BIT(9)
 #define BQ27XXX_FLAG_OTD     BIT(14)
 #define BQ27XXX_FLAG_OTC     BIT(15)

@@ -78,6 +80,12 @@
 #define BQ27000_FLAG_FC              BIT(5)
 #define BQ27000_FLAG_CHGS    BIT(7) /* Charge state flag */
 
+/* control register params */
+#define BQ27XXX_SEALED                       0x20
+#define BQ27XXX_SET_CFGUPDATE                0x13
+#define BQ27XXX_SOFT_RESET           0x42
+#define BQ27XXX_RESET                        0x41
+
 #define BQ27XXX_RS                   (20) /* Resistor sense mOhm */
 #define BQ27XXX_POWER_CONSTANT               (29200) /* 29.2 µV^2 * 1000 */
 #define BQ27XXX_CURRENT_CONSTANT     (3570) /* 3.57 µV * 1000 */

@@ -108,9 +116,21 @@ enum bq27xxx_reg_index {
      BQ27XXX_REG_SOC,        /* State-of-Charge */
      BQ27XXX_REG_DCAP,       /* Design Capacity */
      BQ27XXX_REG_AP,         /* Average Power */
+     BQ27XXX_DM_CTRL,        /* Block Data Control */
+     BQ27XXX_DM_CLASS,       /* Data Class */
+     BQ27XXX_DM_BLOCK,       /* Data Block */
+     BQ27XXX_DM_DATA,        /* Block Data */
+     BQ27XXX_DM_CKSUM,       /* Block Data Checksum */
      BQ27XXX_REG_MAX,        /* sentinel */
 };
 
+#define BQ27XXX_DM_REG_ROWS \
+     [BQ27XXX_DM_CTRL] = 0x61,  \
+     [BQ27XXX_DM_CLASS] = 0x3e, \
+     [BQ27XXX_DM_BLOCK] = 0x3f, \
+     [BQ27XXX_DM_DATA] = 0x40,  \
+     [BQ27XXX_DM_CKSUM] = 0x60
+
 /* Register mappings */
 static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
      [BQ27000] = {

@@ -131,6 +151,11 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x0b,
              [BQ27XXX_REG_DCAP] = 0x76,
              [BQ27XXX_REG_AP] = 0x24,
+             [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
      },
      [BQ27010] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -150,6 +175,11 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x0b,
              [BQ27XXX_REG_DCAP] = 0x76,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
      },
      [BQ2750X] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -169,6 +199,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ2751X] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -188,6 +219,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = 0x2e,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27500] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -207,6 +239,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G1] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -226,6 +259,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G2] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -245,6 +279,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G3] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -264,6 +299,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = 0x2e,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G1] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -283,6 +319,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G2] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -302,6 +339,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G3] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -321,6 +359,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G4] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -340,6 +379,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27530] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -359,6 +399,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27541] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -378,6 +419,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27545] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -397,6 +439,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27421] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -416,6 +459,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x1c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x18,
+             BQ27XXX_DM_REG_ROWS,
      },
 };
 

@@ -757,6 +801,28 @@ static struct {
 static DEFINE_MUTEX(bq27xxx_list_lock);
 static LIST_HEAD(bq27xxx_battery_devices);
 
+#define BQ27XXX_MSLEEP(i) usleep_range((i)*1000, (i)*1000+500)
+
+#define BQ27XXX_DM_SZ        32
+
+/**
+ * struct bq27xxx_dm_buf - chip data memory buffer
+ * @class: data memory subclass_id
+ * @block: data memory block number
+ * @data: data from/for the block
+ * @has_data: true if data has been filled by read
+ * @dirty: true if data has changed since last read/write
+ *
+ * Encapsulates info required to manage chip data memory blocks.
+ */
+struct bq27xxx_dm_buf {
+     u8 class;
+     u8 block;
+     u8 data[BQ27XXX_DM_SZ];
+     bool has_data, dirty;
+};
+
+
 static int poll_interval_param_set(const char *val, const struct kernel_param *kp)
 {
      struct bq27xxx_device_info *di;

@@ -864,6 +930,193 @@ static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in
      return ret;
 }
 
+static int bq27xxx_battery_seal(struct bq27xxx_device_info *di)
+{
+     int ret;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, BQ27XXX_SEALED, false);
+     if (ret < 0) {
+             dev_err(di->dev, "bus error on seal: %d\n", ret);
+             return ret;
+     }
+
+     return 0;
+}
+
+static int bq27xxx_battery_unseal(struct bq27xxx_device_info *di)
+{
+     int ret;
+
+     if (di->unseal_key == 0) {
+             dev_err(di->dev, "unseal failed due to missing key\n");
+             return -EINVAL;
+     }
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)(di->unseal_key >> 16), false);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)di->unseal_key, false);
+     if (ret < 0)
+             goto out;
+
+     return 0;
+
+out:
+     dev_err(di->dev, "bus error on unseal: %d\n", ret);
+     return ret;
+}
+
+static u8 bq27xxx_battery_checksum_dm_block(struct bq27xxx_dm_buf *buf)
+{
+     u16 sum = 0;
+     int i;
+
+     for (i = 0; i < BQ27XXX_DM_SZ; i++)
+             sum += buf->data[i];
+     sum &= 0xff;
+
+     return 0xff - sum;
+}
+
+static int bq27xxx_battery_read_dm_block(struct bq27xxx_device_info *di,
+                                      struct bq27xxx_dm_buf *buf)
+{
+     int ret;
+
+     buf->has_data = false;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
+     if (ret < 0)
+             goto out;
+
+     BQ27XXX_MSLEEP(1);
+
+     ret = bq27xxx_read_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_read(di, BQ27XXX_DM_CKSUM, true);
+     if (ret < 0)
+             goto out;
+
+     if ((u8)ret != bq27xxx_battery_checksum_dm_block(buf)) {
+             ret = -EINVAL;
+             goto out;
+     }
+
+     buf->has_data = true;
+     buf->dirty = false;
+
+     return 0;
+
+out:

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1022

Quoted 5 lines

drivers/power/supply/bq27xxx_battery.c +5 -0

+     dev_err(di->dev, "bus error reading chip memory: %d\n", ret);
+     return ret;
+}
+
+static int bq27xxx_battery_set_cfgupdate(struct bq27xxx_device_info *di, u16 state)

Why do you pass in a flag but treat it like a bool? This whole function needs to be re-factored.

Quoted 30 lines

drivers/power/supply/bq27xxx_battery.c +30 -0

+{
+     const int limit = 100;
+     int ret, try = limit;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL,
+                         state ? BQ27XXX_SET_CFGUPDATE : BQ27XXX_SOFT_RESET,
+                         false);
+     if (ret < 0)
+             goto out;
+
+     do {
+             BQ27XXX_MSLEEP(25);
+             ret = di->bus.read(di, di->regs[BQ27XXX_REG_FLAGS], false);
+             if (ret < 0)
+                     goto out;
+     } while ((ret & BQ27XXX_FLAG_CFGUP) != state && --try);
+
+     if (!try) {
+             dev_err(di->dev, "timed out waiting for cfgupdate flag %d\n", !!state);
+             return -EINVAL;
+     }
+
+     if (limit-try > 3)
+             dev_warn(di->dev, "cfgupdate %d, retries %d\n", !!state, limit-try);
+
+     return 0;
+
+out:
+     dev_err(di->dev, "bus error on %s: %d\n", state ? "set_cfgupdate" : "soft_reset", ret);
+     return ret;

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1058

Quoted 6 lines

drivers/power/supply/bq27xxx_battery.c +6 -0

+}
+
+static int bq27xxx_battery_write_dm_block(struct bq27xxx_device_info *di,
+                                       struct bq27xxx_dm_buf *buf)
+{
+     bool cfgup = di->chip == BQ27421; /* assume group supports cfgupdate */

Group? This is a single chip ID.

Quoted 36 lines

drivers/power/supply/bq27xxx_battery.c +36 -0

+     int ret;
+
+     if (!buf->dirty)
+             return 0;
+
+     if (cfgup) {
+             ret = bq27xxx_battery_set_cfgupdate(di, BQ27XXX_FLAG_CFGUP);
+             if (ret < 0)
+                     return ret;
+     }
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CTRL, 0, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
+     if (ret < 0)
+             goto out;
+
+     BQ27XXX_MSLEEP(1);
+
+     ret = bq27xxx_write_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CKSUM,
+                         bq27xxx_battery_checksum_dm_block(buf), true);
+     if (ret < 0)
+             goto out;
+
+     /* DO NOT read BQ27XXX_DM_CKSUM here to verify it! That may cause NVM
+      * corruption on the '425 chip (and perhaps others), which can damage

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1098

Quoted 4 lines

drivers/power/supply/bq27xxx_battery.c +4 -0

+      * the chip. See TI bqtool for what not to do:
+      * http://git.ti.com/bms-linux/bqtool/blobs/master/gauge.c#line328
+      */
+

Again, this is not needed, I'm sorry you fried your chip somehow but this program is not incorrect, it is used by our customers all the time and does not fry chips, drop this comment.

Quoted 37 lines

drivers/power/supply/bq27xxx_battery.c +21 -0

+     if (cfgup) {
+             BQ27XXX_MSLEEP(1);
+             ret = bq27xxx_battery_set_cfgupdate(di, 0);
+             if (ret < 0)
+                     return ret;
+     } else {
+             BQ27XXX_MSLEEP(100); /* flash DM updates in <100ms */
+     }
+
+     buf->dirty = false;
+
+     return 0;
+
+out:
+     if (cfgup)
+             bq27xxx_battery_set_cfgupdate(di, 0);
+
+     dev_err(di->dev, "bus error writing chip memory: %d\n", ret);
+     return ret;
+}
+
 /*
  * Return the battery State-of-Charge
  * Or < 0 if something fails.

include/linux/power/bq27xxx_battery.h +1 -0

index c3369fa..b1defb8 100644
@@ -64,6 +64,7 @@ struct bq27xxx_device_info {
      int id;
      enum bq27xxx_chip chip;
      const char *name;
+     u32 unseal_key;
      struct bq27xxx_access_methods bus;
      struct bq27xxx_reg_cache cache;
      int charge_design_full;

Quoted 326 lines · Liam Breck

From: Liam Breck <[email protected]>

Add these to enable read/write of chip data memory RAM/NVM/flash:
bq27xxx_battery_seal()
bq27xxx_battery_unseal() bq27xxx_battery_set_cfgupdate() bq27xxx_battery_read_dm_block() bq27xxx_battery_write_dm_block() bq27xxx_battery_checksum_dm_block()

Signed-off-by Matt Ranostay <[email protected]>

Signed-off-by Liam Breck <[email protected]>

---
 drivers/power/supply/bq27xxx_battery.c | 253 +++++++++++++++++++++++++++++++++
 include/linux/power/bq27xxx_battery.h  |   1 +
 2 files changed, 254 insertions(+)

drivers/power/supply/bq27xxx_battery.c +151 -0

index a11dfad..8ab184c 100644
@@ -5,6 +5,7 @@
  * Copyright (C) 2008 Eurotech S.p.A. <[email protected]>
  * Copyright (C) 2010-2011 Lars-Peter Clausen <[email protected]>
  * Copyright (C) 2011 Pali Rohár <[email protected]>
+ * Copyright (C) 2017 Liam Breck <[email protected]>
  *
  * Based on a previous work by Copyright (C) 2008 Texas Instruments, Inc.
  *

@@ -65,6 +66,7 @@
 #define BQ27XXX_FLAG_DSC     BIT(0)
 #define BQ27XXX_FLAG_SOCF    BIT(1) /* State-of-Charge threshold final */
 #define BQ27XXX_FLAG_SOC1    BIT(2) /* State-of-Charge threshold 1 */
+#define BQ27XXX_FLAG_CFGUP   BIT(4)
 #define BQ27XXX_FLAG_FC              BIT(9)
 #define BQ27XXX_FLAG_OTD     BIT(14)
 #define BQ27XXX_FLAG_OTC     BIT(15)

@@ -78,6 +80,12 @@
 #define BQ27000_FLAG_FC              BIT(5)
 #define BQ27000_FLAG_CHGS    BIT(7) /* Charge state flag */
 
+/* control register params */
+#define BQ27XXX_SEALED                       0x20
+#define BQ27XXX_SET_CFGUPDATE                0x13
+#define BQ27XXX_SOFT_RESET           0x42
+#define BQ27XXX_RESET                        0x41
+
 #define BQ27XXX_RS                   (20) /* Resistor sense mOhm */
 #define BQ27XXX_POWER_CONSTANT               (29200) /* 29.2 µV^2 * 1000 */
 #define BQ27XXX_CURRENT_CONSTANT     (3570) /* 3.57 µV * 1000 */

@@ -108,9 +116,21 @@ enum bq27xxx_reg_index {
      BQ27XXX_REG_SOC,        /* State-of-Charge */
      BQ27XXX_REG_DCAP,       /* Design Capacity */
      BQ27XXX_REG_AP,         /* Average Power */
+     BQ27XXX_DM_CTRL,        /* Block Data Control */
+     BQ27XXX_DM_CLASS,       /* Data Class */
+     BQ27XXX_DM_BLOCK,       /* Data Block */
+     BQ27XXX_DM_DATA,        /* Block Data */
+     BQ27XXX_DM_CKSUM,       /* Block Data Checksum */
      BQ27XXX_REG_MAX,        /* sentinel */
 };
 
+#define BQ27XXX_DM_REG_ROWS \
+     [BQ27XXX_DM_CTRL] = 0x61,  \
+     [BQ27XXX_DM_CLASS] = 0x3e, \
+     [BQ27XXX_DM_BLOCK] = 0x3f, \
+     [BQ27XXX_DM_DATA] = 0x40,  \
+     [BQ27XXX_DM_CKSUM] = 0x60
+
 /* Register mappings */
 static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
      [BQ27000] = {

@@ -131,6 +151,11 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x0b,
              [BQ27XXX_REG_DCAP] = 0x76,
              [BQ27XXX_REG_AP] = 0x24,
+             [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
      },
      [BQ27010] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -150,6 +175,11 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x0b,
              [BQ27XXX_REG_DCAP] = 0x76,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
      },
      [BQ2750X] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -169,6 +199,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ2751X] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -188,6 +219,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = 0x2e,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27500] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -207,6 +239,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G1] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -226,6 +259,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G2] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -245,6 +279,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G3] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -264,6 +299,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = 0x2e,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G1] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -283,6 +319,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G2] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -302,6 +339,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G3] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -321,6 +359,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G4] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -340,6 +379,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27530] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -359,6 +399,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27541] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -378,6 +419,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27545] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -397,6 +439,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27421] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -416,6 +459,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x1c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x18,
+             BQ27XXX_DM_REG_ROWS,
      },
 };
 

@@ -757,6 +801,28 @@ static struct {
 static DEFINE_MUTEX(bq27xxx_list_lock);
 static LIST_HEAD(bq27xxx_battery_devices);
 
+#define BQ27XXX_MSLEEP(i) usleep_range((i)*1000, (i)*1000+500)
+
+#define BQ27XXX_DM_SZ        32
+
+/**
+ * struct bq27xxx_dm_buf - chip data memory buffer
+ * @class: data memory subclass_id
+ * @block: data memory block number
+ * @data: data from/for the block
+ * @has_data: true if data has been filled by read
+ * @dirty: true if data has changed since last read/write
+ *
+ * Encapsulates info required to manage chip data memory blocks.
+ */
+struct bq27xxx_dm_buf {
+     u8 class;
+     u8 block;
+     u8 data[BQ27XXX_DM_SZ];
+     bool has_data, dirty;
+};
+
+
 static int poll_interval_param_set(const char *val, const struct kernel_param *kp)
 {
      struct bq27xxx_device_info *di;

@@ -864,6 +930,193 @@ static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in
      return ret;
 }
 
+static int bq27xxx_battery_seal(struct bq27xxx_device_info *di)
+{
+     int ret;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, BQ27XXX_SEALED, false);
+     if (ret < 0) {
+             dev_err(di->dev, "bus error on seal: %d\n", ret);
+             return ret;
+     }
+
+     return 0;
+}
+
+static int bq27xxx_battery_unseal(struct bq27xxx_device_info *di)
+{
+     int ret;
+
+     if (di->unseal_key == 0) {
+             dev_err(di->dev, "unseal failed due to missing key\n");
+             return -EINVAL;
+     }
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)(di->unseal_key >> 16), false);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)di->unseal_key, false);
+     if (ret < 0)
+             goto out;
+
+     return 0;
+
+out:
+     dev_err(di->dev, "bus error on unseal: %d\n", ret);
+     return ret;
+}
+
+static u8 bq27xxx_battery_checksum_dm_block(struct bq27xxx_dm_buf *buf)
+{
+     u16 sum = 0;
+     int i;
+
+     for (i = 0; i < BQ27XXX_DM_SZ; i++)
+             sum += buf->data[i];
+     sum &= 0xff;
+
+     return 0xff - sum;
+}
+
+static int bq27xxx_battery_read_dm_block(struct bq27xxx_device_info *di,
+                                      struct bq27xxx_dm_buf *buf)
+{
+     int ret;
+
+     buf->has_data = false;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
+     if (ret < 0)
+             goto out;
+
+     BQ27XXX_MSLEEP(1);
+
+     ret = bq27xxx_read_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_read(di, BQ27XXX_DM_CKSUM, true);
+     if (ret < 0)
+             goto out;
+
+     if ((u8)ret != bq27xxx_battery_checksum_dm_block(buf)) {
+             ret = -EINVAL;
+             goto out;
+     }
+
+     buf->has_data = true;
+     buf->dirty = false;
+
+     return 0;
+
+out:

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1022

Quoted 5 lines

drivers/power/supply/bq27xxx_battery.c +5 -0

+     dev_err(di->dev, "bus error reading chip memory: %d\n", ret);
+     return ret;
+}
+
+static int bq27xxx_battery_set_cfgupdate(struct bq27xxx_device_info *di, u16 state)

Why do you pass in a flag but treat it like a bool? This whole function needs to be re-factored.

Quoted 26 lines

drivers/power/supply/bq27xxx_battery.c +26 -0

+{
+     const int limit = 100;
+     int ret, try = limit;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL,
+                         state ? BQ27XXX_SET_CFGUPDATE : BQ27XXX_SOFT_RESET,
+                         false);
+     if (ret < 0)
+             goto out;
+
+     do {
+             BQ27XXX_MSLEEP(25);
+             ret = di->bus.read(di, di->regs[BQ27XXX_REG_FLAGS], false);
+             if (ret < 0)
+                     goto out;
+     } while ((ret & BQ27XXX_FLAG_CFGUP) != state && --try);
+
+     if (!try) {
+             dev_err(di->dev, "timed out waiting for cfgupdate flag %d\n", !!state);
+             return -EINVAL;
+     }
+
+     if (limit-try > 3)
+             dev_warn(di->dev, "cfgupdate %d, retries %d\n", !!state, limit-try);
+
+     return 0;

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1058

Quoted 10 lines

drivers/power/supply/bq27xxx_battery.c +10 -0

+
+out:
+     dev_err(di->dev, "bus error on %s: %d\n", state ? "set_cfgupdate" : "soft_reset", ret);
+     return ret;
+}
+
+static int bq27xxx_battery_write_dm_block(struct bq27xxx_device_info *di,
+                                       struct bq27xxx_dm_buf *buf)
+{
+     bool cfgup = di->chip == BQ27421; /* assume group supports cfgupdate */

Group? This is a single chip ID.

Quoted 30 lines

drivers/power/supply/bq27xxx_battery.c +30 -0

+     int ret;
+
+     if (!buf->dirty)
+             return 0;
+
+     if (cfgup) {
+             ret = bq27xxx_battery_set_cfgupdate(di, BQ27XXX_FLAG_CFGUP);
+             if (ret < 0)
+                     return ret;
+     }
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CTRL, 0, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
+     if (ret < 0)
+             goto out;
+
+     BQ27XXX_MSLEEP(1);
+
+     ret = bq27xxx_write_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CKSUM,

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1098

Quoted 10 lines

drivers/power/supply/bq27xxx_battery.c +10 -0

+                         bq27xxx_battery_checksum_dm_block(buf), true);
+     if (ret < 0)
+             goto out;
+
+     /* DO NOT read BQ27XXX_DM_CKSUM here to verify it! That may cause NVM
+      * corruption on the '425 chip (and perhaps others), which can damage
+      * the chip. See TI bqtool for what not to do:
+      * http://git.ti.com/bms-linux/bqtool/blobs/master/gauge.c#line328
+      */
+

Again, this is not needed, I'm sorry you fried your chip somehow but this program is not incorrect, it is used by our customers all the time and does not fry chips, drop this comment.

Quoted 37 lines

drivers/power/supply/bq27xxx_battery.c +21 -0

+     if (cfgup) {
+             BQ27XXX_MSLEEP(1);
+             ret = bq27xxx_battery_set_cfgupdate(di, 0);
+             if (ret < 0)
+                     return ret;
+     } else {
+             BQ27XXX_MSLEEP(100); /* flash DM updates in <100ms */
+     }
+
+     buf->dirty = false;
+
+     return 0;
+
+out:
+     if (cfgup)
+             bq27xxx_battery_set_cfgupdate(di, 0);
+
+     dev_err(di->dev, "bus error writing chip memory: %d\n", ret);
+     return ret;
+}
+
 /*
  * Return the battery State-of-Charge
  * Or < 0 if something fails.

include/linux/power/bq27xxx_battery.h +1 -0

index c3369fa..b1defb8 100644
@@ -64,6 +64,7 @@ struct bq27xxx_device_info {
      int id;
      enum bq27xxx_chip chip;
      const char *name;
+     u32 unseal_key;
      struct bq27xxx_access_methods bus;
      struct bq27xxx_reg_cache cache;
      int charge_design_full;

Quoted 327 lines · Andrew F. Davis

Quoted 326 lines · Liam Breck

From: Liam Breck <[email protected]>

Add these to enable read/write of chip data memory RAM/NVM/flash:
bq27xxx_battery_seal()
bq27xxx_battery_unseal() bq27xxx_battery_set_cfgupdate() bq27xxx_battery_read_dm_block() bq27xxx_battery_write_dm_block() bq27xxx_battery_checksum_dm_block()

Signed-off-by Matt Ranostay <[email protected]>

Signed-off-by Liam Breck <[email protected]>

---
 drivers/power/supply/bq27xxx_battery.c | 253 +++++++++++++++++++++++++++++++++
 include/linux/power/bq27xxx_battery.h  |   1 +
 2 files changed, 254 insertions(+)

drivers/power/supply/bq27xxx_battery.c +151 -0

index a11dfad..8ab184c 100644
@@ -5,6 +5,7 @@
  * Copyright (C) 2008 Eurotech S.p.A. <[email protected]>
  * Copyright (C) 2010-2011 Lars-Peter Clausen <[email protected]>
  * Copyright (C) 2011 Pali Rohár <[email protected]>
+ * Copyright (C) 2017 Liam Breck <[email protected]>
  *
  * Based on a previous work by Copyright (C) 2008 Texas Instruments, Inc.
  *

@@ -65,6 +66,7 @@
 #define BQ27XXX_FLAG_DSC     BIT(0)
 #define BQ27XXX_FLAG_SOCF    BIT(1) /* State-of-Charge threshold final */
 #define BQ27XXX_FLAG_SOC1    BIT(2) /* State-of-Charge threshold 1 */
+#define BQ27XXX_FLAG_CFGUP   BIT(4)
 #define BQ27XXX_FLAG_FC              BIT(9)
 #define BQ27XXX_FLAG_OTD     BIT(14)
 #define BQ27XXX_FLAG_OTC     BIT(15)

@@ -78,6 +80,12 @@
 #define BQ27000_FLAG_FC              BIT(5)
 #define BQ27000_FLAG_CHGS    BIT(7) /* Charge state flag */
 
+/* control register params */
+#define BQ27XXX_SEALED                       0x20
+#define BQ27XXX_SET_CFGUPDATE                0x13
+#define BQ27XXX_SOFT_RESET           0x42
+#define BQ27XXX_RESET                        0x41
+
 #define BQ27XXX_RS                   (20) /* Resistor sense mOhm */
 #define BQ27XXX_POWER_CONSTANT               (29200) /* 29.2 µV^2 * 1000 */
 #define BQ27XXX_CURRENT_CONSTANT     (3570) /* 3.57 µV * 1000 */

@@ -108,9 +116,21 @@ enum bq27xxx_reg_index {
      BQ27XXX_REG_SOC,        /* State-of-Charge */
      BQ27XXX_REG_DCAP,       /* Design Capacity */
      BQ27XXX_REG_AP,         /* Average Power */
+     BQ27XXX_DM_CTRL,        /* Block Data Control */
+     BQ27XXX_DM_CLASS,       /* Data Class */
+     BQ27XXX_DM_BLOCK,       /* Data Block */
+     BQ27XXX_DM_DATA,        /* Block Data */
+     BQ27XXX_DM_CKSUM,       /* Block Data Checksum */
      BQ27XXX_REG_MAX,        /* sentinel */
 };
 
+#define BQ27XXX_DM_REG_ROWS \
+     [BQ27XXX_DM_CTRL] = 0x61,  \
+     [BQ27XXX_DM_CLASS] = 0x3e, \
+     [BQ27XXX_DM_BLOCK] = 0x3f, \
+     [BQ27XXX_DM_DATA] = 0x40,  \
+     [BQ27XXX_DM_CKSUM] = 0x60
+
 /* Register mappings */
 static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
      [BQ27000] = {

@@ -131,6 +151,11 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x0b,
              [BQ27XXX_REG_DCAP] = 0x76,
              [BQ27XXX_REG_AP] = 0x24,
+             [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
      },
      [BQ27010] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -150,6 +175,11 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x0b,
              [BQ27XXX_REG_DCAP] = 0x76,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
      },
      [BQ2750X] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -169,6 +199,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ2751X] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -188,6 +219,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = 0x2e,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27500] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -207,6 +239,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G1] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -226,6 +259,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G2] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -245,6 +279,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G3] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -264,6 +299,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = 0x2e,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G1] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -283,6 +319,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G2] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -302,6 +339,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G3] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -321,6 +359,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G4] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -340,6 +379,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27530] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -359,6 +399,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27541] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -378,6 +419,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27545] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -397,6 +439,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27421] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -416,6 +459,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x1c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x18,
+             BQ27XXX_DM_REG_ROWS,
      },
 };
 

@@ -757,6 +801,28 @@ static struct {
 static DEFINE_MUTEX(bq27xxx_list_lock);
 static LIST_HEAD(bq27xxx_battery_devices);
 
+#define BQ27XXX_MSLEEP(i) usleep_range((i)*1000, (i)*1000+500)
+
+#define BQ27XXX_DM_SZ        32
+
+/**
+ * struct bq27xxx_dm_buf - chip data memory buffer
+ * @class: data memory subclass_id
+ * @block: data memory block number
+ * @data: data from/for the block
+ * @has_data: true if data has been filled by read
+ * @dirty: true if data has changed since last read/write
+ *
+ * Encapsulates info required to manage chip data memory blocks.
+ */
+struct bq27xxx_dm_buf {
+     u8 class;
+     u8 block;
+     u8 data[BQ27XXX_DM_SZ];
+     bool has_data, dirty;
+};
+
+
 static int poll_interval_param_set(const char *val, const struct kernel_param *kp)
 {
      struct bq27xxx_device_info *di;

@@ -864,6 +930,193 @@ static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in
      return ret;
 }
 
+static int bq27xxx_battery_seal(struct bq27xxx_device_info *di)
+{
+     int ret;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, BQ27XXX_SEALED, false);
+     if (ret < 0) {
+             dev_err(di->dev, "bus error on seal: %d\n", ret);
+             return ret;
+     }
+
+     return 0;
+}
+
+static int bq27xxx_battery_unseal(struct bq27xxx_device_info *di)
+{
+     int ret;
+
+     if (di->unseal_key == 0) {
+             dev_err(di->dev, "unseal failed due to missing key\n");
+             return -EINVAL;
+     }
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)(di->unseal_key >> 16), false);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)di->unseal_key, false);
+     if (ret < 0)
+             goto out;
+
+     return 0;
+
+out:
+     dev_err(di->dev, "bus error on unseal: %d\n", ret);
+     return ret;
+}
+
+static u8 bq27xxx_battery_checksum_dm_block(struct bq27xxx_dm_buf *buf)
+{
+     u16 sum = 0;
+     int i;
+
+     for (i = 0; i < BQ27XXX_DM_SZ; i++)
+             sum += buf->data[i];
+     sum &= 0xff;
+
+     return 0xff - sum;
+}
+
+static int bq27xxx_battery_read_dm_block(struct bq27xxx_device_info *di,
+                                      struct bq27xxx_dm_buf *buf)
+{
+     int ret;
+
+     buf->has_data = false;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
+     if (ret < 0)
+             goto out;
+
+     BQ27XXX_MSLEEP(1);
+
+     ret = bq27xxx_read_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_read(di, BQ27XXX_DM_CKSUM, true);
+     if (ret < 0)
+             goto out;
+
+     if ((u8)ret != bq27xxx_battery_checksum_dm_block(buf)) {
+             ret = -EINVAL;
+             goto out;
+     }
+
+     buf->has_data = true;
+     buf->dirty = false;
+
+     return 0;
+
+out:

Quoted 8 lines

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1022

Quoted 5 lines

drivers/power/supply/bq27xxx_battery.c +5 -0

+     dev_err(di->dev, "bus error reading chip memory: %d\n", ret);
+     return ret;
+}
+
+static int bq27xxx_battery_set_cfgupdate(struct bq27xxx_device_info *di, u16 state)

Why do you pass in a flag but treat it like a bool? This whole function needs to be re-factored.

How's this look?

static int bq27xxx_battery_cfgupdate_priv(struct bq27xxx_device_info *di, bool active)

{
        const int limit = 100;
        int ret, try = limit;

        ret = bq27xxx_write(di, BQ27XXX_REG_CTRL,
                            active ? BQ27XXX_SET_CFGUPDATE : BQ27XXX_SOFT_RESET,
                            false);
        if (ret < 0)
                return ret;

        do {
                BQ27XXX_MSLEEP(25);
                ret = bq27xxx_read(di, BQ27XXX_REG_FLAGS, false);
                if (ret < 0)
                        return ret;
        } while (!!(ret & BQ27XXX_FLAG_CFGUP) != active && --try);

        if (!try) {
                dev_err(di->dev, "timed out waiting for cfgupdate flag
%d\n", active);
                return -EINVAL;
        }

        if (limit - try > 3)
                dev_warn(di->dev, "cfgupdate %d, retries %d\n",

active, limit - try);

        return 0;
}

static inline int bq27xxx_battery_set_cfgupdate(struct bq27xxx_device_info *di)

{
        int ret = bq27xxx_battery_cfgupdate_priv(di, true);
        if (ret < 0 && ret != -EINVAL)
                dev_err(di->dev, "bus error on set_cfgupdate: %d\n", ret);

        return ret;
}

static inline int bq27xxx_battery_soft_reset(struct bq27xxx_device_info *di)

{
        int ret = bq27xxx_battery_cfgupdate_priv(di, false);
        if (ret < 0 && ret != -EINVAL)
                dev_err(di->dev, "bus error on soft_reset: %d\n", ret);

        return ret;
}

Quoted 121 lines

Quoted 26 lines

drivers/power/supply/bq27xxx_battery.c +26 -0

+{
+     const int limit = 100;
+     int ret, try = limit;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL,
+                         state ? BQ27XXX_SET_CFGUPDATE : BQ27XXX_SOFT_RESET,
+                         false);
+     if (ret < 0)
+             goto out;
+
+     do {
+             BQ27XXX_MSLEEP(25);
+             ret = di->bus.read(di, di->regs[BQ27XXX_REG_FLAGS], false);
+             if (ret < 0)
+                     goto out;
+     } while ((ret & BQ27XXX_FLAG_CFGUP) != state && --try);
+
+     if (!try) {
+             dev_err(di->dev, "timed out waiting for cfgupdate flag %d\n", !!state);
+             return -EINVAL;
+     }
+
+     if (limit-try > 3)
+             dev_warn(di->dev, "cfgupdate %d, retries %d\n", !!state, limit-try);
+
+     return 0;

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1058

Quoted 10 lines

drivers/power/supply/bq27xxx_battery.c +10 -0

+
+out:
+     dev_err(di->dev, "bus error on %s: %d\n", state ? "set_cfgupdate" : "soft_reset", ret);
+     return ret;
+}
+
+static int bq27xxx_battery_write_dm_block(struct bq27xxx_device_info *di,
+                                       struct bq27xxx_dm_buf *buf)
+{
+     bool cfgup = di->chip == BQ27421; /* assume group supports cfgupdate */

Group? This is a single chip ID.

Quoted 30 lines

drivers/power/supply/bq27xxx_battery.c +30 -0

+     int ret;
+
+     if (!buf->dirty)
+             return 0;
+
+     if (cfgup) {
+             ret = bq27xxx_battery_set_cfgupdate(di, BQ27XXX_FLAG_CFGUP);
+             if (ret < 0)
+                     return ret;
+     }
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CTRL, 0, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
+     if (ret < 0)
+             goto out;
+
+     BQ27XXX_MSLEEP(1);
+
+     ret = bq27xxx_write_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CKSUM,

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1098

Quoted 10 lines

drivers/power/supply/bq27xxx_battery.c +10 -0

+                         bq27xxx_battery_checksum_dm_block(buf), true);
+     if (ret < 0)
+             goto out;
+
+     /* DO NOT read BQ27XXX_DM_CKSUM here to verify it! That may cause NVM
+      * corruption on the '425 chip (and perhaps others), which can damage
+      * the chip. See TI bqtool for what not to do:
+      * http://git.ti.com/bms-linux/bqtool/blobs/master/gauge.c#line328
+      */
+

Again, this is not needed, I'm sorry you fried your chip somehow but this program is not incorrect, it is used by our customers all the time and does not fry chips, drop this comment.

Quoted 37 lines

drivers/power/supply/bq27xxx_battery.c +21 -0

+     if (cfgup) {
+             BQ27XXX_MSLEEP(1);
+             ret = bq27xxx_battery_set_cfgupdate(di, 0);
+             if (ret < 0)
+                     return ret;
+     } else {
+             BQ27XXX_MSLEEP(100); /* flash DM updates in <100ms */
+     }
+
+     buf->dirty = false;
+
+     return 0;
+
+out:
+     if (cfgup)
+             bq27xxx_battery_set_cfgupdate(di, 0);
+
+     dev_err(di->dev, "bus error writing chip memory: %d\n", ret);
+     return ret;
+}
+
 /*
  * Return the battery State-of-Charge
  * Or < 0 if something fails.

include/linux/power/bq27xxx_battery.h +1 -0

index c3369fa..b1defb8 100644
@@ -64,6 +64,7 @@ struct bq27xxx_device_info {
      int id;
      enum bq27xxx_chip chip;
      const char *name;
+     u32 unseal_key;
      struct bq27xxx_access_methods bus;
      struct bq27xxx_reg_cache cache;
      int charge_design_full;

Quoted 337 lines · Liam Breck

Quoted 335 lines · Andrew F. Davis

Quoted 321 lines · Liam Breck

From: Liam Breck <[email protected]>

Add these to enable read/write of chip data memory RAM/NVM/flash:
bq27xxx_battery_seal()
bq27xxx_battery_unseal() bq27xxx_battery_set_cfgupdate() bq27xxx_battery_read_dm_block() bq27xxx_battery_write_dm_block() bq27xxx_battery_checksum_dm_block()

Signed-off-by Matt Ranostay <[email protected]>

Signed-off-by Liam Breck <[email protected]>

---
 drivers/power/supply/bq27xxx_battery.c | 253 +++++++++++++++++++++++++++++++++
 include/linux/power/bq27xxx_battery.h  |   1 +
 2 files changed, 254 insertions(+)

drivers/power/supply/bq27xxx_battery.c +146 -0

index a11dfad..8ab184c 100644
@@ -5,6 +5,7 @@
  * Copyright (C) 2008 Eurotech S.p.A. <[email protected]>
  * Copyright (C) 2010-2011 Lars-Peter Clausen <[email protected]>
  * Copyright (C) 2011 Pali Rohár <[email protected]>
+ * Copyright (C) 2017 Liam Breck <[email protected]>
  *
  * Based on a previous work by Copyright (C) 2008 Texas Instruments, Inc.
  *

@@ -65,6 +66,7 @@
 #define BQ27XXX_FLAG_DSC     BIT(0)
 #define BQ27XXX_FLAG_SOCF    BIT(1) /* State-of-Charge threshold final */
 #define BQ27XXX_FLAG_SOC1    BIT(2) /* State-of-Charge threshold 1 */
+#define BQ27XXX_FLAG_CFGUP   BIT(4)
 #define BQ27XXX_FLAG_FC              BIT(9)
 #define BQ27XXX_FLAG_OTD     BIT(14)
 #define BQ27XXX_FLAG_OTC     BIT(15)

@@ -78,6 +80,12 @@
 #define BQ27000_FLAG_FC              BIT(5)
 #define BQ27000_FLAG_CHGS    BIT(7) /* Charge state flag */
 
+/* control register params */
+#define BQ27XXX_SEALED                       0x20
+#define BQ27XXX_SET_CFGUPDATE                0x13
+#define BQ27XXX_SOFT_RESET           0x42
+#define BQ27XXX_RESET                        0x41
+
 #define BQ27XXX_RS                   (20) /* Resistor sense mOhm */
 #define BQ27XXX_POWER_CONSTANT               (29200) /* 29.2 µV^2 * 1000 */
 #define BQ27XXX_CURRENT_CONSTANT     (3570) /* 3.57 µV * 1000 */

@@ -108,9 +116,21 @@ enum bq27xxx_reg_index {
      BQ27XXX_REG_SOC,        /* State-of-Charge */
      BQ27XXX_REG_DCAP,       /* Design Capacity */
      BQ27XXX_REG_AP,         /* Average Power */
+     BQ27XXX_DM_CTRL,        /* Block Data Control */
+     BQ27XXX_DM_CLASS,       /* Data Class */
+     BQ27XXX_DM_BLOCK,       /* Data Block */
+     BQ27XXX_DM_DATA,        /* Block Data */
+     BQ27XXX_DM_CKSUM,       /* Block Data Checksum */
      BQ27XXX_REG_MAX,        /* sentinel */
 };
 
+#define BQ27XXX_DM_REG_ROWS \
+     [BQ27XXX_DM_CTRL] = 0x61,  \
+     [BQ27XXX_DM_CLASS] = 0x3e, \
+     [BQ27XXX_DM_BLOCK] = 0x3f, \
+     [BQ27XXX_DM_DATA] = 0x40,  \
+     [BQ27XXX_DM_CKSUM] = 0x60
+
 /* Register mappings */
 static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
      [BQ27000] = {

@@ -131,6 +151,11 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x0b,
              [BQ27XXX_REG_DCAP] = 0x76,
              [BQ27XXX_REG_AP] = 0x24,
+             [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
      },
      [BQ27010] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -150,6 +175,11 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x0b,
              [BQ27XXX_REG_DCAP] = 0x76,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
+             [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
      },
      [BQ2750X] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -169,6 +199,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ2751X] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -188,6 +219,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = 0x2e,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27500] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -207,6 +239,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G1] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -226,6 +259,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G2] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -245,6 +279,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27510G3] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -264,6 +299,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = 0x2e,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G1] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -283,6 +319,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G2] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -302,6 +339,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G3] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -321,6 +359,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27520G4] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -340,6 +379,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x20,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27530] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -359,6 +399,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27541] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -378,6 +419,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27545] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -397,6 +439,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x2c,
              [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
              [BQ27XXX_REG_AP] = 0x24,
+             BQ27XXX_DM_REG_ROWS,
      },
      [BQ27421] = {
              [BQ27XXX_REG_CTRL] = 0x00,

@@ -416,6 +459,7 @@ static u8 bq27xxx_regs[][BQ27XXX_REG_MAX] = {
              [BQ27XXX_REG_SOC] = 0x1c,
              [BQ27XXX_REG_DCAP] = 0x3c,
              [BQ27XXX_REG_AP] = 0x18,
+             BQ27XXX_DM_REG_ROWS,
      },
 };
 

@@ -757,6 +801,28 @@ static struct {
 static DEFINE_MUTEX(bq27xxx_list_lock);
 static LIST_HEAD(bq27xxx_battery_devices);
 
+#define BQ27XXX_MSLEEP(i) usleep_range((i)*1000, (i)*1000+500)
+
+#define BQ27XXX_DM_SZ        32
+
+/**
+ * struct bq27xxx_dm_buf - chip data memory buffer
+ * @class: data memory subclass_id
+ * @block: data memory block number
+ * @data: data from/for the block
+ * @has_data: true if data has been filled by read
+ * @dirty: true if data has changed since last read/write
+ *
+ * Encapsulates info required to manage chip data memory blocks.
+ */
+struct bq27xxx_dm_buf {
+     u8 class;
+     u8 block;
+     u8 data[BQ27XXX_DM_SZ];
+     bool has_data, dirty;
+};
+
+
 static int poll_interval_param_set(const char *val, const struct kernel_param *kp)
 {
      struct bq27xxx_device_info *di;

@@ -864,6 +930,193 @@ static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in
      return ret;
 }
 
+static int bq27xxx_battery_seal(struct bq27xxx_device_info *di)
+{
+     int ret;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, BQ27XXX_SEALED, false);
+     if (ret < 0) {
+             dev_err(di->dev, "bus error on seal: %d\n", ret);
+             return ret;
+     }
+
+     return 0;
+}
+
+static int bq27xxx_battery_unseal(struct bq27xxx_device_info *di)
+{
+     int ret;
+
+     if (di->unseal_key == 0) {
+             dev_err(di->dev, "unseal failed due to missing key\n");
+             return -EINVAL;
+     }
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)(di->unseal_key >> 16), false);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)di->unseal_key, false);
+     if (ret < 0)
+             goto out;
+
+     return 0;
+
+out:
+     dev_err(di->dev, "bus error on unseal: %d\n", ret);
+     return ret;
+}
+
+static u8 bq27xxx_battery_checksum_dm_block(struct bq27xxx_dm_buf *buf)
+{
+     u16 sum = 0;
+     int i;
+
+     for (i = 0; i < BQ27XXX_DM_SZ; i++)
+             sum += buf->data[i];
+     sum &= 0xff;
+
+     return 0xff - sum;
+}
+
+static int bq27xxx_battery_read_dm_block(struct bq27xxx_device_info *di,
+                                      struct bq27xxx_dm_buf *buf)
+{
+     int ret;
+
+     buf->has_data = false;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
+     if (ret < 0)
+             goto out;
+
+     BQ27XXX_MSLEEP(1);
+
+     ret = bq27xxx_read_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_read(di, BQ27XXX_DM_CKSUM, true);
+     if (ret < 0)
+             goto out;
+
+     if ((u8)ret != bq27xxx_battery_checksum_dm_block(buf)) {
+             ret = -EINVAL;
+             goto out;
+     }
+
+     buf->has_data = true;

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1022

Quoted 10 lines

drivers/power/supply/bq27xxx_battery.c +10 -0

+     buf->dirty = false;
+
+     return 0;
+
+out:
+     dev_err(di->dev, "bus error reading chip memory: %d\n", ret);
+     return ret;
+}
+
+static int bq27xxx_battery_set_cfgupdate(struct bq27xxx_device_info *di, u16 state)

Why do you pass in a flag but treat it like a bool? This whole function needs to be re-factored.

Quoted 2 lines

How's this look?

Better, how about we store the mask at the start, might improve readability, something like this would be nice:

static int bq27xxx_battery_cfgupdate_priv(struct bq27xxx_device_info *di, bool active)

{
        const int limit = 100;
        int ret, try = 0;
        u16 command = active ? BQ27XXX_SET_CFGUPDATE : BQ27XXX_SOFT_RESET;

        ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, command, false);
        if (ret < 0)
                return ret;

        do {
                BQ27XXX_MSLEEP(25);
                ret = bq27xxx_read(di, BQ27XXX_REG_FLAGS, false);
                if (ret < 0)
                        return ret;

                if (try++ > limit) {
                        dev_err(di->dev, "timed out waiting for cfgupdate flag %d\n", active);
                        return -EINVAL;
                }
        } while (!!(ret & BQ27XXX_FLAG_CFGUP) != active);

        return 0;
}

Quoted 173 lines

static int bq27xxx_battery_cfgupdate_priv(struct bq27xxx_device_info *di, bool active)

{
        const int limit = 100;
        int ret, try = limit;

        ret = bq27xxx_write(di, BQ27XXX_REG_CTRL,
                            active ? BQ27XXX_SET_CFGUPDATE : BQ27XXX_SOFT_RESET,
                            false);
        if (ret < 0)
                return ret;

        do {
                BQ27XXX_MSLEEP(25);
                ret = bq27xxx_read(di, BQ27XXX_REG_FLAGS, false);
                if (ret < 0)
                        return ret;
        } while (!!(ret & BQ27XXX_FLAG_CFGUP) != active && --try);

        if (!try) {
                dev_err(di->dev, "timed out waiting for cfgupdate flag
%d\n", active);
                return -EINVAL;
        }

        if (limit - try > 3)
                dev_warn(di->dev, "cfgupdate %d, retries %d\n",

active, limit - try);

        return 0;
}

static inline int bq27xxx_battery_set_cfgupdate(struct bq27xxx_device_info *di)

{
        int ret = bq27xxx_battery_cfgupdate_priv(di, true);
        if (ret < 0 && ret != -EINVAL)
                dev_err(di->dev, "bus error on set_cfgupdate: %d\n", ret);

        return ret;
}

static inline int bq27xxx_battery_soft_reset(struct bq27xxx_device_info *di)

{
        int ret = bq27xxx_battery_cfgupdate_priv(di, false);
        if (ret < 0 && ret != -EINVAL)
                dev_err(di->dev, "bus error on soft_reset: %d\n", ret);

        return ret;
}

Quoted 121 lines

Quoted 26 lines

drivers/power/supply/bq27xxx_battery.c +26 -0

+{
+     const int limit = 100;
+     int ret, try = limit;
+
+     ret = bq27xxx_write(di, BQ27XXX_REG_CTRL,
+                         state ? BQ27XXX_SET_CFGUPDATE : BQ27XXX_SOFT_RESET,
+                         false);
+     if (ret < 0)
+             goto out;
+
+     do {
+             BQ27XXX_MSLEEP(25);
+             ret = di->bus.read(di, di->regs[BQ27XXX_REG_FLAGS], false);
+             if (ret < 0)
+                     goto out;
+     } while ((ret & BQ27XXX_FLAG_CFGUP) != state && --try);
+
+     if (!try) {
+             dev_err(di->dev, "timed out waiting for cfgupdate flag %d\n", !!state);
+             return -EINVAL;
+     }
+
+     if (limit-try > 3)
+             dev_warn(di->dev, "cfgupdate %d, retries %d\n", !!state, limit-try);
+
+     return 0;

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1058

Quoted 10 lines

drivers/power/supply/bq27xxx_battery.c +10 -0

+
+out:
+     dev_err(di->dev, "bus error on %s: %d\n", state ? "set_cfgupdate" : "soft_reset", ret);
+     return ret;
+}
+
+static int bq27xxx_battery_write_dm_block(struct bq27xxx_device_info *di,
+                                       struct bq27xxx_dm_buf *buf)
+{
+     bool cfgup = di->chip == BQ27421; /* assume group supports cfgupdate */

Group? This is a single chip ID.

Quoted 30 lines

drivers/power/supply/bq27xxx_battery.c +30 -0

+     int ret;
+
+     if (!buf->dirty)
+             return 0;
+
+     if (cfgup) {
+             ret = bq27xxx_battery_set_cfgupdate(di, BQ27XXX_FLAG_CFGUP);
+             if (ret < 0)
+                     return ret;
+     }
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CTRL, 0, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
+     if (ret < 0)
+             goto out;
+
+     BQ27XXX_MSLEEP(1);
+
+     ret = bq27xxx_write_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
+     if (ret < 0)
+             goto out;
+
+     ret = bq27xxx_write(di, BQ27XXX_DM_CKSUM,

drivers/power/supply/bq27xxx_battery.c static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_in · line 1098

Quoted 10 lines

drivers/power/supply/bq27xxx_battery.c +10 -0

+                         bq27xxx_battery_checksum_dm_block(buf), true);
+     if (ret < 0)
+             goto out;
+
+     /* DO NOT read BQ27XXX_DM_CKSUM here to verify it! That may cause NVM
+      * corruption on the '425 chip (and perhaps others), which can damage
+      * the chip. See TI bqtool for what not to do:
+      * http://git.ti.com/bms-linux/bqtool/blobs/master/gauge.c#line328
+      */
+

Again, this is not needed, I'm sorry you fried your chip somehow but this program is not incorrect, it is used by our customers all the time and does not fry chips, drop this comment.

Quoted 37 lines

drivers/power/supply/bq27xxx_battery.c +21 -0

+     if (cfgup) {
+             BQ27XXX_MSLEEP(1);
+             ret = bq27xxx_battery_set_cfgupdate(di, 0);
+             if (ret < 0)
+                     return ret;
+     } else {
+             BQ27XXX_MSLEEP(100); /* flash DM updates in <100ms */
+     }
+
+     buf->dirty = false;
+
+     return 0;
+
+out:
+     if (cfgup)
+             bq27xxx_battery_set_cfgupdate(di, 0);
+
+     dev_err(di->dev, "bus error writing chip memory: %d\n", ret);
+     return ret;
+}
+
 /*
  * Return the battery State-of-Charge
  * Or < 0 if something fails.

include/linux/power/bq27xxx_battery.h +1 -0

index c3369fa..b1defb8 100644
@@ -64,6 +64,7 @@ struct bq27xxx_device_info {
      int id;
      enum bq27xxx_chip chip;
      const char *name;
+     u32 unseal_key;
      struct bq27xxx_access_methods bus;
      struct bq27xxx_reg_cache cache;
      int charge_design_full;

From: Liam Breck <[email protected]>

Previously there was no way to configure these chips in the event that the defaults didn't match the battery in question.

For chips with RAM data memory (and also those with flash/NVM data memory if CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is defined and the user has not set module param dt_monitored_battery_updates_nvm=0) we now call power_supply_get_battery_info(), check its values, and write battery properties to chip data memory if there is a dm_regs table for the chip.

Signed-off-by Matt Ranostay <[email protected]>

Signed-off-by Liam Breck <[email protected]>

---
 drivers/power/supply/Kconfig           |   9 ++
 drivers/power/supply/bq27xxx_battery.c | 199 ++++++++++++++++++++++++++++++++-
 include/linux/power/bq27xxx_battery.h  |   2 +
 3 files changed, 209 insertions(+), 1 deletion(-)

drivers/power/supply/Kconfig +9 -0

index 76806a0..85e2fb2 100644
@@ -178,6 +178,15 @@ config BATTERY_BQ27XXX_I2C
 	  Say Y here to enable support for batteries with BQ27xxx chips
 	  connected over an I2C bus.
 
+config BATTERY_BQ27XXX_DT_UPDATES_NVM
+	bool "BQ27xxx support for update of NVM/flash data memory"
+	depends on BATTERY_BQ27XXX_I2C
+	help
+	  Say Y here to enable devicetree monitored-battery config to update
+	  NVM/flash data memory. Only enable this option for devices with a
+	  fuel gauge mounted on the circuit board, and a battery that cannot
+	  be replaced with one of a different type.
+
 config BATTERY_DA9030
 	tristate "DA9030 battery driver"
 	depends on PMIC_DA903X

drivers/power/supply/bq27xxx_battery.c +31 -0

index 8ab184c..06f15da 100644
@@ -805,6 +805,13 @@ static LIST_HEAD(bq27xxx_battery_devices);
 
 #define BQ27XXX_DM_SZ	32
 
+struct bq27xxx_dm_reg {
+	u8 subclass_id;
+	u8 offset;
+	u8 bytes;
+	u16 min, max;
+};
+
 /**
  * struct bq27xxx_dm_buf - chip data memory buffer
  * @class: data memory subclass_id

@@ -822,6 +829,43 @@ struct bq27xxx_dm_buf {
 	bool has_data, dirty;
 };
 
+#define BQ27XXX_DM_BUF(di, i) { \
+	.class = (di)->dm_regs[i].subclass_id, \
+	.block = (di)->dm_regs[i].offset / BQ27XXX_DM_SZ, \
+}
+
+static inline u16 *bq27xxx_dm_reg_ptr(struct bq27xxx_dm_buf *buf,
+				      struct bq27xxx_dm_reg *reg)
+{
+	if (buf->class == reg->subclass_id &&
+	    buf->block == reg->offset / BQ27XXX_DM_SZ)
+		return (u16 *) (buf->data + reg->offset % BQ27XXX_DM_SZ);
+
+	return NULL;
+}
+
+enum bq27xxx_dm_reg_id {
+	BQ27XXX_DM_DESIGN_CAPACITY = 0,
+	BQ27XXX_DM_DESIGN_ENERGY,
+	BQ27XXX_DM_TERMINATE_VOLTAGE,
+};
+
+static const char * const bq27xxx_dm_reg_name[] = {
+	[BQ27XXX_DM_DESIGN_CAPACITY] = "design-capacity",
+	[BQ27XXX_DM_DESIGN_ENERGY] = "design-energy",

drivers/power/supply/bq27xxx_battery.c +157 -1

+#else
+static bool bq27xxx_dt_to_nvm = false;
+#endif
 
 static int poll_interval_param_set(const char *val, const struct kernel_param *kp)
 {

@@ -1019,6 +1063,51 @@ static int bq27xxx_battery_read_dm_block(struct bq27xxx_device_info *di,
 	return ret;
 }
 
+static void bq27xxx_battery_update_dm_block(struct bq27xxx_device_info *di,
+					    struct bq27xxx_dm_buf *buf,
+					    enum bq27xxx_dm_reg_id reg_id,
+					    unsigned int val)
+{
+	struct bq27xxx_dm_reg *reg = &di->dm_regs[reg_id];
+	const char *str = bq27xxx_dm_reg_name[reg_id];
+	u16 *prev = bq27xxx_dm_reg_ptr(buf, reg);
+
+	if (prev == NULL) {
+		dev_warn(di->dev, "buffer does not match %s dm spec\n", str);
+		return;
+	}
+
+	if (reg->bytes != 2) {
+		dev_warn(di->dev, "%s dm spec has unsupported byte size\n", str);
+		return;
+	}
+
+	if (!buf->has_data)
+		return;
+
+	if (be16_to_cpup(prev) == val) {
+		dev_info(di->dev, "%s has %u\n", str, val);
+		return;
+	}
+
+	if (!di->ram_chip && !bq27xxx_dt_to_nvm) {
+		/* devicetree and NVM differ; defer to NVM */
+		dev_warn(di->dev, "%s has %u; update to %u disallowed "
+#ifdef CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM
+			 "by dt_monitored_battery_updates_nvm=0"
+#else
+			 "for flash/NVM data memory"
+#endif
+			 "\n", str, be16_to_cpup(prev), val);
+		return;
+	}
+
+	dev_info(di->dev, "update %s to %u\n", str, val);
+
+	*prev = cpu_to_be16(val);
+	buf->dirty = true;
+}
+
 static int bq27xxx_battery_set_cfgupdate(struct bq27xxx_device_info *di, u16 state)
 {
 	const int limit = 100;

@@ -1117,6 +1206,103 @@ static int bq27xxx_battery_write_dm_block(struct bq27xxx_device_info *di,
 	return ret;
 }
 
+static void bq27xxx_battery_set_config(struct bq27xxx_device_info *di,
+				       struct power_supply_battery_info *info)
+{
+	struct bq27xxx_dm_buf bd = BQ27XXX_DM_BUF(di, BQ27XXX_DM_DESIGN_CAPACITY);
+	struct bq27xxx_dm_buf bt = BQ27XXX_DM_BUF(di, BQ27XXX_DM_TERMINATE_VOLTAGE);
+	bool updated;
+
+	if (bq27xxx_battery_unseal(di) < 0)
+		return;
+
+	if (info->charge_full_design_uah != -EINVAL &&
+	    info->energy_full_design_uwh != -EINVAL) {
+		bq27xxx_battery_read_dm_block(di, &bd);
+		/* assume design energy & capacity are in same block */
+		bq27xxx_battery_update_dm_block(di, &bd,
+					BQ27XXX_DM_DESIGN_CAPACITY,
+					info->charge_full_design_uah / 1000);
+		bq27xxx_battery_update_dm_block(di, &bd,
+					BQ27XXX_DM_DESIGN_ENERGY,
+					info->energy_full_design_uwh / 1000);
+	}
+
+	if (info->voltage_min_design_uv != -EINVAL) {
+		bool same = bd.class == bt.class && bd.block == bt.block;
+		if (!same)
+			bq27xxx_battery_read_dm_block(di, &bt);
+		bq27xxx_battery_update_dm_block(di, same ? &bd : &bt,
+					BQ27XXX_DM_TERMINATE_VOLTAGE,
+					info->voltage_min_design_uv / 1000);
+	}
+
+	updated = bd.dirty || bt.dirty;
+
+	bq27xxx_battery_write_dm_block(di, &bd);
+	bq27xxx_battery_write_dm_block(di, &bt);
+
+	bq27xxx_battery_seal(di);
+
+	if (updated && di->chip != BQ27421) { /* not a cfgupdate chip, so reset */
+		bq27xxx_write(di, BQ27XXX_REG_CTRL, BQ27XXX_RESET, false);
+		BQ27XXX_MSLEEP(300); /* reset time is not documented */
+	}
+	/* assume bq27xxx_battery_update() is called hereafter */
+}
+
+static void bq27xxx_battery_settings(struct bq27xxx_device_info *di)
+{
+	struct power_supply_battery_info info = {};
+	unsigned int min, max;
+
+	if (power_supply_get_battery_info(di->bat, &info) < 0)
+		return;
+
+	if (!di->dm_regs) {
+		dev_warn(di->dev, "data memory update not supported for chip\n");
+		return;
+	}
+
+	if (info.energy_full_design_uwh != info.charge_full_design_uah) {
+		if (info.energy_full_design_uwh == -EINVAL)
+			dev_warn(di->dev, "missing battery:energy-full-design-microwatt-hours\n");
+		else if (info.charge_full_design_uah == -EINVAL)
+			dev_warn(di->dev, "missing battery:charge-full-design-microamp-hours\n");
+	}
+
+	/* assume min == 0 */
+	max = di->dm_regs[BQ27XXX_DM_DESIGN_ENERGY].max;
+	if (info.energy_full_design_uwh > max * 1000) {
+		dev_err(di->dev, "invalid battery:energy-full-design-microwatt-hours %d\n",
+			info.energy_full_design_uwh);
+		info.energy_full_design_uwh = -EINVAL;
+	}
+
+	/* assume min == 0 */
+	max = di->dm_regs[BQ27XXX_DM_DESIGN_CAPACITY].max;
+	if (info.charge_full_design_uah > max * 1000) {
+		dev_err(di->dev, "invalid battery:charge-full-design-microamp-hours %d\n",
+			info.charge_full_design_uah);
+		info.charge_full_design_uah = -EINVAL;
+	}
+
+	min = di->dm_regs[BQ27XXX_DM_TERMINATE_VOLTAGE].min;
+	max = di->dm_regs[BQ27XXX_DM_TERMINATE_VOLTAGE].max;
+	if ((info.voltage_min_design_uv < min * 1000 ||
+	     info.voltage_min_design_uv > max * 1000) &&
+	     info.voltage_min_design_uv != -EINVAL) {
+		dev_err(di->dev, "invalid battery:voltage-min-design-microvolt %d\n",
+			info.voltage_min_design_uv);
+		info.voltage_min_design_uv = -EINVAL;
+	}
+
+	if ((info.energy_full_design_uwh != -EINVAL &&
+	     info.charge_full_design_uah != -EINVAL) ||
+	     info.voltage_min_design_uv  != -EINVAL)
+		bq27xxx_battery_set_config(di, &info);
+}
+
 /*
  * Return the battery State-of-Charge
  * Or < 0 if something fails.

@@ -1634,6 +1820,13 @@ static int bq27xxx_battery_get_property(struct power_supply *psy,
 	case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
 		ret = bq27xxx_simple_value(di->charge_design_full, val);
 		break;
+	/*
+	 * TODO: Implement these to make registers set from
+	 * power_supply_battery_info visible in sysfs.
+	 */
+	case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:
+	case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+		return -EINVAL;
 	case POWER_SUPPLY_PROP_CYCLE_COUNT:
 		ret = bq27xxx_simple_value(di->cache.cycle_count, val);
 		break;

@@ -1667,7 +1860,10 @@ static void bq27xxx_external_power_changed(struct power_supply *psy)
 int bq27xxx_battery_setup(struct bq27xxx_device_info *di)
 {
 	struct power_supply_desc *psy_desc;
-	struct power_supply_config psy_cfg = { .drv_data = di, };
+	struct power_supply_config psy_cfg = {
+		.of_node = di->dev->of_node,
+		.drv_data = di,
+	};
 
 	INIT_DELAYED_WORK(&di->work, bq27xxx_battery_poll);
 	mutex_init(&di->lock);

@@ -1692,6 +1888,7 @@ int bq27xxx_battery_setup(struct bq27xxx_device_info *di)
 
 	dev_info(di->dev, "support ver. %s enabled\n", DRIVER_VERSION);
 
+	bq27xxx_battery_settings(di);
 	bq27xxx_battery_update(di);
 
 	mutex_lock(&bq27xxx_list_lock);

include/linux/power/bq27xxx_battery.h +2 -0

index b1defb8..11e1168 100644
@@ -63,7 +63,9 @@ struct bq27xxx_device_info {
 	struct device *dev;
 	int id;
 	enum bq27xxx_chip chip;
+	bool ram_chip;
 	const char *name;
+	struct bq27xxx_dm_reg *dm_regs;
 	u32 unseal_key;
 	struct bq27xxx_access_methods bus;
 	struct bq27xxx_reg_cache cache;

Quoted 93 lines · Liam Breck

From: Liam Breck <[email protected]>

Previously there was no way to configure these chips in the event that the defaults didn't match the battery in question.

For chips with RAM data memory (and also those with flash/NVM data memory if CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is defined and the user has not set module param dt_monitored_battery_updates_nvm=0) we now call power_supply_get_battery_info(), check its values, and write battery properties to chip data memory if there is a dm_regs table for the chip.

Signed-off-by Matt Ranostay <[email protected]>

Signed-off-by Liam Breck <[email protected]>

---
 drivers/power/supply/Kconfig           |   9 ++
 drivers/power/supply/bq27xxx_battery.c | 199 ++++++++++++++++++++++++++++++++-
 include/linux/power/bq27xxx_battery.h  |   2 +
 3 files changed, 209 insertions(+), 1 deletion(-)

drivers/power/supply/Kconfig +9 -0

index 76806a0..85e2fb2 100644
@@ -178,6 +178,15 @@ config BATTERY_BQ27XXX_I2C
        Say Y here to enable support for batteries with BQ27xxx chips
        connected over an I2C bus.
 
+config BATTERY_BQ27XXX_DT_UPDATES_NVM
+     bool "BQ27xxx support for update of NVM/flash data memory"
+     depends on BATTERY_BQ27XXX_I2C
+     help
+       Say Y here to enable devicetree monitored-battery config to update
+       NVM/flash data memory. Only enable this option for devices with a
+       fuel gauge mounted on the circuit board, and a battery that cannot
+       be replaced with one of a different type.
+
 config BATTERY_DA9030
      tristate "DA9030 battery driver"
      depends on PMIC_DA903X

drivers/power/supply/bq27xxx_battery.c +39 -0

index 8ab184c..06f15da 100644
@@ -805,6 +805,13 @@ static LIST_HEAD(bq27xxx_battery_devices);
 
 #define BQ27XXX_DM_SZ        32
 
+struct bq27xxx_dm_reg {
+     u8 subclass_id;
+     u8 offset;
+     u8 bytes;
+     u16 min, max;
+};
+
 /**
  * struct bq27xxx_dm_buf - chip data memory buffer
  * @class: data memory subclass_id

@@ -822,6 +829,43 @@ struct bq27xxx_dm_buf {
      bool has_data, dirty;
 };
 
+#define BQ27XXX_DM_BUF(di, i) { \
+     .class = (di)->dm_regs[i].subclass_id, \
+     .block = (di)->dm_regs[i].offset / BQ27XXX_DM_SZ, \
+}
+
+static inline u16 *bq27xxx_dm_reg_ptr(struct bq27xxx_dm_buf *buf,
+                                   struct bq27xxx_dm_reg *reg)
+{
+     if (buf->class == reg->subclass_id &&
+         buf->block == reg->offset / BQ27XXX_DM_SZ)
+             return (u16 *) (buf->data + reg->offset % BQ27XXX_DM_SZ);
+
+     return NULL;
+}
+
+enum bq27xxx_dm_reg_id {
+     BQ27XXX_DM_DESIGN_CAPACITY = 0,
+     BQ27XXX_DM_DESIGN_ENERGY,
+     BQ27XXX_DM_TERMINATE_VOLTAGE,
+};
+
+static const char * const bq27xxx_dm_reg_name[] = {
+     [BQ27XXX_DM_DESIGN_CAPACITY] = "design-capacity",
+     [BQ27XXX_DM_DESIGN_ENERGY] = "design-energy",
+     [BQ27XXX_DM_TERMINATE_VOLTAGE] = "terminate-voltage",
+};
+
+
+#ifdef CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM
+static bool bq27xxx_dt_to_nvm = true;
+
+module_param_named(dt_monitored_battery_updates_nvm, bq27xxx_dt_to_nvm, bool, 0444);

drivers/power/supply/bq27xxx_battery.c struct bq27xxx_dm_buf { · line 865

Quoted 2 lines

drivers/power/supply/bq27xxx_battery.c +2 -0

+MODULE_PARM_DESC(dt_monitored_battery_updates_nvm,
+     "Devicetree monitored-battery config updates NVM/flash data memory, if present. Default is 1/y.");

As before, the default should not be y, this is a rare case and I can't see it being useful or wanted by anyone but device manufacturers. I don't want everyones chip's factory programmed NVM overwritten by accident when someone compiles and ships a kernel with BATTERY_BQ27XXX_DT_UPDATES_NVM=y

Quoted 211 lines

drivers/power/supply/bq27xxx_battery.c +157 -1

+#else
+static bool bq27xxx_dt_to_nvm = false;
+#endif
 
 static int poll_interval_param_set(const char *val, const struct kernel_param *kp)
 {

@@ -1019,6 +1063,51 @@ static int bq27xxx_battery_read_dm_block(struct bq27xxx_device_info *di,
      return ret;
 }
 
+static void bq27xxx_battery_update_dm_block(struct bq27xxx_device_info *di,
+                                         struct bq27xxx_dm_buf *buf,
+                                         enum bq27xxx_dm_reg_id reg_id,
+                                         unsigned int val)
+{
+     struct bq27xxx_dm_reg *reg = &di->dm_regs[reg_id];
+     const char *str = bq27xxx_dm_reg_name[reg_id];
+     u16 *prev = bq27xxx_dm_reg_ptr(buf, reg);
+
+     if (prev == NULL) {
+             dev_warn(di->dev, "buffer does not match %s dm spec\n", str);
+             return;
+     }
+
+     if (reg->bytes != 2) {
+             dev_warn(di->dev, "%s dm spec has unsupported byte size\n", str);
+             return;
+     }
+
+     if (!buf->has_data)
+             return;
+
+     if (be16_to_cpup(prev) == val) {
+             dev_info(di->dev, "%s has %u\n", str, val);
+             return;
+     }
+
+     if (!di->ram_chip && !bq27xxx_dt_to_nvm) {
+             /* devicetree and NVM differ; defer to NVM */
+             dev_warn(di->dev, "%s has %u; update to %u disallowed "
+#ifdef CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM
+                      "by dt_monitored_battery_updates_nvm=0"
+#else
+                      "for flash/NVM data memory"
+#endif
+                      "\n", str, be16_to_cpup(prev), val);
+             return;
+     }
+
+     dev_info(di->dev, "update %s to %u\n", str, val);
+
+     *prev = cpu_to_be16(val);
+     buf->dirty = true;
+}
+
 static int bq27xxx_battery_set_cfgupdate(struct bq27xxx_device_info *di, u16 state)
 {
      const int limit = 100;

@@ -1117,6 +1206,103 @@ static int bq27xxx_battery_write_dm_block(struct bq27xxx_device_info *di,
      return ret;
 }
 
+static void bq27xxx_battery_set_config(struct bq27xxx_device_info *di,
+                                    struct power_supply_battery_info *info)
+{
+     struct bq27xxx_dm_buf bd = BQ27XXX_DM_BUF(di, BQ27XXX_DM_DESIGN_CAPACITY);
+     struct bq27xxx_dm_buf bt = BQ27XXX_DM_BUF(di, BQ27XXX_DM_TERMINATE_VOLTAGE);
+     bool updated;
+
+     if (bq27xxx_battery_unseal(di) < 0)
+             return;
+
+     if (info->charge_full_design_uah != -EINVAL &&
+         info->energy_full_design_uwh != -EINVAL) {
+             bq27xxx_battery_read_dm_block(di, &bd);
+             /* assume design energy & capacity are in same block */
+             bq27xxx_battery_update_dm_block(di, &bd,
+                                     BQ27XXX_DM_DESIGN_CAPACITY,
+                                     info->charge_full_design_uah / 1000);
+             bq27xxx_battery_update_dm_block(di, &bd,
+                                     BQ27XXX_DM_DESIGN_ENERGY,
+                                     info->energy_full_design_uwh / 1000);
+     }
+
+     if (info->voltage_min_design_uv != -EINVAL) {
+             bool same = bd.class == bt.class && bd.block == bt.block;
+             if (!same)
+                     bq27xxx_battery_read_dm_block(di, &bt);
+             bq27xxx_battery_update_dm_block(di, same ? &bd : &bt,
+                                     BQ27XXX_DM_TERMINATE_VOLTAGE,
+                                     info->voltage_min_design_uv / 1000);
+     }
+
+     updated = bd.dirty || bt.dirty;
+
+     bq27xxx_battery_write_dm_block(di, &bd);
+     bq27xxx_battery_write_dm_block(di, &bt);
+
+     bq27xxx_battery_seal(di);
+
+     if (updated && di->chip != BQ27421) { /* not a cfgupdate chip, so reset */
+             bq27xxx_write(di, BQ27XXX_REG_CTRL, BQ27XXX_RESET, false);
+             BQ27XXX_MSLEEP(300); /* reset time is not documented */
+     }
+     /* assume bq27xxx_battery_update() is called hereafter */
+}
+
+static void bq27xxx_battery_settings(struct bq27xxx_device_info *di)
+{
+     struct power_supply_battery_info info = {};
+     unsigned int min, max;
+
+     if (power_supply_get_battery_info(di->bat, &info) < 0)
+             return;
+
+     if (!di->dm_regs) {
+             dev_warn(di->dev, "data memory update not supported for chip\n");
+             return;
+     }
+
+     if (info.energy_full_design_uwh != info.charge_full_design_uah) {
+             if (info.energy_full_design_uwh == -EINVAL)
+                     dev_warn(di->dev, "missing battery:energy-full-design-microwatt-hours\n");
+             else if (info.charge_full_design_uah == -EINVAL)
+                     dev_warn(di->dev, "missing battery:charge-full-design-microamp-hours\n");
+     }
+
+     /* assume min == 0 */
+     max = di->dm_regs[BQ27XXX_DM_DESIGN_ENERGY].max;
+     if (info.energy_full_design_uwh > max * 1000) {
+             dev_err(di->dev, "invalid battery:energy-full-design-microwatt-hours %d\n",
+                     info.energy_full_design_uwh);
+             info.energy_full_design_uwh = -EINVAL;
+     }
+
+     /* assume min == 0 */
+     max = di->dm_regs[BQ27XXX_DM_DESIGN_CAPACITY].max;
+     if (info.charge_full_design_uah > max * 1000) {
+             dev_err(di->dev, "invalid battery:charge-full-design-microamp-hours %d\n",
+                     info.charge_full_design_uah);
+             info.charge_full_design_uah = -EINVAL;
+     }
+
+     min = di->dm_regs[BQ27XXX_DM_TERMINATE_VOLTAGE].min;
+     max = di->dm_regs[BQ27XXX_DM_TERMINATE_VOLTAGE].max;
+     if ((info.voltage_min_design_uv < min * 1000 ||
+          info.voltage_min_design_uv > max * 1000) &&
+          info.voltage_min_design_uv != -EINVAL) {
+             dev_err(di->dev, "invalid battery:voltage-min-design-microvolt %d\n",
+                     info.voltage_min_design_uv);
+             info.voltage_min_design_uv = -EINVAL;
+     }
+
+     if ((info.energy_full_design_uwh != -EINVAL &&
+          info.charge_full_design_uah != -EINVAL) ||
+          info.voltage_min_design_uv  != -EINVAL)
+             bq27xxx_battery_set_config(di, &info);
+}
+
 /*
  * Return the battery State-of-Charge
  * Or < 0 if something fails.

@@ -1634,6 +1820,13 @@ static int bq27xxx_battery_get_property(struct power_supply *psy,
      case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
              ret = bq27xxx_simple_value(di->charge_design_full, val);
              break;
+     /*
+      * TODO: Implement these to make registers set from
+      * power_supply_battery_info visible in sysfs.
+      */
+     case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:
+     case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+             return -EINVAL;
      case POWER_SUPPLY_PROP_CYCLE_COUNT:
              ret = bq27xxx_simple_value(di->cache.cycle_count, val);
              break;

@@ -1667,7 +1860,10 @@ static void bq27xxx_external_power_changed(struct power_supply *psy)
 int bq27xxx_battery_setup(struct bq27xxx_device_info *di)
 {
      struct power_supply_desc *psy_desc;
-     struct power_supply_config psy_cfg = { .drv_data = di, };
+     struct power_supply_config psy_cfg = {
+             .of_node = di->dev->of_node,
+             .drv_data = di,
+     };
 
      INIT_DELAYED_WORK(&di->work, bq27xxx_battery_poll);
      mutex_init(&di->lock);

@@ -1692,6 +1888,7 @@ int bq27xxx_battery_setup(struct bq27xxx_device_info *di)
 
      dev_info(di->dev, "support ver. %s enabled\n", DRIVER_VERSION);
 
+     bq27xxx_battery_settings(di);
      bq27xxx_battery_update(di);
 
      mutex_lock(&bq27xxx_list_lock);

include/linux/power/bq27xxx_battery.h +2 -0

index b1defb8..11e1168 100644
@@ -63,7 +63,9 @@ struct bq27xxx_device_info {
      struct device *dev;
      int id;
      enum bq27xxx_chip chip;
+     bool ram_chip;
      const char *name;
+     struct bq27xxx_dm_reg *dm_regs;
      u32 unseal_key;
      struct bq27xxx_access_methods bus;
      struct bq27xxx_reg_cache cache;