Skip to contentSkip to conversation

Staging: ccree: ssi_cipher: fix brace coding style issue

PATCH In review Ammly Fredrick 2 participants 2 messages May 13, 2017 – May 14, 2017 Staging

lore
Share & tools
lore

Ammly Fredrick

author
#0 lore raw

PATCH 12622/12622 Staging: ccree: ssi_cipher: fix brace coding style issue

Fixed some coding style issues after running scripts/checkpatch.pl

Fixed spelling in ssi_blkcipher_complete(), should be counter not couter.

Signed-off-by Ammly Fredrick <[email protected]>
---
 drivers/staging/ccree/ssi_cipher.c | 72 ++++++++++++++++++--------------------
 1 file changed, 34 insertions(+), 38 deletions(-)
drivers/staging/ccree/ssi_cipher.c +34 -38
index 664ed7e52cf2..37ed4e5133fc 100644
@@ -72,7 +72,7 @@ static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req, void __io
 static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, uint32_t size) {
 	switch (ctx_p->flow_mode){
 	case S_DIN_to_AES:
-		switch (size){
+		switch (size) {
 		case CC_AES_128_BIT_KEY_SIZE:
 		case CC_AES_192_BIT_KEY_SIZE:
 			if (likely((ctx_p->cipher_mode != DRV_CIPHER_XTS) &&

@@ -82,8 +82,8 @@ static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, uint32_t size)
 			break;
 		case CC_AES_256_BIT_KEY_SIZE:
 			return 0;
-		case (CC_AES_192_BIT_KEY_SIZE*2):
-		case (CC_AES_256_BIT_KEY_SIZE*2):
+		case (CC_AES_192_BIT_KEY_SIZE * 2):
+		case (CC_AES_256_BIT_KEY_SIZE * 2):
 			if (likely((ctx_p->cipher_mode == DRV_CIPHER_XTS) ||
 				   (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) ||
 				   (ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER)))

@@ -94,7 +94,7 @@ static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, uint32_t size)
 		}
 	case S_DIN_to_DES:
 		if (likely(size == DES3_EDE_KEY_SIZE ||
-		    size == DES_KEY_SIZE))
+	             size == DES_KEY_SIZE))
 			return 0;
 		break;
 #if SSI_CC_HAS_MULTI2

@@ -105,16 +105,15 @@ static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, uint32_t size)
 #endif
 	default:
 		break;
-
 	}
 	return -EINVAL;
 }
 
 
 static int validate_data_size(struct ssi_ablkcipher_ctx *ctx_p, unsigned int size) {
-	switch (ctx_p->flow_mode){
+	switch (ctx_p->flow_mode) {
 	case S_DIN_to_AES:
-		switch (ctx_p->cipher_mode){
+		switch (ctx_p->cipher_mode) {
 		case DRV_CIPHER_XTS:
 			if ((size >= SSI_MIN_AES_XTS_SIZE) &&
 			    (size <= SSI_MAX_AES_XTS_SIZE) && 

@@ -172,9 +171,8 @@ static unsigned int get_max_keysize(struct crypto_tfm *tfm)
 		return ssi_alg->crypto_alg.cra_ablkcipher.max_keysize;
 	}
 
-	if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_BLKCIPHER) {
+	if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_BLKCIPHER)
 		return ssi_alg->crypto_alg.cra_blkcipher.max_keysize;
-	}
 
 	return 0;
 }

@@ -199,7 +197,7 @@ static int ssi_blkcipher_init(struct crypto_tfm *tfm)
 	dev = &ctx_p->drvdata->plat_dev->dev;
 
 	/* Allocate key buffer, cache line aligned */
-	ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL|GFP_DMA);
+	ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL | GFP_DMA);
 	if (!ctx_p->user.key) {
 		SSI_LOG_ERR("Allocating key buffer in context failed\n");
 		rc = -ENOMEM;

@@ -260,11 +258,11 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm)
 }
 
 
-typedef struct tdes_keys{
+typedef struct tdes_keys {
         u8      key1[DES_KEY_SIZE];
         u8      key2[DES_KEY_SIZE];
         u8      key3[DES_KEY_SIZE];
-}tdes_keys_t;
+} tdes_keys_t;
 
 static const u8 zero_buff[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 
                                0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,

@@ -294,9 +292,9 @@ static int ssi_fips_verify_xts_keys(const u8 *key, unsigned int keylen)
         /* Weak key is define as key that its first half (128/256 lsb) equals its second half (128/256 msb) */
         int singleKeySize = keylen >> 1;
 
-	if (unlikely(memcmp(key, &key[singleKeySize], singleKeySize) == 0)) {
+	if (unlikely(memcmp(key, &key[singleKeySize], singleKeySize) == 0))
 		return -ENOEXEC;
-	}
+
 #endif /* CCREE_FIPS_SUPPORT */
 
         return 0;

@@ -340,12 +338,12 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm,
 
 #if SSI_CC_HAS_MULTI2
 	/*last byte of key buffer is round number and should not be a part of key size*/
-	if (ctx_p->flow_mode == S_DIN_to_MULTI2) {
-		keylen -=1;
-	}
+	if (ctx_p->flow_mode == S_DIN_to_MULTI2)
+		keylen -= 1;
+	
 #endif /*SSI_CC_HAS_MULTI2*/
 
-	if (unlikely(validate_keys_sizes(ctx_p,keylen) != 0)) {
+	if (unlikely(validate_keys_sizes(ctx_p, keylen) != 0)) {
 		SSI_LOG_ERR("Unsupported key size %d.\n", keylen);
 		crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
 		return -EINVAL;

@@ -449,7 +447,7 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm,
 	}
 	dma_sync_single_for_device(dev, ctx_p->user.key_dma_addr, 
 					max_key_buf_size, DMA_TO_DEVICE);
-	SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx_p->user.key_dma_addr ,max_key_buf_size);
+	SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx_p->user.key_dma_addr, max_key_buf_size);
 	ctx_p->keylen = keylen;
 	
 	END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_1);

@@ -497,7 +495,7 @@ ssi_blkcipher_create_setup_desc(
 		HW_DESC_SET_FLOW_MODE(&desc[*seq_size], flow_mode);
 		HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], cipher_mode);
 		if ((cipher_mode == DRV_CIPHER_CTR) || 
-		    (cipher_mode == DRV_CIPHER_OFB) ) {
+		    (cipher_mode == DRV_CIPHER_OFB)) {
 			HW_DESC_SET_SETUP_MODE(&desc[*seq_size],
 					       SETUP_LOAD_STATE1);
 		} else {

@@ -544,10 +542,10 @@ ssi_blkcipher_create_setup_desc(
 			HW_DESC_SET_HW_CRYPTO_KEY(&desc[*seq_size], ctx_p->hw.key1_slot);
 		} else {
 			HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI,
-					     key_dma_addr, key_len/2,
+					     key_dma_addr, key_len / 2,
 					     NS_BIT);
 		}
-		HW_DESC_SET_KEY_SIZE_AES(&desc[*seq_size], key_len/2);
+		HW_DESC_SET_KEY_SIZE_AES(&desc[*seq_size], key_len / 2);
 		HW_DESC_SET_FLOW_MODE(&desc[*seq_size], flow_mode);
 		HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_KEY0);
 		(*seq_size)++;

@@ -560,12 +558,12 @@ ssi_blkcipher_create_setup_desc(
 			HW_DESC_SET_HW_CRYPTO_KEY(&desc[*seq_size], ctx_p->hw.key2_slot);
 		} else {
 			HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, 
-					     (key_dma_addr+key_len/2), key_len/2,
+					     (key_dma_addr + key_len / 2), key_len / 2,
 					     NS_BIT);
 		}
 		HW_DESC_SET_XEX_DATA_UNIT_SIZE(&desc[*seq_size], du_size);
 		HW_DESC_SET_FLOW_MODE(&desc[*seq_size], S_DIN_to_AES2);
-		HW_DESC_SET_KEY_SIZE_AES(&desc[*seq_size], key_len/2);
+		HW_DESC_SET_KEY_SIZE_AES(&desc[*seq_size], key_len / 2);
 		HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_XEX_KEY);
 		(*seq_size)++;
 	

@@ -574,7 +572,7 @@ ssi_blkcipher_create_setup_desc(
 		HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_STATE1);
 		HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], cipher_mode);
 		HW_DESC_SET_CIPHER_CONFIG0(&desc[*seq_size], direction);
-		HW_DESC_SET_KEY_SIZE_AES(&desc[*seq_size], key_len/2);
+		HW_DESC_SET_KEY_SIZE_AES(&desc[*seq_size], key_len / 2);
 		HW_DESC_SET_FLOW_MODE(&desc[*seq_size], flow_mode);
 		HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI,
 				     iv_dma_addr, CC_AES_BLOCK_SIZE,

@@ -620,7 +618,7 @@ static inline void ssi_blkcipher_create_multi2_setup_desc(
 	HW_DESC_SET_FLOW_MODE(&desc[*seq_size], ctx_p->flow_mode);
 	HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], ctx_p->cipher_mode);
 	HW_DESC_SET_CIPHER_CONFIG0(&desc[*seq_size], direction);
-	HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_STATE0 );
+	HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_STATE0);
 	(*seq_size)++;
 	
 	

@@ -634,7 +632,6 @@ static inline void ssi_blkcipher_create_multi2_setup_desc(
 	HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], ctx_p->cipher_mode);
 	HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_STATE1);	
 	(*seq_size)++;
-	
 }
 #endif /*SSI_CC_HAS_MULTI2*/
 

@@ -682,7 +679,7 @@ ssi_blkcipher_create_data_desc(
 		HW_DESC_SET_DOUT_DLLI(&desc[*seq_size],
 				      sg_dma_address(dst),
 				      nbytes,
-				      NS_BIT, (areq == NULL)? 0:1);
+				      NS_BIT, (areq == NULL) ? 0:1);
 		if (areq != NULL) {
 			HW_DESC_SET_QUEUE_LAST_IND(&desc[*seq_size]);
 		}

@@ -718,7 +715,7 @@ ssi_blkcipher_create_data_desc(
 			HW_DESC_SET_DOUT_MLLI(&desc[*seq_size], 
 			ctx_p->drvdata->mlli_sram_addr,
 					      req_ctx->in_mlli_nents,
-					      NS_BIT,(areq == NULL)? 0:1);
+					      NS_BIT, (areq == NULL) ? 0:1);
 		} else {
 			SSI_LOG_DEBUG(" din/dout params "
 				     "addr 0x%08X addr 0x%08X\n",

@@ -730,7 +727,7 @@ ssi_blkcipher_create_data_desc(
 				(ctx_p->drvdata->mlli_sram_addr +
 				LLI_ENTRY_BYTE_SIZE * 
 						req_ctx->in_mlli_nents), 
-				req_ctx->out_mlli_nents, NS_BIT,(areq == NULL)? 0:1);
+				req_ctx->out_mlli_nents, NS_BIT, (areq == NULL) ? 0:1);
 		}
 		if (areq != NULL) {
 			HW_DESC_SET_QUEUE_LAST_IND(&desc[*seq_size]);

@@ -759,13 +756,13 @@ static int ssi_blkcipher_complete(struct device *dev,
 	END_CYCLE_COUNT(STAT_OP_TYPE_GENERIC, STAT_PHASE_4);
 
 
-	/*Set the inflight couter value to local variable*/
+	/*Set the inflight counter value to local variable*/
 	inflight_counter =  ctx_p->drvdata->inflight_counter;
 	/*Decrease the inflight counter*/
-	if(ctx_p->flow_mode == BYPASS && ctx_p->drvdata->inflight_counter > 0)
+	if (ctx_p->flow_mode == BYPASS && ctx_p->drvdata->inflight_counter > 0)
 		ctx_p->drvdata->inflight_counter--;
 
-	if(areq){
+	if (areq) {
 		ablkcipher_request_complete(areq, completion_error);
 		return 0;
 	}

@@ -786,11 +783,11 @@ static int ssi_blkcipher_process(
 	struct device *dev = &ctx_p->drvdata->plat_dev->dev;
 	HwDesc_s desc[MAX_ABLKCIPHER_SEQ_LEN];
 	struct ssi_crypto_req ssi_req = {};
-	int rc, seq_len = 0,cts_restore_flag = 0;
+	int rc, seq_len = 0, cts_restore_flag = 0;
 	DECL_CYCLE_COUNT_RESOURCES;
 
 	SSI_LOG_DEBUG("%s areq=%p info=%p nbytes=%d\n",
-		((direction==DRV_CRYPTO_DIRECTION_ENCRYPT)?"Encrypt":"Decrypt"),
+		((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt":"Decrypt"),
 		     areq, info, nbytes);
 
 	CHECK_AND_RETURN_UPON_FIPS_ERROR();

@@ -809,7 +806,6 @@ static int ssi_blkcipher_process(
 	}
         /*For CTS in case of data size aligned to 16 use CBC mode*/
 	if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == DRV_CIPHER_CBC_CTS)){
-
 		ctx_p->cipher_mode = DRV_CIPHER_CBC;
 		cts_restore_flag = 1;
 	}

@@ -882,7 +878,7 @@ static int ssi_blkcipher_process(
 	START_CYCLE_COUNT();
 	
 	rc = send_request(ctx_p->drvdata, &ssi_req, desc, seq_len, (areq == NULL)? 0:1);
-	if(areq != NULL) {
+	if (areq != NULL) {
 		if (unlikely(rc != -EINPROGRESS)) {
 			/* Failed to send the request or request completed synchronously */
 			ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst);

@@ -926,7 +922,7 @@ static int ssi_sblkcipher_init(struct crypto_tfm *tfm)
 	struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
 
 	/* Allocate sync ctx buffer */
-	ctx_p->sync_ctx = kmalloc(sizeof(struct blkcipher_req_ctx), GFP_KERNEL|GFP_DMA);
+	ctx_p->sync_ctx = kmalloc(sizeof(struct blkcipher_req_ctx), GFP_KERNEL | GFP_DMA);
 	if (!ctx_p->sync_ctx) {
 		SSI_LOG_ERR("Allocating sync ctx buffer in context failed\n");
 		return -ENOMEM;
Signature · 1 line
2.11.0
maintainer
#1 lore raw
Quoted 5 lines · Ammly Fredrick

Fixed some coding style issues after running scripts/checkpatch.pl

Fixed spelling in ssi_blkcipher_complete(), should be counter not couter.

Signed-off-by Ammly Fredrick <[email protected]>

I don't see the 12621 other patches in this series, did you really make that many changes in this driver? :)

You are doing a lot of different things all in the same patch, which isn't allowed. Please fix up and only do one type of thing at a time.

thanks,

greg k-h