pinctrl: imx: add generic pin config and imx7ulp support

PATCH Superseded Dong Aisheng 2 participants 28 messages May 12, 2017 – May 15, 2017

Subsystems (5)

Device tree bindings Arm i.MX and Layerscape GPIO Pin control +1 more subsystems

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Dong Aisheng

author maintainer

2017-05-12 12:38 UTC #0 lore raw

cover pinctrl: imx: add generic pin config and imx7ulp support

This patch series intends to add the generic pin config support for imx platforms.

The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform.

Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently.

In order to cope with some special case, a platform specific fixup() function is also available to use.

The series also added the imx7ulp pinctrl support which only supports generic pin config.

Dong Aisheng (5):
pinctrl: imx: add generic pin config core support
pinctrl: imx: add soc specific mux_mode mask and shift property
dt-bindings: pinctrl: add imx7ulp pinctrl binding doc
pinctrl: imx: add imx7ulp driver
pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case

 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  56 +++
 drivers/pinctrl/freescale/Kconfig                  |   9 +-
 drivers/pinctrl/freescale/Makefile                 |   1 +
 drivers/pinctrl/freescale/pinctrl-imx.c            | 128 +++++-
 drivers/pinctrl/freescale/pinctrl-imx.h            |  29 ++
 drivers/pinctrl/freescale/pinctrl-imx7ulp.c        | 358 ++++++++++++++++
 drivers/pinctrl/freescale/pinctrl-vf610.c          |   2 +
 include/dt-bindings/pinctrl/imx7ulp-pinfunc.h      | 468 +++++++++++++++++++++
 8 files changed, 1030 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 drivers/pinctrl/freescale/pinctrl-imx7ulp.c
 create mode 100644 include/dt-bindings/pinctrl/imx7ulp-pinfunc.h

Signature · 1 line

2.7.4

Dong Aisheng

author maintainer

2017-05-12 12:38 UTC #1 lore raw

PATCH 1/5 pinctrl: imx: add generic pin config core support

Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently.

In order to cope with some special case, a platform specific fixup() function is also available to use.

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Bai Ping <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 drivers/pinctrl/freescale/Kconfig       |   2 +-
 drivers/pinctrl/freescale/pinctrl-imx.c | 106 ++++++++++++++++++++++++++++----
 drivers/pinctrl/freescale/pinctrl-imx.h |  25 ++++++++
 3 files changed, 121 insertions(+), 12 deletions(-)

drivers/pinctrl/freescale/Kconfig +1 -1

index cae05e7..0b266b2 100644
@@ -2,7 +2,7 @@ config PINCTRL_IMX
 	bool
 	select GENERIC_PINCTRL_GROUPS
 	select GENERIC_PINMUX_FUNCTIONS
-	select PINCONF
+	select GENERIC_PINCONF
 	select REGMAP
 
 config PINCTRL_IMX1_CORE

drivers/pinctrl/freescale/pinctrl-imx.c +95 ~~-11~~

163 lines not on this page · raw message

drivers/pinctrl/freescale/pinctrl-imx.h +25 -0

index ff2d3e5..b5c8fe1 100644
@@ -15,6 +15,8 @@
 #ifndef __DRIVERS_PINCTRL_IMX_H
 #define __DRIVERS_PINCTRL_IMX_H
 
+#include <linux/pinctrl/pinconf-generic.h>
+
 struct platform_device;
 
 /**

@@ -44,6 +46,14 @@ struct imx_pin_reg {
 	s16 conf_reg;
 };
 
+/* decode a generic config into raw register value */
+struct imx_cfg_params_decode {
+	enum pin_config_param param;
+	u32 mask;
+	u8 offset;
+	bool invert;
+};
+
 struct imx_pinctrl_soc_info {
 	struct device *dev;
 	const struct pinctrl_pin_desc *pins;

@@ -53,8 +63,23 @@ struct imx_pinctrl_soc_info {
 	unsigned int flags;
 	const char *gpr_compatible;
 	struct mutex mutex;
+
+	/* generic pinconf */
+	bool generic_pinconf;
+	const struct pinconf_generic_params *custom_params;
+	unsigned int num_custom_params;
+	struct imx_cfg_params_decode *decodes;
+	unsigned int num_decodes;
+	void (*fixup)(unsigned long *configs, unsigned int num_configs,
+		      u32 *raw_config);
 };
 
+#define IMX_CFG_PARAMS_DECODE(p, m, o) \
+	{ .param = p, .mask = m, .offset = o, .invert = false, }
+
+#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
+	{ .param = p, .mask = m, .offset = o, .invert = true, }
+
 #define SHARE_MUX_CONF_REG	0x1
 #define ZERO_OFFSET_VALID	0x2

Signature · 1 line

2.7.4

Shawn Guo

2017-05-15 08:35 UTC #2 lore raw

PATCH 1/5 pinctrl: imx: add generic pin config core support

Quoted 4 lines · Dong Aisheng

The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform.

We should probably make it clearer that rather than fully utilizing the generic pinconf support provided by pinctrl core, we only adopt the device tree bindings of generic pinconf. The config used in .pin_config_get[set] are raw register data instead of generic one, and that's why we cannot set pinconf_ops.is_generic.

Quoted 121 lines

Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently.

In order to cope with some special case, a platform specific fixup() function is also available to use.

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Bai Ping <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 drivers/pinctrl/freescale/Kconfig       |   2 +-
 drivers/pinctrl/freescale/pinctrl-imx.c | 106 ++++++++++++++++++++++++++++----
 drivers/pinctrl/freescale/pinctrl-imx.h |  25 ++++++++
 3 files changed, 121 insertions(+), 12 deletions(-)

drivers/pinctrl/freescale/Kconfig +1 -1

index cae05e7..0b266b2 100644
@@ -2,7 +2,7 @@ config PINCTRL_IMX
 	bool
 	select GENERIC_PINCTRL_GROUPS
 	select GENERIC_PINMUX_FUNCTIONS
-	select PINCONF
+	select GENERIC_PINCONF
 	select REGMAP
 
 config PINCTRL_IMX1_CORE

drivers/pinctrl/freescale/pinctrl-imx.c +59 -1

index a7ace9e..db76e9d 100644
@@ -27,6 +27,7 @@
 #include <linux/regmap.h>
 
 #include "../core.h"
+#include "../pinconf.h"
 #include "../pinmux.h"
 #include "pinctrl-imx.h"

@@ -359,6 +360,62 @@ static const struct pinmux_ops imx_pmx_ops = {
 	.gpio_set_direction = imx_pmx_gpio_set_direction,
 };
 
+/* decode generic config into raw register values */
+static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
+					      unsigned long *configs,
+					      unsigned int num_configs)
+{
+	struct imx_pinctrl_soc_info *info = ipctl->info;
+	struct imx_cfg_params_decode *decode;
+	enum pin_config_param param;
+	u32 raw_config = 0;
+	u32 param_val;
+	int i, j;
+
+	WARN_ON(num_configs > info->num_decodes);
+
+	for (i = 0; i < num_configs; i++) {
+		param = pinconf_to_config_param(configs[i]);
+		param_val = pinconf_to_config_argument(configs[i]);
+		decode = info->decodes;
+		for (j = 0; j < info->num_decodes; j++) {
+			if (param == decode->param) {
+				if (decode->invert)
+					param_val = !param_val;
+				raw_config |= (param_val << decode->offset)
+					      & decode->mask;
+				break;
+			}
+			decode++;
+		}
+	}
+
+	if (info->fixup)
+		info->fixup(configs, num_configs, &raw_config);
+
+	return raw_config;
+}
+
+static u32 imx_pinconf_parse_generic_config(struct device_node *np,
+					    struct imx_pinctrl *ipctl)
+{
+	struct imx_pinctrl_soc_info *info = ipctl->info;
+	struct pinctrl_dev *pctl = ipctl->pctl;
+	unsigned int num_configs;
+	unsigned long *configs;
+	int ret;
+
+	if (!info->generic_pinconf)
+		return 0;
+
+	ret = pinconf_generic_parse_dt_config(np, pctl, &configs,
+					      &num_configs);
+	if (ret)
+		return 0;
+
+	return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
+}
+
 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 			     unsigned pin_id, unsigned long *config)
 {

@@ -475,9 +532,10 @@ static const struct pinconf_ops imx_pinconf_ops = {
 
 static int imx_pinctrl_parse_groups(struct device_node *np,
 				    struct group_desc *grp,
-				    struct imx_pinctrl_soc_info *info,
+				    struct imx_pinctrl *ipctl,
 				    u32 index)
 {
+	struct imx_pinctrl_soc_info *info = ipctl->info;
 	int size, pin_size;
 	const __be32 *list;
 	int i;

@@ -489,17 +547,29 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
 		pin_size = SHARE_FSL_PIN_SIZE;
 	else
 		pin_size = FSL_PIN_SIZE;

drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinctrl_parse_groups(struct device_node *np, · line 558

Quoted 10 lines

drivers/pinctrl/freescale/pinctrl-imx.c +5 -1

+
+	if (info->generic_pinconf)
+		pin_size -= 4;
+
 	/* Initialise group */
 	grp->name = np->name;
 
 	/*
-	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
+	 * the binding format is pins = <PIN_FUNC_ID CONFIG ...>,

This is not correct for generic pinconf bindings. CONIFIG shouldn't be there.

Quoted 41 lines

drivers/pinctrl/freescale/pinctrl-imx.c +16 -8

 	 * do sanity check and calculate pins number
+	 *
+	 * First try generic 'pins' property, then fall back to the
+	 * legacy 'fsl,pins'.
 	 */
-	list = of_get_property(np, "fsl,pins", &size);
+	list = of_get_property(np, "pins", &size);
 	if (!list) {
-		dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
-		return -EINVAL;
+		list = of_get_property(np, "fsl,pins", &size);
+		if (!list) {
+			dev_err(info->dev,
+				"no pins and fsl,pins property in node %s\n",
+				np->full_name);
+			return -EINVAL;
+		}
 	}
 
 	/* we do not check return since it's safe node passed down */

@@ -508,6 +578,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
 		return -EINVAL;
 	}
 
+	/* first try to parse the generic pin config */
+	config = imx_pinconf_parse_generic_config(np, ipctl);
+
 	grp->num_pins = size / pin_size;
 	grp->data = devm_kzalloc(info->dev, grp->num_pins *
 				 sizeof(struct imx_pin), GFP_KERNEL);

@@ -544,11 +617,18 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
 		pin->mux_mode = be32_to_cpu(*list++);
 		pin->input_val = be32_to_cpu(*list++);
 
-		/* SION bit is in mux register */
-		config = be32_to_cpu(*list++);
-		if (config & IMX_PAD_SION)
-			pin->mux_mode |= IOMUXC_CONFIG_SION;
-		pin->config = config & ~IMX_PAD_SION;
+		if (info->generic_pinconf) {
+			/* generic pin config decoded */

drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinctrl_parse_groups(struct device_node *np, · line 631

Quoted 10 lines

drivers/pinctrl/freescale/pinctrl-imx.c +10 -0

+			pin->config = config;
+		} else {
+			/* legacy pin config read from devicetree */
+			config = be32_to_cpu(*list++);
+
+			/* SION bit is in mux register */
+			if (config & IMX_PAD_SION)
+				pin->mux_mode |= IOMUXC_CONFIG_SION;
+			pin->config = config & ~IMX_PAD_SION;
+		}

So we do not have this SION support for all SoCs that will use generic pinconf bindings?

Quoted 37 lines

drivers/pinctrl/freescale/pinctrl-imx.c +5 -1

 		dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
 				pin->mux_mode, pin->config);

@@ -598,7 +678,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
 				  info->group_index++, grp);
 		mutex_unlock(&info->mutex);
 
-		imx_pinctrl_parse_groups(child, grp, info, i++);
+		imx_pinctrl_parse_groups(child, grp, ipctl, i++);
 	}
 
 	return 0;

@@ -769,6 +849,10 @@ int imx_pinctrl_probe(struct platform_device *pdev,
 	imx_pinctrl_desc->confops = &imx_pinconf_ops;
 	imx_pinctrl_desc->owner = THIS_MODULE;
 
+	/* for generic pinconf */
+	imx_pinctrl_desc->custom_params = info->custom_params;
+	imx_pinctrl_desc->num_custom_params = info->num_custom_params;
+
 	mutex_init(&info->mutex);
 
 	ipctl->info = info;

drivers/pinctrl/freescale/pinctrl-imx.h +2 -0

index ff2d3e5..b5c8fe1 100644
@@ -15,6 +15,8 @@
 #ifndef __DRIVERS_PINCTRL_IMX_H
 #define __DRIVERS_PINCTRL_IMX_H
 
+#include <linux/pinctrl/pinconf-generic.h>
+
 struct platform_device;
 
 /**

drivers/pinctrl/freescale/pinctrl-imx.h struct imx_pin_reg { · line 53

Quoted 8 lines

drivers/pinctrl/freescale/pinctrl-imx.h +5 -0

@@ -44,6 +46,14 @@ struct imx_pin_reg {
 	s16 conf_reg;
 };
 
+/* decode a generic config into raw register value */
+struct imx_cfg_params_decode {
+	enum pin_config_param param;
+	u32 mask;
+	u8 offset;

'shift' might be better, since we mostly use 'offset' for a register offset.

Shawn

Quoted 38 lines

drivers/pinctrl/freescale/pinctrl-imx.h +18 -0

+	bool invert;
+};
+
 struct imx_pinctrl_soc_info {
 	struct device *dev;
 	const struct pinctrl_pin_desc *pins;

@@ -53,8 +63,23 @@ struct imx_pinctrl_soc_info {
 	unsigned int flags;
 	const char *gpr_compatible;
 	struct mutex mutex;
+
+	/* generic pinconf */
+	bool generic_pinconf;
+	const struct pinconf_generic_params *custom_params;
+	unsigned int num_custom_params;
+	struct imx_cfg_params_decode *decodes;
+	unsigned int num_decodes;
+	void (*fixup)(unsigned long *configs, unsigned int num_configs,
+		      u32 *raw_config);
 };
 
+#define IMX_CFG_PARAMS_DECODE(p, m, o) \
+	{ .param = p, .mask = m, .offset = o, .invert = false, }
+
+#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
+	{ .param = p, .mask = m, .offset = o, .invert = true, }
+
 #define SHARE_MUX_CONF_REG	0x1
 #define ZERO_OFFSET_VALID	0x2

Signature · 7 lines

2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

A.S. Dong

author maintainer

2017-05-15 08:56 UTC #3 lore raw

PATCH 1/5 pinctrl: imx: add generic pin config core support

Hi Shawn,

Sorry to reply in outlook as I don't know why my gmail failed to receive this mail.

First of all, thank you for the review.

Quoted 15 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 4:35 PM
To: A.S. Dong
Cc: linux-gpio at vger.kernel.org; Andy Duan; Jacky Bai; linus.walleij at linaro.org; stefan at agner.ch; kernel at pengutronix.de; linux- arm-kernel at lists.infradead.org
Subject: Re: [PATCH 1/5] pinctrl: imx: add generic pin config core support
Quoted 4 lines · Dong Aisheng
The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform.

Quoted 6 lines

We should probably make it clearer that rather than fully utilizing the generic pinconf support provided by pinctrl core, we only adopt the device tree bindings of generic pinconf. The config used in .pin_config_get[set] are raw register data instead of generic one, and that's why we cannot set pinconf_ops.is_generic.

Yes, that's true.
Maybe i could merge these words into the commit message in my next version Then we can make it clearer.

Quoted 132 lines

Quoted 3 lines

Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register

decode map conveniently.

Quoted 93 lines

In order to cope with some special case, a platform specific fixup() function is also available to use.

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Bai Ping <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 drivers/pinctrl/freescale/Kconfig       |   2 +-
 drivers/pinctrl/freescale/pinctrl-imx.c | 106
++++++++++++++++++++++++++++----
drivers/pinctrl/freescale/pinctrl-imx.h |  25 ++++++++
 3 files changed, 121 insertions(+), 12 deletions(-)

drivers/pinctrl/freescale/Kconfig +1 -1

index cae05e7..0b266b2 100644
@@ -2,7 +2,7 @@ config PINCTRL_IMX
 	bool
 	select GENERIC_PINCTRL_GROUPS
 	select GENERIC_PINMUX_FUNCTIONS
-	select PINCONF
+	select GENERIC_PINCONF
 	select REGMAP
 
 config PINCTRL_IMX1_CORE

drivers/pinctrl/freescale/pinctrl-imx.c +49 -0

index a7ace9e..db76e9d 100644
@@ -27,6 +27,7 @@
 #include <linux/regmap.h>
 
 #include "../core.h"
+#include "../pinconf.h"
 #include "../pinmux.h"
 #include "pinctrl-imx.h"

@@ -359,6 +360,62 @@ static const struct pinmux_ops imx_pmx_ops = {
 	.gpio_set_direction = imx_pmx_gpio_set_direction,  };
 
+/* decode generic config into raw register values */ static u32
+imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
+					      unsigned long *configs,
+					      unsigned int num_configs)
+{
+	struct imx_pinctrl_soc_info *info = ipctl->info;
+	struct imx_cfg_params_decode *decode;
+	enum pin_config_param param;
+	u32 raw_config = 0;
+	u32 param_val;
+	int i, j;
+
+	WARN_ON(num_configs > info->num_decodes);
+
+	for (i = 0; i < num_configs; i++) {
+		param = pinconf_to_config_param(configs[i]);
+		param_val = pinconf_to_config_argument(configs[i]);
+		decode = info->decodes;
+		for (j = 0; j < info->num_decodes; j++) {
+			if (param == decode->param) {
+				if (decode->invert)
+					param_val = !param_val;
+				raw_config |= (param_val << decode->offset)
+					      & decode->mask;
+				break;
+			}
+			decode++;
+		}
+	}
+
+	if (info->fixup)
+		info->fixup(configs, num_configs, &raw_config);
+
+	return raw_config;
+}
+
+static u32 imx_pinconf_parse_generic_config(struct device_node *np,
+					    struct imx_pinctrl *ipctl)
+{
+	struct imx_pinctrl_soc_info *info = ipctl->info;
+	struct pinctrl_dev *pctl = ipctl->pctl;
+	unsigned int num_configs;
+	unsigned long *configs;
+	int ret;
+
+	if (!info->generic_pinconf)
+		return 0;
+

drivers/pinctrl/freescale/pinctrl-imx.c static const struct pinmux_ops imx_pmx_ops = { · line 419

Quoted 10 lines

drivers/pinctrl/freescale/pinctrl-imx.c +8 -0

+	ret = pinconf_generic_parse_dt_config(np, pctl, &configs,
+					      &num_configs);
+	if (ret)
+		return 0;
+
+	return imx_pinconf_decode_generic_config(ipctl, configs,
+num_configs); }
+
 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 			     unsigned pin_id, unsigned long *config)  { @@ -

475,9 +532,10

drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinctrl_parse_groups(struct

Quoted 13 lines

drivers/pinctrl/freescale/pinctrl-imx.c +0 -0

 @@ static const struct pinconf_ops imx_pinconf_ops = {

static int imx_pinctrl_parse_groups(struct device_node *np,

drivers/pinctrl/freescale/pinctrl-imx.c +2 -1

 				    struct group_desc *grp,
-				    struct imx_pinctrl_soc_info *info,
+				    struct imx_pinctrl *ipctl,
 				    u32 index)
 {
+	struct imx_pinctrl_soc_info *info = ipctl->info;
 	int size, pin_size;
 	const __be32 *list;
 	int i;

@@ -489,17 +547,29 @@ static int imx_pinctrl_parse_groups(struct

device_node *np,

Quoted 10 lines

drivers/pinctrl/freescale/pinctrl-imx.c +4 -0

 		pin_size = SHARE_FSL_PIN_SIZE;
 	else
 		pin_size = FSL_PIN_SIZE;
+
+	if (info->generic_pinconf)
+		pin_size -= 4;
+
 	/* Initialise group */
 	grp->name = np->name;

Quoted 7 lines

drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinctrl_parse_groups(struct · line 558
Quoted 3 lines
drivers/pinctrl/freescale/pinctrl-imx.c +1 -1
 	/*
-	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
+	 * the binding format is pins = <PIN_FUNC_ID CONFIG ...>,
This is not correct for generic pinconf bindings. CONIFIG shouldn't be there.

Yes, that's for legacy stuff.

To make things easy, how about adding below notes and keep it there?

drivers/pinctrl/freescale/pinctrl-imx.c +3 -0

index 57e1f7a..b2cb3f5 100644
@@ -564,6 +564,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
         *
         * First try generic 'pins' property, then fall back to the
         * legacy 'fsl,pins'.
+        *
+        * Note: for generic pin config case, there's no CONFIG part in
+        * the binding format.
         */
        list = of_get_property(np, "pins", &size);
        if (!list) {

Quoted 49 lines

Quoted 20 lines

drivers/pinctrl/freescale/pinctrl-imx.c +11 -3

 	 * do sanity check and calculate pins number
+	 *
+	 * First try generic 'pins' property, then fall back to the
+	 * legacy 'fsl,pins'.
 	 */
-	list = of_get_property(np, "fsl,pins", &size);
+	list = of_get_property(np, "pins", &size);
 	if (!list) {
-		dev_err(info->dev, "no fsl,pins property in node %s\n", np-
 full_name);
-		return -EINVAL;
+		list = of_get_property(np, "fsl,pins", &size);
+		if (!list) {
+			dev_err(info->dev,
+				"no pins and fsl,pins property in node %s\n",
+				np->full_name);
+			return -EINVAL;
+		}
 	}

Quoted 2 lines

/* we do not check return since it's safe node passed down */ @@
-508,6 +578,9 @@ static int imx_pinctrl_parse_groups(struct device_node

*np,

drivers/pinctrl/freescale/pinctrl-imx.c

Quoted 9 lines

drivers/pinctrl/freescale/pinctrl-imx.c +3 -0

 		return -EINVAL;
 	}
 
+	/* first try to parse the generic pin config */
+	config = imx_pinconf_parse_generic_config(np, ipctl);
+
 	grp->num_pins = size / pin_size;
 	grp->data = devm_kzalloc(info->dev, grp->num_pins *
 				 sizeof(struct imx_pin), GFP_KERNEL); @@ -544,11

+617,18 @@

Quoted 16 lines

static int imx_pinctrl_parse_groups(struct device_node *np,

drivers/pinctrl/freescale/pinctrl-imx.c +7 -5

 		pin->mux_mode = be32_to_cpu(*list++);
 		pin->input_val = be32_to_cpu(*list++);
 
-		/* SION bit is in mux register */
-		config = be32_to_cpu(*list++);
-		if (config & IMX_PAD_SION)
-			pin->mux_mode |= IOMUXC_CONFIG_SION;
-		pin->config = config & ~IMX_PAD_SION;
+		if (info->generic_pinconf) {
+			/* generic pin config decoded */
+			pin->config = config;
+		} else {
+			/* legacy pin config read from devicetree */
+			config = be32_to_cpu(*list++);
+

Quoted 9 lines

drivers/pinctrl/freescale/pinctrl-imx.c
Quoted 5 lines
drivers/pinctrl/freescale/pinctrl-imx.c +5 -0
+			/* SION bit is in mux register */
+			if (config & IMX_PAD_SION)
+				pin->mux_mode |= IOMUXC_CONFIG_SION;
+			pin->config = config & ~IMX_PAD_SION;
+		}
So we do not have this SION support for all SoCs that will use generic pinconf bindings?

Yes, we only support starting from IMX7ULP and IMX7ULP has no SION bit.

If we do want the legacy MX6&7 supports as well, we could add it later With a separate patch as it probably needs change not only SION bit, But should also taking account of generic and non-generic pinconf co-exist.

Quoted 42 lines

drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinctrl_parse_functions(struct

Quoted 4 lines

drivers/pinctrl/freescale/pinctrl-imx.c +0 -0

 		dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
 				pin->mux_mode, pin->config);

@@ -598,7 +678,7 @@ static int imx_pinctrl_parse_functions(struct

device_node *np,

Quoted 37 lines

drivers/pinctrl/freescale/pinctrl-imx.c +5 -1

 				  info->group_index++, grp);
 		mutex_unlock(&info->mutex);
 
-		imx_pinctrl_parse_groups(child, grp, info, i++);
+		imx_pinctrl_parse_groups(child, grp, ipctl, i++);
 	}
 
 	return 0;

@@ -769,6 +849,10 @@ int imx_pinctrl_probe(struct platform_device *pdev,
 	imx_pinctrl_desc->confops = &imx_pinconf_ops;
 	imx_pinctrl_desc->owner = THIS_MODULE;
 
+	/* for generic pinconf */
+	imx_pinctrl_desc->custom_params = info->custom_params;
+	imx_pinctrl_desc->num_custom_params = info->num_custom_params;
+
 	mutex_init(&info->mutex);
 
 	ipctl->info = info;

drivers/pinctrl/freescale/pinctrl-imx.h +2 -0

index ff2d3e5..b5c8fe1 100644
@@ -15,6 +15,8 @@
 #ifndef __DRIVERS_PINCTRL_IMX_H
 #define __DRIVERS_PINCTRL_IMX_H
 
+#include <linux/pinctrl/pinconf-generic.h>
+
 struct platform_device;
 
 /**

@@ -44,6 +46,14 @@ struct imx_pin_reg {
 	s16 conf_reg;
 };

Quoted 9 lines

drivers/pinctrl/freescale/pinctrl-imx.h struct imx_pin_reg { · line 53
Quoted 5 lines
drivers/pinctrl/freescale/pinctrl-imx.h +5 -0
+/* decode a generic config into raw register value */ struct
+imx_cfg_params_decode {
+	enum pin_config_param param;
+	u32 mask;
+	u8 offset;
'shift' might be better, since we mostly use 'offset' for a register offset.

Got it.
I'm fine with it, will update later.

Regards
Dong Aisheng

Quoted 40 lines

Shawn

Quoted 38 lines

drivers/pinctrl/freescale/pinctrl-imx.h +3 -0

+	bool invert;
+};
+
 struct imx_pinctrl_soc_info {
 	struct device *dev;
 	const struct pinctrl_pin_desc *pins; @@ -53,8 +63,23 @@ struct

imx_pinctrl_soc_info {

drivers/pinctrl/freescale/pinctrl-imx.h +15 -1

 	unsigned int flags;
 	const char *gpr_compatible;
 	struct mutex mutex;
+
+	/* generic pinconf */
+	bool generic_pinconf;
+	const struct pinconf_generic_params *custom_params;
+	unsigned int num_custom_params;
+	struct imx_cfg_params_decode *decodes;
+	unsigned int num_decodes;
+	void (*fixup)(unsigned long *configs, unsigned int num_configs,
+		      u32 *raw_config);
 };
 
+#define IMX_CFG_PARAMS_DECODE(p, m, o) \
+	{ .param = p, .mask = m, .offset = o, .invert = false, }
+
+#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
+	{ .param = p, .mask = m, .offset = o, .invert = true, }
+
 #define SHARE_MUX_CONF_REG	0x1
 #define ZERO_OFFSET_VALID	0x2
 
--

2.7.4

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Shawn Guo

2017-05-15 10:56 UTC #4 lore raw

PATCH 1/5 pinctrl: imx: add generic pin config core support

Quoted 20 lines · A.S. Dong

Quoted 12 lines
Review static int imx_pinctrl_parse_groups(struct
Quoted 1 line
(quoted diff) +0 -0
@@ -489,17 +547,29 @@ static int imx_pinctrl_parse_groups(struct
device_node *np,
Quoted 10 lines
(quoted diff) +4 -0
 		pin_size = SHARE_FSL_PIN_SIZE;
 	else
 		pin_size = FSL_PIN_SIZE;
+
+	if (info->generic_pinconf)
+		pin_size -= 4;
+
 	/* Initialise group */
 	grp->name = np->name;
 
Quoted 7 lines
Review static int imx_pinctrl_parse_groups(struct · line 558
Quoted 3 lines
(quoted diff) +1 -1
 	/*
-	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
+	 * the binding format is pins = <PIN_FUNC_ID CONFIG ...>,
This is not correct for generic pinconf bindings. CONIFIG shouldn't be there.

Quoted 1 line

Yes, that's for legacy stuff.

If that's for legacy bindings, you shouldn't change 'fsl,pins' to 'pins', right?

Shawn

A.S. Dong

author maintainer

2017-05-15 11:16 UTC #5 lore raw

PATCH 1/5 pinctrl: imx: add generic pin config core support

Quoted 30 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 6:56 PM
To: A.S. Dong
Cc: Andy Duan; Jacky Bai; linus.walleij at linaro.org; stefan at agner.ch; linux-gpio at vger.kernel.org; kernel at pengutronix.de; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH 1/5] pinctrl: imx: add generic pin config core support
Quoted 20 lines · A.S. Dong
Quoted 19 lines
Review static int imx_pinctrl_parse_groups(struct
Quoted 1 line
(quoted diff) +0 -0
@@ -489,17 +547,29 @@ static int imx_pinctrl_parse_groups(struct
device_node *np,
Review static int imx_pinctrl_parse_groups(struct · line 558
Quoted 13 lines
(quoted diff) +5 -1
 		pin_size = SHARE_FSL_PIN_SIZE;
 	else
 		pin_size = FSL_PIN_SIZE;
+
+	if (info->generic_pinconf)
+		pin_size -= 4;
+
 	/* Initialise group */
 	grp->name = np->name;
 
 	/*
-	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
+	 * the binding format is pins = <PIN_FUNC_ID CONFIG ...>,
This is not correct for generic pinconf bindings. CONIFIG shouldn't be there.

Quoted 5 lines

Quoted 1 line
Yes, that's for legacy stuff.
If that's for legacy bindings, you shouldn't change 'fsl,pins' to 'pins', right?

I mean the binding format.
For the legacy format, either the name of 'fsl,pins' or 'pins' is ok.

But in order to increase the standard 'pins' priority, I change 'fsl,pins' to 'pins' to make it more explicitly.

I do can leave "fsl,pins' not changed, but I think the new one may be better, right?

Regards
Dong Aisheng

Quoted 1 line

Shawn

Shawn Guo

2017-05-15 11:56 UTC #6 lore raw

PATCH 1/5 pinctrl: imx: add generic pin config core support

Quoted 36 lines · A.S. Dong

Quoted 30 lines
-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 6:56 PM
To: A.S. Dong
Cc: Andy Duan; Jacky Bai; linus.walleij at linaro.org; stefan at agner.ch; linux-gpio at vger.kernel.org; kernel at pengutronix.de; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH 1/5] pinctrl: imx: add generic pin config core support
Quoted 20 lines · A.S. Dong
Quoted 19 lines
Review static int imx_pinctrl_parse_groups(struct
Quoted 1 line
(quoted diff) +0 -0
@@ -489,17 +547,29 @@ static int imx_pinctrl_parse_groups(struct
device_node *np,
Review static int imx_pinctrl_parse_groups(struct · line 558
Quoted 13 lines
(quoted diff) +5 -1
 		pin_size = SHARE_FSL_PIN_SIZE;
 	else
 		pin_size = FSL_PIN_SIZE;
+
+	if (info->generic_pinconf)
+		pin_size -= 4;
+
 	/* Initialise group */
 	grp->name = np->name;
 
 	/*
-	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
+	 * the binding format is pins = <PIN_FUNC_ID CONFIG ...>,
This is not correct for generic pinconf bindings. CONIFIG shouldn't be there.
Quoted 5 lines
Quoted 1 line
Yes, that's for legacy stuff.
If that's for legacy bindings, you shouldn't change 'fsl,pins' to 'pins', right?

Quoted 8 lines

I mean the binding format.
For the legacy format, either the name of 'fsl,pins' or 'pins' is ok.
But in order to increase the standard 'pins' priority, I change 'fsl,pins' to 'pins' to make it more explicitly.
I do can leave "fsl,pins' not changed, but I think the new one may be better, right?

Please leave "fsl,pins' unchanged, and let's use 'fsl,pins' for legacy bindings and 'pins' for new one.

Shawn

A.S. Dong

author maintainer

2017-05-15 12:07 UTC #7 lore raw

PATCH 1/5 pinctrl: imx: add generic pin config core support

Quoted 51 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 7:57 PM
To: A.S. Dong
Cc: Andy Duan; Jacky Bai; linus.walleij at linaro.org; stefan at agner.ch; linux-gpio at vger.kernel.org; kernel at pengutronix.de; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH 1/5] pinctrl: imx: add generic pin config core support
Quoted 41 lines · A.S. Dong
Quoted 32 lines
-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 6:56 PM
To: A.S. Dong
Cc: Andy Duan; Jacky Bai; linus.walleij at linaro.org; stefan at agner.ch; linux-gpio at vger.kernel.org; kernel at pengutronix.de; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH 1/5] pinctrl: imx: add generic pin config core support
Quoted 21 lines · A.S. Dong
Quoted 20 lines
Quoted 2 lines
(quoted diff) +0 -0
@@ -489,17 +547,29 @@ static int
imx_pinctrl_parse_groups(struct
device_node *np,
Review
Quoted 13 lines
(quoted diff) +5 -1
 		pin_size = SHARE_FSL_PIN_SIZE;
 	else
 		pin_size = FSL_PIN_SIZE;
+
+	if (info->generic_pinconf)
+		pin_size -= 4;
+
 	/* Initialise group */
 	grp->name = np->name;
 
 	/*
-	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
+	 * the binding format is pins = <PIN_FUNC_ID CONFIG ...>,
This is not correct for generic pinconf bindings. CONIFIG shouldn't be there.
Quoted 5 lines
Quoted 1 line
Yes, that's for legacy stuff.
If that's for legacy bindings, you shouldn't change 'fsl,pins' to 'pins', right?
I mean the binding format.
For the legacy format, either the name of 'fsl,pins' or 'pins' is ok.

Quoted 9 lines

Quoted 5 lines
But in order to increase the standard 'pins' priority, I change 'fsl,pins' to 'pins' to make it more explicitly.
I do can leave "fsl,pins' not changed, but I think the new one may be better, right?
Please leave "fsl,pins' unchanged, and let's use 'fsl,pins' for legacy bindings and 'pins' for new one.

Okay, make sense, got it.

Regards
Dong Aisheng

Quoted 1 line

Shawn

Dong Aisheng

author maintainer

2017-05-12 12:38 UTC #8 lore raw

PATCH 2/5 pinctrl: imx: add soc specific mux_mode mask and shift property

In reply to Dong Aisheng

MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support.

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Stefan Agner <[email protected]>

Cc Bai Ping <[email protected]>

Signed-off-by Fugang Duan <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 drivers/pinctrl/freescale/pinctrl-imx.c   | 10 +++++-----
 drivers/pinctrl/freescale/pinctrl-imx.h   |  4 ++++
 drivers/pinctrl/freescale/pinctrl-vf610.c |  2 ++
 3 files changed, 11 insertions(+), 5 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +5 -5

index db76e9d..8347197 100644
@@ -197,8 +197,8 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->mux_reg);
-			reg &= ~(0x7 << 20);
-			reg |= (pin->mux_mode << 20);
+			reg &= ~info->mux_mask;
+			reg |= (pin->mux_mode << info->mux_shift);
 			writel(reg, ipctl->base + pin_reg->mux_reg);
 		} else {
 			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);

@@ -288,7 +288,7 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
 
 mux_pin:
 	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~(0x7 << 20);
+	reg &= ~info->mux_mask;
 	reg |= imx_pin->config;
 	writel(reg, ipctl->base + pin_reg->mux_reg);

@@ -432,7 +432,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 	*config = readl(ipctl->base + pin_reg->conf_reg);
 
 	if (info->flags & SHARE_MUX_CONF_REG)
-		*config &= 0xffff;
+		*config &= ~info->mux_mask;
 
 	return 0;
 }

@@ -459,7 +459,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->conf_reg);
-			reg &= ~0xffff;
+			reg &= info->mux_mask;
 			reg |= configs[i];
 			writel(reg, ipctl->base + pin_reg->conf_reg);
 		} else {

drivers/pinctrl/freescale/pinctrl-imx.h +4 -0

index b5c8fe1..eb0ce95 100644
@@ -64,6 +64,10 @@ struct imx_pinctrl_soc_info {
 	const char *gpr_compatible;
 	struct mutex mutex;
 
+	/* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
+	unsigned int mux_mask;
+	u8 mux_shift;
+
 	/* generic pinconf */
 	bool generic_pinconf;
 	const struct pinconf_generic_params *custom_params;

drivers/pinctrl/freescale/pinctrl-vf610.c +2 -0

index 2b1e198..3bd8556 100644
@@ -299,6 +299,8 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
 	.pins = vf610_pinctrl_pads,
 	.npins = ARRAY_SIZE(vf610_pinctrl_pads),
 	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+	.mux_mask = 0x700000,
+	.mux_shift = 20,
 };
 
 static const struct of_device_id vf610_pinctrl_of_match[] = {

Signature · 1 line

2.7.4

Shawn Guo

2017-05-15 08:52 UTC #9 lore raw

PATCH 2/5 pinctrl: imx: add soc specific mux_mode mask and shift property

Quoted 41 lines · Dong Aisheng

MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support.

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Stefan Agner <[email protected]>

Cc Bai Ping <[email protected]>

Signed-off-by Fugang Duan <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 drivers/pinctrl/freescale/pinctrl-imx.c   | 10 +++++-----
 drivers/pinctrl/freescale/pinctrl-imx.h   |  4 ++++
 drivers/pinctrl/freescale/pinctrl-vf610.c |  2 ++
 3 files changed, 11 insertions(+), 5 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +3 -3

index db76e9d..8347197 100644
@@ -197,8 +197,8 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->mux_reg);
-			reg &= ~(0x7 << 20);
-			reg |= (pin->mux_mode << 20);
+			reg &= ~info->mux_mask;
+			reg |= (pin->mux_mode << info->mux_shift);
 			writel(reg, ipctl->base + pin_reg->mux_reg);
 		} else {
 			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);

@@ -288,7 +288,7 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
 
 mux_pin:
 	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~(0x7 << 20);
+	reg &= ~info->mux_mask;
 	reg |= imx_pin->config;
 	writel(reg, ipctl->base + pin_reg->mux_reg);

drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinconf_get(struct pinctrl_dev *pctldev, · line 435

Quoted 5 lines

drivers/pinctrl/freescale/pinctrl-imx.c +1 -1

@@ -432,7 +432,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 	*config = readl(ipctl->base + pin_reg->conf_reg);
 
 	if (info->flags & SHARE_MUX_CONF_REG)
-		*config &= 0xffff;
+		*config &= ~info->mux_mask;

It changes the way how code works. We need a note in the commit log explaining why it's safe.

Shawn

Quoted 48 lines

drivers/pinctrl/freescale/pinctrl-imx.c +1 -1

 	return 0;
 }

@@ -459,7 +459,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->conf_reg);
-			reg &= ~0xffff;
+			reg &= info->mux_mask;
 			reg |= configs[i];
 			writel(reg, ipctl->base + pin_reg->conf_reg);
 		} else {

drivers/pinctrl/freescale/pinctrl-imx.h +4 -0

index b5c8fe1..eb0ce95 100644
@@ -64,6 +64,10 @@ struct imx_pinctrl_soc_info {
 	const char *gpr_compatible;
 	struct mutex mutex;
 
+	/* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
+	unsigned int mux_mask;
+	u8 mux_shift;
+
 	/* generic pinconf */
 	bool generic_pinconf;
 	const struct pinconf_generic_params *custom_params;

drivers/pinctrl/freescale/pinctrl-vf610.c +2 -0

index 2b1e198..3bd8556 100644
@@ -299,6 +299,8 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
 	.pins = vf610_pinctrl_pads,
 	.npins = ARRAY_SIZE(vf610_pinctrl_pads),
 	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+	.mux_mask = 0x700000,
+	.mux_shift = 20,
 };
 
 static const struct of_device_id vf610_pinctrl_of_match[] = {

Signature · 7 lines

2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

A.S. Dong

author maintainer

2017-05-15 09:00 UTC #10 lore raw

PATCH 2/5 pinctrl: imx: add soc specific mux_mode mask and shift property

Quoted 57 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 4:53 PM
To: A.S. Dong
Cc: linux-gpio at vger.kernel.org; Andy Duan; Jacky Bai; linus.walleij at linaro.org; stefan at agner.ch; kernel at pengutronix.de; linux- arm-kernel at lists.infradead.org
Subject: Re: [PATCH 2/5] pinctrl: imx: add soc specific mux_mode mask and shift property
drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pmx_set(struct pinctrl_dev *pctldev,
Quoted 22 lines · Dong Aisheng
MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support.
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Fugang Duan <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
 drivers/pinctrl/freescale/pinctrl-imx.c   | 10 +++++-----
 drivers/pinctrl/freescale/pinctrl-imx.h   |  4 ++++
 drivers/pinctrl/freescale/pinctrl-vf610.c |  2 ++
 3 files changed, 11 insertions(+), 5 deletions(-)
drivers/pinctrl/freescale/pinctrl-imx.c +0 -0
index db76e9d..8347197 100644
@@ -197,8 +197,8 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
unsigned selector,
drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, · line 204
Quoted 10 lines
drivers/pinctrl/freescale/pinctrl-imx.c +2 -2
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->mux_reg);
-			reg &= ~(0x7 << 20);
-			reg |= (pin->mux_mode << 20);
+			reg &= ~info->mux_mask;
+			reg |= (pin->mux_mode << info->mux_shift);
 			writel(reg, ipctl->base + pin_reg->mux_reg);
 		} else {
 			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
@@ -288,7
drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinconf_get(struct pinctrl_dev
Quoted 11 lines
+288,7 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
mux_pin:
drivers/pinctrl/freescale/pinctrl-imx.c +1 -1
 	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~(0x7 << 20);
+	reg &= ~info->mux_mask;
 	reg |= imx_pin->config;
 	writel(reg, ipctl->base + pin_reg->mux_reg);
@@ -432,7 +432,7 @@ static int imx_pinconf_get(struct pinctrl_dev
*pctldev,

Quoted 9 lines

drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinconf_get(struct pinctrl_dev *pctldev, · line 435
Quoted 5 lines
drivers/pinctrl/freescale/pinctrl-imx.c +1 -1
 	*config = readl(ipctl->base + pin_reg->conf_reg);
 
 	if (info->flags & SHARE_MUX_CONF_REG)
-		*config &= 0xffff;
+		*config &= ~info->mux_mask;
It changes the way how code works. We need a note in the commit log explaining why it's safe.

Well, that's Vybrid tricks that BIT[15-0] are all configs part. So it hardcoded 0xffff there.

But it's not true in ULP, so use mux_mask instead to address the difference.

Regards
Dong Aisheng

Quoted 54 lines

Shawn
drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinconf_set(struct pinctrl_dev
Quoted 4 lines
drivers/pinctrl/freescale/pinctrl-imx.c +0 -0
 	return 0;
 }
@@ -459,7 +459,7 @@ static int imx_pinconf_set(struct pinctrl_dev
*pctldev,
drivers/pinctrl/freescale/pinctrl-vf610.c static struct imx_pinctrl_soc_info
Quoted 30 lines
drivers/pinctrl/freescale/pinctrl-imx.c +1 -1
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->conf_reg);
-			reg &= ~0xffff;
+			reg &= info->mux_mask;
 			reg |= configs[i];
 			writel(reg, ipctl->base + pin_reg->conf_reg);
 		} else {
drivers/pinctrl/freescale/pinctrl-imx.h +4 -0
index b5c8fe1..eb0ce95 100644
@@ -64,6 +64,10 @@ struct imx_pinctrl_soc_info {
 	const char *gpr_compatible;
 	struct mutex mutex;
 
+	/* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
+	unsigned int mux_mask;
+	u8 mux_shift;
+
 	/* generic pinconf */
 	bool generic_pinconf;
 	const struct pinconf_generic_params *custom_params; diff --git
a/drivers/pinctrl/freescale/pinctrl-vf610.c
b/drivers/pinctrl/freescale/pinctrl-vf610.c
index 2b1e198..3bd8556 100644
drivers/pinctrl/freescale/pinctrl-vf610.c +0 -0
@@ -299,6 +299,8 @@ static struct imx_pinctrl_soc_info
vf610_pinctrl_info = {
Quoted 16 lines
drivers/pinctrl/freescale/pinctrl-vf610.c +2 -1
 	.pins = vf610_pinctrl_pads,
 	.npins = ARRAY_SIZE(vf610_pinctrl_pads),
 	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+	.mux_mask = 0x700000,
+	.mux_shift = 20,
 };
 
 static const struct of_device_id vf610_pinctrl_of_match[] = {
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Shawn Guo

2017-05-15 10:59 UTC #11 lore raw

PATCH 2/5 pinctrl: imx: add soc specific mux_mode mask and shift property

Quoted 12 lines · A.S. Dong

Quoted 11 lines
Review static int imx_pinconf_get(struct pinctrl_dev
Quoted 1 line
(quoted diff) +0 -0
@@ -432,7 +432,7 @@ static int imx_pinconf_get(struct pinctrl_dev
*pctldev,
drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinconf_get(struct pinctrl_dev *pctldev, · line 435
Quoted 5 lines
drivers/pinctrl/freescale/pinctrl-imx.c +1 -1
 	*config = readl(ipctl->base + pin_reg->conf_reg);
 
 	if (info->flags & SHARE_MUX_CONF_REG)
-		*config &= 0xffff;
+		*config &= ~info->mux_mask;
It changes the way how code works. We need a note in the commit log explaining why it's safe.

Quoted 5 lines

Well, that's Vybrid tricks that BIT[15-0] are all configs part. So it hardcoded 0xffff there.
But it's not true in ULP, so use mux_mask instead to address the difference.

So you make the assumption that for all SHARE_MUX_CONF_REG SoCs, all bits in the register except mux ones are config bits. You at least need to mention that in the commit log, IMO.

Shawn

A.S. Dong

author maintainer

2017-05-15 11:04 UTC #12 lore raw

PATCH 2/5 pinctrl: imx: add soc specific mux_mode mask and shift property

Quoted 26 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 6:59 PM
To: A.S. Dong
Cc: Andy Duan; Jacky Bai; linus.walleij at linaro.org; stefan at agner.ch; linux-gpio at vger.kernel.org; kernel at pengutronix.de; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH 2/5] pinctrl: imx: add soc specific mux_mode mask and shift property
Quoted 15 lines · A.S. Dong
Quoted 11 lines
Review static int imx_pinconf_get(struct pinctrl_dev
Quoted 1 line
(quoted diff) +0 -0
@@ -432,7 +432,7 @@ static int imx_pinconf_get(struct pinctrl_dev
*pctldev,
drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pinconf_get(struct pinctrl_dev *pctldev, · line 435
Quoted 5 lines
drivers/pinctrl/freescale/pinctrl-imx.c +1 -1
 	*config = readl(ipctl->base + pin_reg->conf_reg);
 
 	if (info->flags & SHARE_MUX_CONF_REG)
-		*config &= 0xffff;
+		*config &= ~info->mux_mask;
It changes the way how code works. We need a note in the commit log explaining why it's safe.
Well, that's Vybrid tricks that BIT[15-0] are all configs part. So it hardcoded 0xffff there.

Quoted 6 lines

Quoted 2 lines
But it's not true in ULP, so use mux_mask instead to address the difference.
So you make the assumption that for all SHARE_MUX_CONF_REG SoCs, all bits in the register except mux ones are config bits. You at least need to mention that in the commit log, IMO.

Yes, it's true, at least for all current known SoCs. But your suggestion is good, I can add it in commit log.

Thanks

Regards
Dong Aisheng

Quoted 2 lines

Shawn

Dong Aisheng

author maintainer

2017-05-12 12:38 UTC #13 lore raw

PATCH 2/5 pinctrl: pinctrl-imx: add soc specific mux_mode mask and shift property

In reply to Dong Aisheng

MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support.

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Stefan Agner <[email protected]>

Cc Bai Ping <[email protected]>

Signed-off-by Fugang Duan <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 drivers/pinctrl/freescale/pinctrl-imx.c   | 10 +++++-----
 drivers/pinctrl/freescale/pinctrl-imx.h   |  4 ++++
 drivers/pinctrl/freescale/pinctrl-vf610.c |  2 ++
 3 files changed, 11 insertions(+), 5 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +5 -5

index 406881d..ef4951f 100644
@@ -197,8 +197,8 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->mux_reg);
-			reg &= ~(0x7 << 20);
-			reg |= (pin->mux_mode << 20);
+			reg &= ~info->mux_mask;
+			reg |= (pin->mux_mode << info->mux_shift);
 			writel(reg, ipctl->base + pin_reg->mux_reg);
 		} else {
 			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);

@@ -288,7 +288,7 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
 
 mux_pin:
 	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~(0x7 << 20);
+	reg &= ~info->mux_mask;
 	reg |= imx_pin->config;
 	writel(reg, ipctl->base + pin_reg->mux_reg);

@@ -432,7 +432,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 	*config = readl(ipctl->base + pin_reg->conf_reg);
 
 	if (info->flags & SHARE_MUX_CONF_REG)
-		*config &= 0xffff;
+		*config &= ~info->mux_mask;
 
 	return 0;
 }

@@ -459,7 +459,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->conf_reg);
-			reg &= ~0xffff;
+			reg &= info->mux_mask;
 			reg |= configs[i];
 			writel(reg, ipctl->base + pin_reg->conf_reg);
 		} else {

drivers/pinctrl/freescale/pinctrl-imx.h +4 -0

index b5c8fe1..eb0ce95 100644
@@ -64,6 +64,10 @@ struct imx_pinctrl_soc_info {
 	const char *gpr_compatible;
 	struct mutex mutex;
 
+	/* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
+	unsigned int mux_mask;
+	u8 mux_shift;
+
 	/* generic pinconf */
 	bool generic_pinconf;
 	const struct pinconf_generic_params *custom_params;

drivers/pinctrl/freescale/pinctrl-vf610.c +2 -0

index 2b1e198..3bd8556 100644
@@ -299,6 +299,8 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
 	.pins = vf610_pinctrl_pads,
 	.npins = ARRAY_SIZE(vf610_pinctrl_pads),
 	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+	.mux_mask = 0x700000,
+	.mux_shift = 20,
 };
 
 static const struct of_device_id vf610_pinctrl_of_match[] = {

Signature · 1 line

2.7.4

A.S. Dong

author maintainer

2017-05-12 13:32 UTC #14 lore raw

PATCH 2/5 pinctrl: pinctrl-imx: add soc specific mux_mode mask and shift property

Quoted 14 lines

-----Original Message-----
From: Dong Aisheng [mailto:aisheng.dong at nxp.com]
Sent: Friday, May 12, 2017 8:38 PM
To: linux-gpio at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org; linus.walleij at linaro.org; shawnguo at kernel.org; stefan at agner.ch; Jacky Bai; Andy Duan; kernel at pengutronix.de; A.S. Dong
Subject: [PATCH 2/5] pinctrl: pinctrl-imx: add soc specific mux_mode mask and shift property
MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support.

Quoted 6 lines

Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Fugang Duan <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

Please ignore this one which is sent out accidentally.
It's actually the same as the following one except the patch title difference. [PATCH 2/5] pinctrl: imx: add soc specific mux_mode mask and shift property

Others all are ok.

Regards
Dong Aisheng

Quoted 84 lines

---
 drivers/pinctrl/freescale/pinctrl-imx.c   | 10 +++++-----
 drivers/pinctrl/freescale/pinctrl-imx.h   |  4 ++++
 drivers/pinctrl/freescale/pinctrl-vf610.c |  2 ++
 3 files changed, 11 insertions(+), 5 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +2 -2

index 406881d..ef4951f 100644
@@ -197,8 +197,8 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev,
 unsigned selector,
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->mux_reg);
-			reg &= ~(0x7 << 20);
-			reg |= (pin->mux_mode << 20);
+			reg &= ~info->mux_mask;
+			reg |= (pin->mux_mode << info->mux_shift);
 			writel(reg, ipctl->base + pin_reg->mux_reg);
 		} else {

drivers/pinctrl/freescale/pinctrl-imx.c +3 -3

 			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);

@@ -288,7 +288,7 @@ static int imx_pmx_gpio_request_enable(struct
 pinctrl_dev *pctldev,
 
 mux_pin:
 	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~(0x7 << 20);
+	reg &= ~info->mux_mask;
 	reg |= imx_pin->config;
 	writel(reg, ipctl->base + pin_reg->mux_reg);

@@ -432,7 +432,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 	*config = readl(ipctl->base + pin_reg->conf_reg);
 
 	if (info->flags & SHARE_MUX_CONF_REG)
-		*config &= 0xffff;
+		*config &= ~info->mux_mask;
 
 	return 0;
 }

@@ -459,7 +459,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->conf_reg);
-			reg &= ~0xffff;
+			reg &= info->mux_mask;
 			reg |= configs[i];
 			writel(reg, ipctl->base + pin_reg->conf_reg);
 		} else {

drivers/pinctrl/freescale/pinctrl-imx.h +4 -0

index b5c8fe1..eb0ce95 100644
@@ -64,6 +64,10 @@ struct imx_pinctrl_soc_info {
 	const char *gpr_compatible;
 	struct mutex mutex;
 
+	/* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
+	unsigned int mux_mask;
+	u8 mux_shift;
+
 	/* generic pinconf */
 	bool generic_pinconf;
 	const struct pinconf_generic_params *custom_params; diff --git

a/drivers/pinctrl/freescale/pinctrl-vf610.c
b/drivers/pinctrl/freescale/pinctrl-vf610.c
index 2b1e198..3bd8556 100644

drivers/pinctrl/freescale/pinctrl-vf610.c +2 -0

@@ -299,6 +299,8 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_info
 = {
 	.pins = vf610_pinctrl_pads,
 	.npins = ARRAY_SIZE(vf610_pinctrl_pads),
 	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+	.mux_mask = 0x700000,
+	.mux_shift = 20,
 };

static const struct of_device_id vf610_pinctrl_of_match[] = {
--
2.7.4

Dong Aisheng

author maintainer

2017-05-12 12:38 UTC #15 lore raw

PATCH 3/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

In reply to Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.

Cc Rob Herring <[email protected]>

Cc Mark Rutland <[email protected]>

Cc devicetree at vger.kernel.org

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  56 +++
 include/dt-bindings/pinctrl/imx7ulp-pinfunc.h      | 468 +++++++++++++++++++++
 2 files changed, 524 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 include/dt-bindings/pinctrl/imx7ulp-pinfunc.h

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +56 -0

new file mode 100644
index 0000000..0c1a48a
@@ -0,0 +1,56 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible:	"fsl,imx7ulp-iomuxc1"
+- reg:		Should contain the base physical address and size of the iomuxc
+		registers.
+
+=== Pin Configuration Node ===
+- pins: One integers array, represents a group of pins mux setting.
+	The format is fsl,pins = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
+	a specific function.
+
+	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
+	and config register as follows:
+	<mux_conf_reg input_reg mux_mode input_val>
+
+	Refer to imx7ulp-pinfunc.h in include/dt-bindings/pinctrl/imx7ulp-pinfunc.h
+	for all available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- output-buffer-enable:		Bool. Output buffer enabled
+- input-buffer-enable:		Bool. Input buffer enabled
+- drive-strength		Integer. Controls Drive Strength
+					0: Standard
+					1: Hi Driver
+- drive-push-pull		Bool. Enable Pin Push-pull
+- drive-open-drain		Bool. Enable Pin Open-drian
+- slew-rate:			Integer. Controls Slew Rate
+					0: Standard
+					1: Slow
+- bias-disable:			Bool. Pull disabled
+- bias-pull-down:		Bool. Pull down on pin
+- bias-pull-up:			Bool. Pull up on pin
+
+e.g.
+#include <dt-bindings/pinctrl/imx7ulp-pinfunc.h>
+
+/* Pin Controller Node */
+iomuxc1: iomuxc1 at 40ac0000 {
+	compatible = "fsl,imx7ulp-iomuxc1";
+	reg = <0x40ac0000 0x1000>;
+
+	/* Pin Configuration Node */
+	pinctrl_lpuart4: lpuart4grp {
+		pins = <
+			ULP1_PAD_PTC3__LPUART4_RX
+			ULP1_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+};

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +468 -0

468 lines not on this page · raw message

Signature · 1 line

2.7.4

Shawn Guo

2017-05-15 11:43 UTC #16 lore raw

PATCH 3/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 24 lines · Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.
This patch adds the IOMUXC1 support for A7.
Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  56 +++
 include/dt-bindings/pinctrl/imx7ulp-pinfunc.h      | 468 +++++++++++++++++++++
 2 files changed, 524 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 include/dt-bindings/pinctrl/imx7ulp-pinfunc.h
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +0 -0
new file mode 100644
index 0000000..0c1a48a

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 4

Quoted 4 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +4 -0
@@ -0,0 +1,56 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.

Are imx7ulp-pinctrl bindings more alike to fsl,imx-pinctrl.txt or generic pinctrl-bindings.txt? My personal feeling is that it might be better to take pinctrl-bindings.txt as the reference base and highlight how imx7ulp-pinctrl bindings differ from it.

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 11

Quoted 7 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +7 -0

+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible:	"fsl,imx7ulp-iomuxc1"
+- reg:		Should contain the base physical address and size of the iomuxc
+		registers.

Should we somehow document this is the one for Cortex-A7, or we name the compatible something like "fsl,imx7ulp-iomuxc-a7"?

Quoted 5 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +5 -0

+
+=== Pin Configuration Node ===
+- pins: One integers array, represents a group of pins mux setting.
+	The format is fsl,pins = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
+	a specific function.

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 26

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +10 -0

+
+	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
+	and config register as follows:
+	<mux_conf_reg input_reg mux_mode input_val>
+
+	Refer to imx7ulp-pinfunc.h in include/dt-bindings/pinctrl/imx7ulp-pinfunc.h
+	for all available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- output-buffer-enable:		Bool. Output buffer enabled

Shouldn't it be nxp,output-buffer-enable?

Quoted 4 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +4 -0
+- input-buffer-enable:		Bool. Input buffer enabled
+- drive-strength		Integer. Controls Drive Strength
+					0: Standard
+					1: Hi Driver

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 40

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +10 -0

+- drive-push-pull		Bool. Enable Pin Push-pull
+- drive-open-drain		Bool. Enable Pin Open-drian
+- slew-rate:			Integer. Controls Slew Rate
+					0: Standard
+					1: Slow
+- bias-disable:			Bool. Pull disabled
+- bias-pull-down:		Bool. Pull down on pin
+- bias-pull-up:			Bool. Pull up on pin
+
+e.g.

Examples:

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 44

Quoted 4 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +4 -0
+#include <dt-bindings/pinctrl/imx7ulp-pinfunc.h>
+
+/* Pin Controller Node */
+iomuxc1: iomuxc1 at 40ac0000 {

The number suffix doesn't make too much sense in node name.

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h

Quoted 17 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +12 -0
+	compatible = "fsl,imx7ulp-iomuxc1";
+	reg = <0x40ac0000 0x1000>;
+
+	/* Pin Configuration Node */
+	pinctrl_lpuart4: lpuart4grp {
+		pins = <
+			ULP1_PAD_PTC3__LPUART4_RX
+			ULP1_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+};
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +0 -0
new file mode 100644
index 0000000..b6db73f

The header will only be used by dts files, right? If so, arch/arm/boot/dts is the better place.

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 11

Quoted 12 lines

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +11 -0

@@ -0,0 +1,468 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_ULP1_PINFUNC_H

s/ULP1/IMX7ULP?

Shawn

Quoted 465 lines

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +457 -0

+#define __DTS_ULP1_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_conf_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define ULP1_PAD_PTC0__PTC0                                       0x0000 0x0000 0x1 0x0
+#define ULP1_PAD_PTC0__TRACE_D15                                  0x0000 0x0000 0xa 0x0
+#define ULP1_PAD_PTC0__LPUART4_CTS_B                              0x0000 0x0244 0x4 0x1
+#define ULP1_PAD_PTC0__LPI2C4_SCL                                 0x0000 0x0278 0x5 0x1
+#define ULP1_PAD_PTC0__TPM4_CLKIN                                 0x0000 0x0298 0x6 0x1
+#define ULP1_PAD_PTC0__FB_AD0                                     0x0000 0x0000 0x9 0x0
+#define ULP1_PAD_PTC1__PTC1                                       0x0004 0x0000 0x1 0x0
+#define ULP1_PAD_PTC1__TRACE_D14                                  0x0004 0x0000 0xa 0x0
+#define ULP1_PAD_PTC1__LPUART4_RTS_B                              0x0004 0x0000 0x4 0x0
+#define ULP1_PAD_PTC1__LPI2C4_SDA                                 0x0004 0x027c 0x5 0x1
+#define ULP1_PAD_PTC1__TPM4_CH0                                   0x0004 0x0280 0x6 0x1
+#define ULP1_PAD_PTC1__FB_AD1                                     0x0004 0x0000 0x9 0x0
+#define ULP1_PAD_PTC2__PTC2                                       0x0008 0x0000 0x1 0x0
+#define ULP1_PAD_PTC2__TRACE_D13                                  0x0008 0x0000 0xa 0x0
+#define ULP1_PAD_PTC2__LPUART4_TX                                 0x0008 0x024c 0x4 0x1
+#define ULP1_PAD_PTC2__LPI2C4_HREQ                                0x0008 0x0274 0x5 0x1
+#define ULP1_PAD_PTC2__TPM4_CH1                                   0x0008 0x0284 0x6 0x1
+#define ULP1_PAD_PTC2__FB_AD2                                     0x0008 0x0000 0x9 0x0
+#define ULP1_PAD_PTC3__PTC3                                       0x000c 0x0000 0x1 0x0
+#define ULP1_PAD_PTC3__TRACE_D12                                  0x000c 0x0000 0xa 0x0
+#define ULP1_PAD_PTC3__LPUART4_RX                                 0x000c 0x0248 0x4 0x1
+#define ULP1_PAD_PTC3__TPM4_CH2                                   0x000c 0x0288 0x6 0x1
+#define ULP1_PAD_PTC3__FB_AD3                                     0x000c 0x0000 0x9 0x0
+#define ULP1_PAD_PTC4__PTC4                                       0x0010 0x0000 0x1 0x0
+#define ULP1_PAD_PTC4__TRACE_D11                                  0x0010 0x0000 0xa 0x0
+#define ULP1_PAD_PTC4__FXIO1_D0                                   0x0010 0x0204 0x2 0x1
+#define ULP1_PAD_PTC4__LPSPI2_PCS1                                0x0010 0x02a0 0x3 0x1
+#define ULP1_PAD_PTC4__LPUART5_CTS_B                              0x0010 0x0250 0x4 0x1
+#define ULP1_PAD_PTC4__LPI2C5_SCL                                 0x0010 0x02bc 0x5 0x1
+#define ULP1_PAD_PTC4__TPM4_CH3                                   0x0010 0x028c 0x6 0x1
+#define ULP1_PAD_PTC4__FB_AD4                                     0x0010 0x0000 0x9 0x0
+#define ULP1_PAD_PTC5__PTC5                                       0x0014 0x0000 0x1 0x0
+#define ULP1_PAD_PTC5__TRACE_D10                                  0x0014 0x0000 0xa 0x0
+#define ULP1_PAD_PTC5__FXIO1_D1                                   0x0014 0x0208 0x2 0x1
+#define ULP1_PAD_PTC5__LPSPI2_PCS2                                0x0014 0x02a4 0x3 0x1
+#define ULP1_PAD_PTC5__LPUART5_RTS_B                              0x0014 0x0000 0x4 0x0
+#define ULP1_PAD_PTC5__LPI2C5_SDA                                 0x0014 0x02c0 0x5 0x1
+#define ULP1_PAD_PTC5__TPM4_CH4                                   0x0014 0x0290 0x6 0x1
+#define ULP1_PAD_PTC5__FB_AD5                                     0x0014 0x0000 0x9 0x0
+#define ULP1_PAD_PTC6__PTC6                                       0x0018 0x0000 0x1 0x0
+#define ULP1_PAD_PTC6__TRACE_D9                                   0x0018 0x0000 0xa 0x0
+#define ULP1_PAD_PTC6__FXIO1_D2                                   0x0018 0x020c 0x2 0x1
+#define ULP1_PAD_PTC6__LPSPI2_PCS3                                0x0018 0x02a8 0x3 0x1
+#define ULP1_PAD_PTC6__LPUART5_TX                                 0x0018 0x0258 0x4 0x1
+#define ULP1_PAD_PTC6__LPI2C5_HREQ                                0x0018 0x02b8 0x5 0x1
+#define ULP1_PAD_PTC6__TPM4_CH5                                   0x0018 0x0294 0x6 0x1
+#define ULP1_PAD_PTC6__FB_AD6                                     0x0018 0x0000 0x9 0x0
+#define ULP1_PAD_PTC7__PTC7                                       0x001c 0x0000 0x1 0x0
+#define ULP1_PAD_PTC7__TRACE_D8                                   0x001c 0x0000 0xa 0x0
+#define ULP1_PAD_PTC7__FXIO1_D3                                   0x001c 0x0210 0x2 0x1
+#define ULP1_PAD_PTC7__LPUART5_RX                                 0x001c 0x0254 0x4 0x1
+#define ULP1_PAD_PTC7__TPM5_CH1                                   0x001c 0x02c8 0x6 0x1
+#define ULP1_PAD_PTC7__FB_AD7                                     0x001c 0x0000 0x9 0x0
+#define ULP1_PAD_PTC8__PTC8                                       0x0020 0x0000 0x1 0x0
+#define ULP1_PAD_PTC8__TRACE_D7                                   0x0020 0x0000 0xa 0x0
+#define ULP1_PAD_PTC8__FXIO1_D4                                   0x0020 0x0214 0x2 0x1
+#define ULP1_PAD_PTC8__LPSPI2_SIN                                 0x0020 0x02b0 0x3 0x1
+#define ULP1_PAD_PTC8__LPUART6_CTS_B                              0x0020 0x025c 0x4 0x1
+#define ULP1_PAD_PTC8__LPI2C6_SCL                                 0x0020 0x02fc 0x5 0x1
+#define ULP1_PAD_PTC8__TPM5_CLKIN                                 0x0020 0x02cc 0x6 0x1
+#define ULP1_PAD_PTC8__FB_AD8                                     0x0020 0x0000 0x9 0x0
+#define ULP1_PAD_PTC9__PTC9                                       0x0024 0x0000 0x1 0x0
+#define ULP1_PAD_PTC9__TRACE_D6                                   0x0024 0x0000 0xa 0x0
+#define ULP1_PAD_PTC9__FXIO1_D5                                   0x0024 0x0218 0x2 0x1
+#define ULP1_PAD_PTC9__LPSPI2_SOUT                                0x0024 0x02b4 0x3 0x1
+#define ULP1_PAD_PTC9__LPUART6_RTS_B                              0x0024 0x0000 0x4 0x0
+#define ULP1_PAD_PTC9__LPI2C6_SDA                                 0x0024 0x0300 0x5 0x1
+#define ULP1_PAD_PTC9__TPM5_CH0                                   0x0024 0x02c4 0x6 0x1
+#define ULP1_PAD_PTC9__FB_AD9                                     0x0024 0x0000 0x9 0x0
+#define ULP1_PAD_PTC10__PTC10                                     0x0028 0x0000 0x1 0x0
+#define ULP1_PAD_PTC10__TRACE_D5                                  0x0028 0x0000 0xa 0x0
+#define ULP1_PAD_PTC10__FXIO1_D6                                  0x0028 0x021c 0x2 0x1
+#define ULP1_PAD_PTC10__LPSPI2_SCK                                0x0028 0x02ac 0x3 0x1
+#define ULP1_PAD_PTC10__LPUART6_TX                                0x0028 0x0264 0x4 0x1
+#define ULP1_PAD_PTC10__LPI2C6_HREQ                               0x0028 0x02f8 0x5 0x1
+#define ULP1_PAD_PTC10__TPM7_CH3                                  0x0028 0x02e8 0x6 0x1
+#define ULP1_PAD_PTC10__FB_AD10                                   0x0028 0x0000 0x9 0x0
+#define ULP1_PAD_PTC11__PTC11                                     0x002c 0x0000 0x1 0x0
+#define ULP1_PAD_PTC11__TRACE_D4                                  0x002c 0x0000 0xa 0x0
+#define ULP1_PAD_PTC11__FXIO1_D7                                  0x002c 0x0220 0x2 0x1
+#define ULP1_PAD_PTC11__LPSPI2_PCS0                               0x002c 0x029c 0x3 0x1
+#define ULP1_PAD_PTC11__LPUART6_RX                                0x002c 0x0260 0x4 0x1
+#define ULP1_PAD_PTC11__TPM7_CH4                                  0x002c 0x02ec 0x6 0x1
+#define ULP1_PAD_PTC11__FB_AD11                                   0x002c 0x0000 0x9 0x0
+#define ULP1_PAD_PTC12__PTC12                                     0x0030 0x0000 0x1 0x0
+#define ULP1_PAD_PTC12__TRACE_D3                                  0x0030 0x0000 0xa 0x0
+#define ULP1_PAD_PTC12__FXIO1_D8                                  0x0030 0x0224 0x2 0x1
+#define ULP1_PAD_PTC12__LPSPI3_PCS1                               0x0030 0x0314 0x3 0x1
+#define ULP1_PAD_PTC12__LPUART7_CTS_B                             0x0030 0x0268 0x4 0x1
+#define ULP1_PAD_PTC12__LPI2C7_SCL                                0x0030 0x0308 0x5 0x1
+#define ULP1_PAD_PTC12__TPM7_CH5                                  0x0030 0x02f0 0x6 0x1
+#define ULP1_PAD_PTC12__FB_AD12                                   0x0030 0x0000 0x9 0x0
+#define ULP1_PAD_PTC13__PTC13                                     0x0034 0x0000 0x1 0x0
+#define ULP1_PAD_PTC13__TRACE_D2                                  0x0034 0x0000 0xa 0x0
+#define ULP1_PAD_PTC13__FXIO1_D9                                  0x0034 0x0228 0x2 0x1
+#define ULP1_PAD_PTC13__LPSPI3_PCS2                               0x0034 0x0318 0x3 0x1
+#define ULP1_PAD_PTC13__LPUART7_RTS_B                             0x0034 0x0000 0x4 0x0
+#define ULP1_PAD_PTC13__LPI2C7_SDA                                0x0034 0x030c 0x5 0x1
+#define ULP1_PAD_PTC13__TPM7_CLKIN                                0x0034 0x02f4 0x6 0x1
+#define ULP1_PAD_PTC13__FB_AD13                                   0x0034 0x0000 0x9 0x0
+#define ULP1_PAD_PTC14__PTC14                                     0x0038 0x0000 0x1 0x0
+#define ULP1_PAD_PTC14__TRACE_D1                                  0x0038 0x0000 0xa 0x0
+#define ULP1_PAD_PTC14__FXIO1_D10                                 0x0038 0x022c 0x2 0x1
+#define ULP1_PAD_PTC14__LPSPI3_PCS3                               0x0038 0x031c 0x3 0x1
+#define ULP1_PAD_PTC14__LPUART7_TX                                0x0038 0x0270 0x4 0x1
+#define ULP1_PAD_PTC14__LPI2C7_HREQ                               0x0038 0x0304 0x5 0x1
+#define ULP1_PAD_PTC14__TPM7_CH0                                  0x0038 0x02dc 0x6 0x1
+#define ULP1_PAD_PTC14__FB_AD14                                   0x0038 0x0000 0x9 0x0
+#define ULP1_PAD_PTC15__PTC15                                     0x003c 0x0000 0x1 0x0
+#define ULP1_PAD_PTC15__TRACE_D0                                  0x003c 0x0000 0xa 0x0
+#define ULP1_PAD_PTC15__FXIO1_D11                                 0x003c 0x0230 0x2 0x1
+#define ULP1_PAD_PTC15__LPUART7_RX                                0x003c 0x026c 0x4 0x1
+#define ULP1_PAD_PTC15__TPM7_CH1                                  0x003c 0x02e0 0x6 0x1
+#define ULP1_PAD_PTC15__FB_AD15                                   0x003c 0x0000 0x9 0x0
+#define ULP1_PAD_PTC16__PTC16                                     0x0040 0x0000 0x1 0x0
+#define ULP1_PAD_PTC16__TRACE_CLKOUT                              0x0040 0x0000 0xa 0x0
+#define ULP1_PAD_PTC16__FXIO1_D12                                 0x0040 0x0234 0x2 0x1
+#define ULP1_PAD_PTC16__LPSPI3_SIN                                0x0040 0x0324 0x3 0x1
+#define ULP1_PAD_PTC16__TPM7_CH2                                  0x0040 0x02e4 0x6 0x1
+#define ULP1_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B                   0x0040 0x0000 0x9 0x0
+#define ULP1_PAD_PTC17__PTC17                                     0x0044 0x0000 0x1 0x0
+#define ULP1_PAD_PTC17__FXIO1_D13                                 0x0044 0x0238 0x2 0x1
+#define ULP1_PAD_PTC17__LPSPI3_SOUT                               0x0044 0x0328 0x3 0x1
+#define ULP1_PAD_PTC17__TPM6_CLKIN                                0x0044 0x02d8 0x6 0x1
+#define ULP1_PAD_PTC17__FB_CS0_B                                  0x0044 0x0000 0x9 0x0
+#define ULP1_PAD_PTC18__PTC18                                     0x0048 0x0000 0x1 0x0
+#define ULP1_PAD_PTC18__FXIO1_D14                                 0x0048 0x023c 0x2 0x1
+#define ULP1_PAD_PTC18__LPSPI3_SCK                                0x0048 0x0320 0x3 0x1
+#define ULP1_PAD_PTC18__TPM6_CH0                                  0x0048 0x02d0 0x6 0x1
+#define ULP1_PAD_PTC18__FB_OE_B                                   0x0048 0x0000 0x9 0x0
+#define ULP1_PAD_PTC19__PTC19                                     0x004c 0x0000 0x1 0x0
+#define ULP1_PAD_PTC19__FXIO1_D15                                 0x004c 0x0240 0x2 0x1
+#define ULP1_PAD_PTC19__LPSPI3_PCS0                               0x004c 0x0310 0x3 0x1
+#define ULP1_PAD_PTC19__TPM6_CH1                                  0x004c 0x02d4 0x6 0x1
+#define ULP1_PAD_PTC19__FB_A16                                    0x004c 0x0000 0x9 0x0
+#define ULP1_PAD_PTD0__PTD0                                       0x0080 0x0000 0x1 0x0
+#define ULP1_PAD_PTD0__SDHC0_RESET_B                              0x0080 0x0000 0x8 0x0
+#define ULP1_PAD_PTD1__PTD1                                       0x0084 0x0000 0x1 0x0
+#define ULP1_PAD_PTD1__SDHC0_CMD                                  0x0084 0x0000 0x8 0x0
+#define ULP1_PAD_PTD2__PTD2                                       0x0088 0x0000 0x1 0x0
+#define ULP1_PAD_PTD2__SDHC0_CLK                                  0x0088 0x0000 0x8 0x0
+#define ULP1_PAD_PTD3__PTD3                                       0x008c 0x0000 0x1 0x0
+#define ULP1_PAD_PTD3__SDHC0_D7                                   0x008c 0x0000 0x8 0x0
+#define ULP1_PAD_PTD4__PTD4                                       0x0090 0x0000 0x1 0x0
+#define ULP1_PAD_PTD4__SDHC0_D6                                   0x0090 0x0000 0x8 0x0
+#define ULP1_PAD_PTD5__PTD5                                       0x0094 0x0000 0x1 0x0
+#define ULP1_PAD_PTD5__SDHC0_D5                                   0x0094 0x0000 0x8 0x0
+#define ULP1_PAD_PTD6__PTD6                                       0x0098 0x0000 0x1 0x0
+#define ULP1_PAD_PTD6__SDHC0_D4                                   0x0098 0x0000 0x8 0x0
+#define ULP1_PAD_PTD7__PTD7                                       0x009c 0x0000 0x1 0x0
+#define ULP1_PAD_PTD7__SDHC0_D3                                   0x009c 0x0000 0x8 0x0
+#define ULP1_PAD_PTD8__PTD8                                       0x00a0 0x0000 0x1 0x0
+#define ULP1_PAD_PTD8__TPM4_CLKIN                                 0x00a0 0x0298 0x6 0x2
+#define ULP1_PAD_PTD8__SDHC0_D2                                   0x00a0 0x0000 0x8 0x0
+#define ULP1_PAD_PTD9__PTD9                                       0x00a4 0x0000 0x1 0x0
+#define ULP1_PAD_PTD9__TPM4_CH0                                   0x00a4 0x0280 0x6 0x2
+#define ULP1_PAD_PTD9__SDHC0_D1                                   0x00a4 0x0000 0x8 0x0
+#define ULP1_PAD_PTD10__PTD10                                     0x00a8 0x0000 0x1 0x0
+#define ULP1_PAD_PTD10__TPM4_CH1                                  0x00a8 0x0284 0x6 0x2
+#define ULP1_PAD_PTD10__SDHC0_D0                                  0x00a8 0x0000 0x8 0x0
+#define ULP1_PAD_PTD11__PTD11                                     0x00ac 0x0000 0x1 0x0
+#define ULP1_PAD_PTD11__TPM4_CH2                                  0x00ac 0x0288 0x6 0x2
+#define ULP1_PAD_PTD11__SDHC0_DQS                                 0x00ac 0x0000 0x8 0x0
+#define ULP1_PAD_PTE0__PTE0                                       0x0100 0x0000 0x1 0x0
+#define ULP1_PAD_PTE0__FXIO1_D31                                  0x0100 0x0000 0x2 0x0
+#define ULP1_PAD_PTE0__LPSPI2_PCS1                                0x0100 0x02a0 0x3 0x2
+#define ULP1_PAD_PTE0__LPUART4_CTS_B                              0x0100 0x0244 0x4 0x2
+#define ULP1_PAD_PTE0__LPI2C4_SCL                                 0x0100 0x0278 0x5 0x2
+#define ULP1_PAD_PTE0__SDHC1_D1                                   0x0100 0x0000 0x8 0x0
+#define ULP1_PAD_PTE0__FB_A25                                     0x0100 0x0000 0x9 0x0
+#define ULP1_PAD_PTE1__PTE1                                       0x0104 0x0000 0x1 0x0
+#define ULP1_PAD_PTE1__FXIO1_D30                                  0x0104 0x0000 0x2 0x0
+#define ULP1_PAD_PTE1__LPSPI2_PCS2                                0x0104 0x02a4 0x3 0x2
+#define ULP1_PAD_PTE1__LPUART4_RTS_B                              0x0104 0x0000 0x4 0x0
+#define ULP1_PAD_PTE1__LPI2C4_SDA                                 0x0104 0x027c 0x5 0x2
+#define ULP1_PAD_PTE1__SDHC1_D0                                   0x0104 0x0000 0x8 0x0
+#define ULP1_PAD_PTE1__FB_A26                                     0x0104 0x0000 0x9 0x0
+#define ULP1_PAD_PTE2__PTE2                                       0x0108 0x0000 0x1 0x0
+#define ULP1_PAD_PTE2__FXIO1_D29                                  0x0108 0x0000 0x2 0x0
+#define ULP1_PAD_PTE2__LPSPI2_PCS3                                0x0108 0x02a8 0x3 0x2
+#define ULP1_PAD_PTE2__LPUART4_TX                                 0x0108 0x024c 0x4 0x2
+#define ULP1_PAD_PTE2__LPI2C4_HREQ                                0x0108 0x0274 0x5 0x2
+#define ULP1_PAD_PTE2__SDHC1_CLK                                  0x0108 0x0000 0x8 0x0
+#define ULP1_PAD_PTE3__PTE3                                       0x010c 0x0000 0x1 0x0
+#define ULP1_PAD_PTE3__FXIO1_D28                                  0x010c 0x0000 0x2 0x0
+#define ULP1_PAD_PTE3__LPUART4_RX                                 0x010c 0x0248 0x4 0x2
+#define ULP1_PAD_PTE3__TPM5_CH1                                   0x010c 0x02c8 0x6 0x2
+#define ULP1_PAD_PTE3__SDHC1_CMD                                  0x010c 0x0000 0x8 0x0
+#define ULP1_PAD_PTE4__PTE4                                       0x0110 0x0000 0x1 0x0
+#define ULP1_PAD_PTE4__FXIO1_D27                                  0x0110 0x0000 0x2 0x0
+#define ULP1_PAD_PTE4__LPSPI2_SIN                                 0x0110 0x02b0 0x3 0x2
+#define ULP1_PAD_PTE4__LPUART5_CTS_B                              0x0110 0x0250 0x4 0x2
+#define ULP1_PAD_PTE4__LPI2C5_SCL                                 0x0110 0x02bc 0x5 0x2
+#define ULP1_PAD_PTE4__TPM5_CLKIN                                 0x0110 0x02cc 0x6 0x2
+#define ULP1_PAD_PTE4__SDHC1_D3                                   0x0110 0x0000 0x8 0x0
+#define ULP1_PAD_PTE5__PTE5                                       0x0114 0x0000 0x1 0x0
+#define ULP1_PAD_PTE5__FXIO1_D26                                  0x0114 0x0000 0x2 0x0
+#define ULP1_PAD_PTE5__LPSPI2_SOUT                                0x0114 0x02b4 0x3 0x2
+#define ULP1_PAD_PTE5__LPUART5_RTS_B                              0x0114 0x0000 0x4 0x0
+#define ULP1_PAD_PTE5__LPI2C5_SDA                                 0x0114 0x02c0 0x5 0x2
+#define ULP1_PAD_PTE5__TPM5_CH0                                   0x0114 0x02c4 0x6 0x2
+#define ULP1_PAD_PTE5__SDHC1_D2                                   0x0114 0x0000 0x8 0x0
+#define ULP1_PAD_PTE6__PTE6                                       0x0118 0x0000 0x1 0x0
+#define ULP1_PAD_PTE6__FXIO1_D25                                  0x0118 0x0000 0x2 0x0
+#define ULP1_PAD_PTE6__LPSPI2_SCK                                 0x0118 0x02ac 0x3 0x2
+#define ULP1_PAD_PTE6__LPUART5_TX                                 0x0118 0x0258 0x4 0x2
+#define ULP1_PAD_PTE6__LPI2C5_HREQ                                0x0118 0x02b8 0x5 0x2
+#define ULP1_PAD_PTE6__TPM7_CH3                                   0x0118 0x02e8 0x6 0x2
+#define ULP1_PAD_PTE6__SDHC1_D4                                   0x0118 0x0000 0x8 0x0
+#define ULP1_PAD_PTE6__FB_A17                                     0x0118 0x0000 0x9 0x0
+#define ULP1_PAD_PTE7__PTE7                                       0x011c 0x0000 0x1 0x0
+#define ULP1_PAD_PTE7__TRACE_D7                                   0x011c 0x0000 0xa 0x0
+#define ULP1_PAD_PTE7__VIU_FID                                    0x011c 0x0000 0xc 0x0
+#define ULP1_PAD_PTE7__FXIO1_D24                                  0x011c 0x0000 0x2 0x0
+#define ULP1_PAD_PTE7__LPSPI2_PCS0                                0x011c 0x029c 0x3 0x2
+#define ULP1_PAD_PTE7__LPUART5_RX                                 0x011c 0x0254 0x4 0x2
+#define ULP1_PAD_PTE7__TPM7_CH4                                   0x011c 0x02ec 0x6 0x2
+#define ULP1_PAD_PTE7__SDHC1_D5                                   0x011c 0x0000 0x8 0x0
+#define ULP1_PAD_PTE7__FB_A18                                     0x011c 0x0000 0x9 0x0
+#define ULP1_PAD_PTE8__PTE8                                       0x0120 0x0000 0x1 0x0
+#define ULP1_PAD_PTE8__TRACE_D6                                   0x0120 0x0000 0xa 0x0
+#define ULP1_PAD_PTE8__VIU_D16                                    0x0120 0x0000 0xc 0x0
+#define ULP1_PAD_PTE8__FXIO1_D23                                  0x0120 0x0000 0x2 0x0
+#define ULP1_PAD_PTE8__LPSPI3_PCS1                                0x0120 0x0314 0x3 0x2
+#define ULP1_PAD_PTE8__LPUART6_CTS_B                              0x0120 0x025c 0x4 0x2
+#define ULP1_PAD_PTE8__LPI2C6_SCL                                 0x0120 0x02fc 0x5 0x2
+#define ULP1_PAD_PTE8__TPM7_CH5                                   0x0120 0x02f0 0x6 0x2
+#define ULP1_PAD_PTE8__SDHC1_WP                                   0x0120 0x0200 0x7 0x1
+#define ULP1_PAD_PTE8__SDHC1_D6                                   0x0120 0x0000 0x8 0x0
+#define ULP1_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B               0x0120 0x0000 0x9 0x0
+#define ULP1_PAD_PTE9__PTE9                                       0x0124 0x0000 0x1 0x0
+#define ULP1_PAD_PTE9__TRACE_D5                                   0x0124 0x0000 0xa 0x0
+#define ULP1_PAD_PTE9__VIU_D17                                    0x0124 0x0000 0xc 0x0
+#define ULP1_PAD_PTE9__FXIO1_D22                                  0x0124 0x0000 0x2 0x0
+#define ULP1_PAD_PTE9__LPSPI3_PCS2                                0x0124 0x0318 0x3 0x2
+#define ULP1_PAD_PTE9__LPUART6_RTS_B                              0x0124 0x0000 0x4 0x0
+#define ULP1_PAD_PTE9__LPI2C6_SDA                                 0x0124 0x0300 0x5 0x2
+#define ULP1_PAD_PTE9__TPM7_CLKIN                                 0x0124 0x02f4 0x6 0x2
+#define ULP1_PAD_PTE9__SDHC1_CD                                   0x0124 0x032c 0x7 0x1
+#define ULP1_PAD_PTE9__SDHC1_D7                                   0x0124 0x0000 0x8 0x0
+#define ULP1_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B    0x0124 0x0000 0x9 0x0
+#define ULP1_PAD_PTE10__PTE10                                     0x0128 0x0000 0x1 0x0
+#define ULP1_PAD_PTE10__TRACE_D4                                  0x0128 0x0000 0xa 0x0
+#define ULP1_PAD_PTE10__VIU_D18                                   0x0128 0x0000 0xc 0x0
+#define ULP1_PAD_PTE10__FXIO1_D21                                 0x0128 0x0000 0x2 0x0
+#define ULP1_PAD_PTE10__LPSPI3_PCS3                               0x0128 0x031c 0x3 0x2
+#define ULP1_PAD_PTE10__LPUART6_TX                                0x0128 0x0264 0x4 0x2
+#define ULP1_PAD_PTE10__LPI2C6_HREQ                               0x0128 0x02f8 0x5 0x2
+#define ULP1_PAD_PTE10__TPM7_CH0                                  0x0128 0x02dc 0x6 0x2
+#define ULP1_PAD_PTE10__SDHC1_VS                                  0x0128 0x0000 0x7 0x0
+#define ULP1_PAD_PTE10__SDHC1_DQS                                 0x0128 0x0000 0x8 0x0
+#define ULP1_PAD_PTE10__FB_A19                                    0x0128 0x0000 0x9 0x0
+#define ULP1_PAD_PTE11__PTE11                                     0x012c 0x0000 0x1 0x0
+#define ULP1_PAD_PTE11__TRACE_D3                                  0x012c 0x0000 0xa 0x0
+#define ULP1_PAD_PTE11__VIU_D19                                   0x012c 0x0000 0xc 0x0
+#define ULP1_PAD_PTE11__FXIO1_D20                                 0x012c 0x0000 0x2 0x0
+#define ULP1_PAD_PTE11__LPUART6_RX                                0x012c 0x0260 0x4 0x2
+#define ULP1_PAD_PTE11__TPM7_CH1                                  0x012c 0x02e0 0x6 0x2
+#define ULP1_PAD_PTE11__SDHC1_RESET_B                             0x012c 0x0000 0x8 0x0
+#define ULP1_PAD_PTE11__FB_A20                                    0x012c 0x0000 0x9 0x0
+#define ULP1_PAD_PTE12__PTE12                                     0x0130 0x0000 0x1 0x0
+#define ULP1_PAD_PTE12__TRACE_D2                                  0x0130 0x0000 0xa 0x0
+#define ULP1_PAD_PTE12__VIU_D20                                   0x0130 0x0000 0xc 0x0
+#define ULP1_PAD_PTE12__FXIO1_D19                                 0x0130 0x0000 0x2 0x0
+#define ULP1_PAD_PTE12__LPSPI3_SIN                                0x0130 0x0324 0x3 0x2
+#define ULP1_PAD_PTE12__LPUART7_CTS_B                             0x0130 0x0268 0x4 0x2
+#define ULP1_PAD_PTE12__LPI2C7_SCL                                0x0130 0x0308 0x5 0x2
+#define ULP1_PAD_PTE12__TPM7_CH2                                  0x0130 0x02e4 0x6 0x2
+#define ULP1_PAD_PTE12__SDHC1_WP                                  0x0130 0x0200 0x8 0x2
+#define ULP1_PAD_PTE12__FB_A21                                    0x0130 0x0000 0x9 0x0
+#define ULP1_PAD_PTE13__PTE13                                     0x0134 0x0000 0x1 0x0
+#define ULP1_PAD_PTE13__TRACE_D1                                  0x0134 0x0000 0xa 0x0
+#define ULP1_PAD_PTE13__VIU_D21                                   0x0134 0x0000 0xc 0x0
+#define ULP1_PAD_PTE13__FXIO1_D18                                 0x0134 0x0000 0x2 0x0
+#define ULP1_PAD_PTE13__LPSPI3_SOUT                               0x0134 0x0328 0x3 0x2
+#define ULP1_PAD_PTE13__LPUART7_RTS_B                             0x0134 0x0000 0x4 0x0
+#define ULP1_PAD_PTE13__LPI2C7_SDA                                0x0134 0x030c 0x5 0x2
+#define ULP1_PAD_PTE13__TPM6_CLKIN                                0x0134 0x02d8 0x6 0x2
+#define ULP1_PAD_PTE13__SDHC1_CD                                  0x0134 0x032c 0x8 0x2
+#define ULP1_PAD_PTE13__FB_A22                                    0x0134 0x0000 0x9 0x0
+#define ULP1_PAD_PTE14__PTE14                                     0x0138 0x0000 0x1 0x0
+#define ULP1_PAD_PTE14__TRACE_D0                                  0x0138 0x0000 0xa 0x0
+#define ULP1_PAD_PTE14__VIU_D22                                   0x0138 0x0000 0xc 0x0
+#define ULP1_PAD_PTE14__FXIO1_D17                                 0x0138 0x0000 0x2 0x0
+#define ULP1_PAD_PTE14__LPSPI3_SCK                                0x0138 0x0320 0x3 0x2
+#define ULP1_PAD_PTE14__LPUART7_TX                                0x0138 0x0270 0x4 0x2
+#define ULP1_PAD_PTE14__LPI2C7_HREQ                               0x0138 0x0304 0x5 0x2
+#define ULP1_PAD_PTE14__TPM6_CH0                                  0x0138 0x02d0 0x6 0x2
+#define ULP1_PAD_PTE14__SDHC1_VS                                  0x0138 0x0000 0x8 0x0
+#define ULP1_PAD_PTE14__FB_A23                                    0x0138 0x0000 0x9 0x0
+#define ULP1_PAD_PTE15__PTE15                                     0x013c 0x0000 0x1 0x0
+#define ULP1_PAD_PTE15__TRACE_CLKOUT                              0x013c 0x0000 0xa 0x0
+#define ULP1_PAD_PTE15__VIU_D23                                   0x013c 0x0000 0xc 0x0
+#define ULP1_PAD_PTE15__FXIO1_D16                                 0x013c 0x0000 0x2 0x0
+#define ULP1_PAD_PTE15__LPSPI3_PCS0                               0x013c 0x0310 0x3 0x2
+#define ULP1_PAD_PTE15__LPUART7_RX                                0x013c 0x026c 0x4 0x2
+#define ULP1_PAD_PTE15__TPM6_CH1                                  0x013c 0x02d4 0x6 0x2
+#define ULP1_PAD_PTE15__FB_A24                                    0x013c 0x0000 0x9 0x0
+#define ULP1_PAD_PTF0__PTF0                                       0x0180 0x0000 0x1 0x0
+#define ULP1_PAD_PTF0__VIU_DE                                     0x0180 0x0000 0xc 0x0
+#define ULP1_PAD_PTF0__LPUART4_CTS_B                              0x0180 0x0244 0x4 0x3
+#define ULP1_PAD_PTF0__LPI2C4_SCL                                 0x0180 0x0278 0x5 0x3
+#define ULP1_PAD_PTF0__TPM4_CLKIN                                 0x0180 0x0298 0x6 0x3
+#define ULP1_PAD_PTF0__FB_RW_B                                    0x0180 0x0000 0x9 0x0
+#define ULP1_PAD_PTF1__PTF1                                       0x0184 0x0000 0x1 0x0
+#define ULP1_PAD_PTF1__VIU_HSYNC                                  0x0184 0x0000 0xc 0x0
+#define ULP1_PAD_PTF1__LPUART4_RTS_B                              0x0184 0x0000 0x4 0x0
+#define ULP1_PAD_PTF1__LPI2C4_SDA                                 0x0184 0x027c 0x5 0x3
+#define ULP1_PAD_PTF1__TPM4_CH0                                   0x0184 0x0280 0x6 0x3
+#define ULP1_PAD_PTF1__CLKOUT                                     0x0184 0x0000 0x9 0x0
+#define ULP1_PAD_PTF2__PTF2                                       0x0188 0x0000 0x1 0x0
+#define ULP1_PAD_PTF2__VIU_VSYNC                                  0x0188 0x0000 0xc 0x0
+#define ULP1_PAD_PTF2__LPUART4_TX                                 0x0188 0x024c 0x4 0x3
+#define ULP1_PAD_PTF2__LPI2C4_HREQ                                0x0188 0x0274 0x5 0x3
+#define ULP1_PAD_PTF2__TPM4_CH1                                   0x0188 0x0284 0x6 0x3
+#define ULP1_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B     0x0188 0x0000 0x9 0x0
+#define ULP1_PAD_PTF3__PTF3                                       0x018c 0x0000 0x1 0x0
+#define ULP1_PAD_PTF3__VIU_PCLK                                   0x018c 0x0000 0xc 0x0
+#define ULP1_PAD_PTF3__LPUART4_RX                                 0x018c 0x0248 0x4 0x3
+#define ULP1_PAD_PTF3__TPM4_CH2                                   0x018c 0x0288 0x6 0x3
+#define ULP1_PAD_PTF3__FB_AD16                                    0x018c 0x0000 0x9 0x0
+#define ULP1_PAD_PTF4__PTF4                                       0x0190 0x0000 0x1 0x0
+#define ULP1_PAD_PTF4__VIU_D0                                     0x0190 0x0000 0xc 0x0
+#define ULP1_PAD_PTF4__FXIO1_D0                                   0x0190 0x0204 0x2 0x2
+#define ULP1_PAD_PTF4__LPSPI2_PCS1                                0x0190 0x02a0 0x3 0x3
+#define ULP1_PAD_PTF4__LPUART5_CTS_B                              0x0190 0x0250 0x4 0x3
+#define ULP1_PAD_PTF4__LPI2C5_SCL                                 0x0190 0x02bc 0x5 0x3
+#define ULP1_PAD_PTF4__TPM4_CH3                                   0x0190 0x028c 0x6 0x2
+#define ULP1_PAD_PTF4__FB_AD17                                    0x0190 0x0000 0x9 0x0
+#define ULP1_PAD_PTF5__PTF5                                       0x0194 0x0000 0x1 0x0
+#define ULP1_PAD_PTF5__VIU_D1                                     0x0194 0x0000 0xc 0x0
+#define ULP1_PAD_PTF5__FXIO1_D1                                   0x0194 0x0208 0x2 0x2
+#define ULP1_PAD_PTF5__LPSPI2_PCS2                                0x0194 0x02a4 0x3 0x3
+#define ULP1_PAD_PTF5__LPUART5_RTS_B                              0x0194 0x0000 0x4 0x0
+#define ULP1_PAD_PTF5__LPI2C5_SDA                                 0x0194 0x02c0 0x5 0x3
+#define ULP1_PAD_PTF5__TPM4_CH4                                   0x0194 0x0290 0x6 0x2
+#define ULP1_PAD_PTF5__FB_AD18                                    0x0194 0x0000 0x9 0x0
+#define ULP1_PAD_PTF6__PTF6                                       0x0198 0x0000 0x1 0x0
+#define ULP1_PAD_PTF6__VIU_D2                                     0x0198 0x0000 0xc 0x0
+#define ULP1_PAD_PTF6__FXIO1_D2                                   0x0198 0x020c 0x2 0x2
+#define ULP1_PAD_PTF6__LPSPI2_PCS3                                0x0198 0x02a8 0x3 0x3
+#define ULP1_PAD_PTF6__LPUART5_TX                                 0x0198 0x0258 0x4 0x3
+#define ULP1_PAD_PTF6__LPI2C5_HREQ                                0x0198 0x02b8 0x5 0x3
+#define ULP1_PAD_PTF6__TPM4_CH5                                   0x0198 0x0294 0x6 0x2
+#define ULP1_PAD_PTF6__FB_AD19                                    0x0198 0x0000 0x9 0x0
+#define ULP1_PAD_PTF7__PTF7                                       0x019c 0x0000 0x1 0x0
+#define ULP1_PAD_PTF7__VIU_D3                                     0x019c 0x0000 0xc 0x0
+#define ULP1_PAD_PTF7__FXIO1_D3                                   0x019c 0x0210 0x2 0x2
+#define ULP1_PAD_PTF7__LPUART5_RX                                 0x019c 0x0254 0x4 0x3
+#define ULP1_PAD_PTF7__TPM5_CH1                                   0x019c 0x02c8 0x6 0x3
+#define ULP1_PAD_PTF7__FB_AD20                                    0x019c 0x0000 0x9 0x0
+#define ULP1_PAD_PTF8__PTF8                                       0x01a0 0x0000 0x1 0x0
+#define ULP1_PAD_PTF8__USB1_ULPI_CLK                              0x01a0 0x0000 0xb 0x0
+#define ULP1_PAD_PTF8__VIU_D4                                     0x01a0 0x0000 0xc 0x0
+#define ULP1_PAD_PTF8__FXIO1_D4                                   0x01a0 0x0214 0x2 0x2
+#define ULP1_PAD_PTF8__LPSPI2_SIN                                 0x01a0 0x02b0 0x3 0x3
+#define ULP1_PAD_PTF8__LPUART6_CTS_B                              0x01a0 0x025c 0x4 0x3
+#define ULP1_PAD_PTF8__LPI2C6_SCL                                 0x01a0 0x02fc 0x5 0x3
+#define ULP1_PAD_PTF8__TPM5_CLKIN                                 0x01a0 0x02cc 0x6 0x3
+#define ULP1_PAD_PTF8__FB_AD21                                    0x01a0 0x0000 0x9 0x0
+#define ULP1_PAD_PTF9__PTF9                                       0x01a4 0x0000 0x1 0x0
+#define ULP1_PAD_PTF9__USB1_ULPI_NXT                              0x01a4 0x0000 0xb 0x0
+#define ULP1_PAD_PTF9__VIU_D5                                     0x01a4 0x0000 0xc 0x0
+#define ULP1_PAD_PTF9__FXIO1_D5                                   0x01a4 0x0218 0x2 0x2
+#define ULP1_PAD_PTF9__LPSPI2_SOUT                                0x01a4 0x02b4 0x3 0x3
+#define ULP1_PAD_PTF9__LPUART6_RTS_B                              0x01a4 0x0000 0x4 0x0
+#define ULP1_PAD_PTF9__LPI2C6_SDA                                 0x01a4 0x0300 0x5 0x3
+#define ULP1_PAD_PTF9__TPM5_CH0                                   0x01a4 0x02c4 0x6 0x3
+#define ULP1_PAD_PTF9__FB_AD22                                    0x01a4 0x0000 0x9 0x0
+#define ULP1_PAD_PTF10__PTF10                                     0x01a8 0x0000 0x1 0x0
+#define ULP1_PAD_PTF10__USB1_ULPI_STP                             0x01a8 0x0000 0xb 0x0
+#define ULP1_PAD_PTF10__VIU_D6                                    0x01a8 0x0000 0xc 0x0
+#define ULP1_PAD_PTF10__FXIO1_D6                                  0x01a8 0x021c 0x2 0x2
+#define ULP1_PAD_PTF10__LPSPI2_SCK                                0x01a8 0x02ac 0x3 0x3
+#define ULP1_PAD_PTF10__LPUART6_TX                                0x01a8 0x0264 0x4 0x3
+#define ULP1_PAD_PTF10__LPI2C6_HREQ                               0x01a8 0x02f8 0x5 0x3
+#define ULP1_PAD_PTF10__TPM7_CH3                                  0x01a8 0x02e8 0x6 0x3
+#define ULP1_PAD_PTF10__FB_AD23                                   0x01a8 0x0000 0x9 0x0
+#define ULP1_PAD_PTF11__PTF11                                     0x01ac 0x0000 0x1 0x0
+#define ULP1_PAD_PTF11__USB1_ULPI_DIR                             0x01ac 0x0000 0xb 0x0
+#define ULP1_PAD_PTF11__VIU_D7                                    0x01ac 0x0000 0xc 0x0
+#define ULP1_PAD_PTF11__FXIO1_D7                                  0x01ac 0x0220 0x2 0x2
+#define ULP1_PAD_PTF11__LPSPI2_PCS0                               0x01ac 0x029c 0x3 0x3
+#define ULP1_PAD_PTF11__LPUART6_RX                                0x01ac 0x0260 0x4 0x3
+#define ULP1_PAD_PTF11__TPM7_CH4                                  0x01ac 0x02ec 0x6 0x3
+#define ULP1_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B     0x01ac 0x0000 0x9 0x0
+#define ULP1_PAD_PTF12__PTF12                                     0x01b0 0x0000 0x1 0x0
+#define ULP1_PAD_PTF12__USB1_ULPI_DATA0                           0x01b0 0x0000 0xb 0x0
+#define ULP1_PAD_PTF12__VIU_D8                                    0x01b0 0x0000 0xc 0x0
+#define ULP1_PAD_PTF12__FXIO1_D8                                  0x01b0 0x0224 0x2 0x2
+#define ULP1_PAD_PTF12__LPSPI3_PCS1                               0x01b0 0x0314 0x3 0x3
+#define ULP1_PAD_PTF12__LPUART7_CTS_B                             0x01b0 0x0268 0x4 0x3
+#define ULP1_PAD_PTF12__LPI2C7_SCL                                0x01b0 0x0308 0x5 0x3
+#define ULP1_PAD_PTF12__TPM7_CH5                                  0x01b0 0x02f0 0x6 0x3
+#define ULP1_PAD_PTF12__FB_AD24                                   0x01b0 0x0000 0x9 0x0
+#define ULP1_PAD_PTF13__PTF13                                     0x01b4 0x0000 0x1 0x0
+#define ULP1_PAD_PTF13__USB1_ULPI_DATA1                           0x01b4 0x0000 0xb 0x0
+#define ULP1_PAD_PTF13__VIU_D9                                    0x01b4 0x0000 0xc 0x0
+#define ULP1_PAD_PTF13__FXIO1_D9                                  0x01b4 0x0228 0x2 0x2
+#define ULP1_PAD_PTF13__LPSPI3_PCS2                               0x01b4 0x0318 0x3 0x3
+#define ULP1_PAD_PTF13__LPUART7_RTS_B                             0x01b4 0x0000 0x4 0x0
+#define ULP1_PAD_PTF13__LPI2C7_SDA                                0x01b4 0x030c 0x5 0x3
+#define ULP1_PAD_PTF13__TPM7_CLKIN                                0x01b4 0x02f4 0x6 0x3
+#define ULP1_PAD_PTF13__FB_AD25                                   0x01b4 0x0000 0x9 0x0
+#define ULP1_PAD_PTF14__PTF14                                     0x01b8 0x0000 0x1 0x0
+#define ULP1_PAD_PTF14__USB1_ULPI_DATA2                           0x01b8 0x0000 0xb 0x0
+#define ULP1_PAD_PTF14__VIU_D10                                   0x01b8 0x0000 0xc 0x0
+#define ULP1_PAD_PTF14__FXIO1_D10                                 0x01b8 0x022c 0x2 0x2
+#define ULP1_PAD_PTF14__LPSPI3_PCS3                               0x01b8 0x031c 0x3 0x3
+#define ULP1_PAD_PTF14__LPUART7_TX                                0x01b8 0x0270 0x4 0x3
+#define ULP1_PAD_PTF14__LPI2C7_HREQ                               0x01b8 0x0304 0x5 0x3
+#define ULP1_PAD_PTF14__TPM7_CH0                                  0x01b8 0x02dc 0x6 0x3
+#define ULP1_PAD_PTF14__FB_AD26                                   0x01b8 0x0000 0x9 0x0
+#define ULP1_PAD_PTF15__PTF15                                     0x01bc 0x0000 0x1 0x0
+#define ULP1_PAD_PTF15__USB1_ULPI_DATA3                           0x01bc 0x0000 0xb 0x0
+#define ULP1_PAD_PTF15__VIU_D11                                   0x01bc 0x0000 0xc 0x0
+#define ULP1_PAD_PTF15__FXIO1_D11                                 0x01bc 0x0230 0x2 0x2
+#define ULP1_PAD_PTF15__LPUART7_RX                                0x01bc 0x026c 0x4 0x3
+#define ULP1_PAD_PTF15__TPM7_CH1                                  0x01bc 0x02e0 0x6 0x3
+#define ULP1_PAD_PTF15__FB_AD27                                   0x01bc 0x0000 0x9 0x0
+#define ULP1_PAD_PTF16__PTF16                                     0x01c0 0x0000 0x1 0x0
+#define ULP1_PAD_PTF16__USB1_ULPI_DATA4                           0x01c0 0x0000 0xb 0x0
+#define ULP1_PAD_PTF16__VIU_D12                                   0x01c0 0x0000 0xc 0x0
+#define ULP1_PAD_PTF16__FXIO1_D12                                 0x01c0 0x0234 0x2 0x2
+#define ULP1_PAD_PTF16__LPSPI3_SIN                                0x01c0 0x0324 0x3 0x3
+#define ULP1_PAD_PTF16__TPM7_CH2                                  0x01c0 0x02e4 0x6 0x3
+#define ULP1_PAD_PTF16__FB_AD28                                   0x01c0 0x0000 0x9 0x0
+#define ULP1_PAD_PTF17__PTF17                                     0x01c4 0x0000 0x1 0x0
+#define ULP1_PAD_PTF17__USB1_ULPI_DATA5                           0x01c4 0x0000 0xb 0x0
+#define ULP1_PAD_PTF17__VIU_D13                                   0x01c4 0x0000 0xc 0x0
+#define ULP1_PAD_PTF17__FXIO1_D13                                 0x01c4 0x0238 0x2 0x2
+#define ULP1_PAD_PTF17__LPSPI3_SOUT                               0x01c4 0x0328 0x3 0x3
+#define ULP1_PAD_PTF17__TPM6_CLKIN                                0x01c4 0x02d8 0x6 0x3
+#define ULP1_PAD_PTF17__FB_AD29                                   0x01c4 0x0000 0x9 0x0
+#define ULP1_PAD_PTF18__PTF18                                     0x01c8 0x0000 0x1 0x0
+#define ULP1_PAD_PTF18__USB1_ULPI_DATA6                           0x01c8 0x0000 0xb 0x0
+#define ULP1_PAD_PTF18__VIU_D14                                   0x01c8 0x0000 0xc 0x0
+#define ULP1_PAD_PTF18__FXIO1_D14                                 0x01c8 0x023c 0x2 0x2
+#define ULP1_PAD_PTF18__LPSPI3_SCK                                0x01c8 0x0320 0x3 0x3
+#define ULP1_PAD_PTF18__TPM6_CH0                                  0x01c8 0x02d0 0x6 0x3
+#define ULP1_PAD_PTF18__FB_AD30                                   0x01c8 0x0000 0x9 0x0
+#define ULP1_PAD_PTF19__PTF19                                     0x01cc 0x0000 0x1 0x0
+#define ULP1_PAD_PTF19__USB1_ULPI_DATA7                           0x01cc 0x0000 0xb 0x0
+#define ULP1_PAD_PTF19__VIU_D15                                   0x01cc 0x0000 0xc 0x0
+#define ULP1_PAD_PTF19__FXIO1_D15                                 0x01cc 0x0240 0x2 0x2
+#define ULP1_PAD_PTF19__LPSPI3_PCS0                               0x01cc 0x0310 0x3 0x3
+#define ULP1_PAD_PTF19__TPM6_CH1                                  0x01cc 0x02d4 0x6 0x3
+#define ULP1_PAD_PTF19__FB_AD31                                   0x01cc 0x0000 0x9 0x0
+
+#endif /* __DTS_ULP1_PINFUNC_H */

Signature · 7 lines

2.7.4


_______________________________________________
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linux-arm-kernel at lists.infradead.org
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A.S. Dong

author maintainer

2017-05-15 12:06 UTC #17 lore raw

PATCH 3/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 41 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 7:43 PM
To: A.S. Dong
Cc: linux-gpio at vger.kernel.org; Mark Rutland; Andy Duan; Jacky Bai; devicetree at vger.kernel.org; linus.walleij at linaro.org; stefan at agner.ch; Rob Herring; kernel at pengutronix.de; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 3/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc
Quoted 11 lines · Dong Aisheng
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.
This patch adds the IOMUXC1 support for A7.
Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
Quoted 3 lines
---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  56 +++
 include/dt-bindings/pinctrl/imx7ulp-pinfunc.h      | 468
+++++++++++++++++++++
Quoted 15 lines
 2 files changed, 524 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 include/dt-bindings/pinctrl/imx7ulp-pinfunc.h
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file mode 100644
index 0000000..0c1a48a
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +2 -0
+++ t
@@ -0,0 +1,56 @@
+* Freescale i.MX7ULP IOMUX Controller

Quoted 9 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 4
Quoted 3 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +3 -0
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common
+binding part and usage.
Are imx7ulp-pinctrl bindings more alike to fsl,imx-pinctrl.txt or generic pinctrl-bindings.txt? My personal feeling is that it might be better to take pinctrl-bindings.txt as the reference base and highlight how imx7ulp- pinctrl bindings differ from it.

It seems still more like fsl,imx-pinctrl.txt.

I know fsl,imx-pinctrl.txt is a bit out of date, especially after we add generic pinconf.

I plan to update it later after adding generic pin conf support to legacy SoCs (MX6 & 7) as well, do you think it's ok?

Moreover, I think keeping imx in the same common binding doc is still better.

Quoted 7 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 10
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +6 -0
+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible:	"fsl,imx7ulp-iomuxc1"
+- reg:		Should contain the base physical address and size of the
iomuxc

Quoted 5 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 11
Quoted 1 line
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +1 -0
+		registers.
Should we somehow document this is the one for Cortex-A7, or we name the compatible something like "fsl,imx7ulp-iomuxc-a7"?

Hmm.. It stucks me.
I did stop a few minutes on the name before.
As in the reference manual, it's officially named IOMUXC1 for A7 and IOMUXC0 for M4,
So I'm not sure if it's really necessary to change.

Quoted 14 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 15
Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +4 -0
+
+=== Pin Configuration Node ===
+- pins: One integers array, represents a group of pins mux setting.
+	The format is fsl,pins = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working
on
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 18
Quoted 3 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +3 -0
+	a specific function.
+
+	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one
mux
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 22
Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +4 -0
+	and config register as follows:
+	<mux_conf_reg input_reg mux_mode input_val>
+
+	Refer to imx7ulp-pinfunc.h in include/dt-bindings/pinctrl/imx7ulp-
pinfunc.h

Quoted 7 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 26
Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +4 -0
+	for all available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- output-buffer-enable:		Bool. Output buffer enabled
Shouldn't it be nxp,output-buffer-enable?

You're right, good catch.

Quoted 8 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +8 -0

+- input-buffer-enable:		Bool. Input buffer enabled
+- drive-strength		Integer. Controls Drive Strength
+					0: Standard
+					1: Hi Driver
+- drive-push-pull		Bool. Enable Pin Push-pull
+- drive-open-drain		Bool. Enable Pin Open-drian
+- slew-rate:			Integer. Controls Slew Rate
+					0: Standard

Quoted 9 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 40
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +6 -0
+					1: Slow
+- bias-disable:			Bool. Pull disabled
+- bias-pull-down:		Bool. Pull down on pin
+- bias-pull-up:			Bool. Pull up on pin
+
+e.g.
Examples:

Got it.

Quoted 7 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 44
Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +4 -0
+#include <dt-bindings/pinctrl/imx7ulp-pinfunc.h>
+
+/* Pin Controller Node */
+iomuxc1: iomuxc1 at 40ac0000 {
The number suffix doesn't make too much sense in node name.

Good suggestion

Quoted 13 lines

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +12 -0

+	compatible = "fsl,imx7ulp-iomuxc1";
+	reg = <0x40ac0000 0x1000>;
+
+	/* Pin Configuration Node */
+	pinctrl_lpuart4: lpuart4grp {
+		pins = <
+			ULP1_PAD_PTC3__LPUART4_RX
+			ULP1_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+};

(quoted diff) +0 -0

Quoted 9 lines

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h
Quoted 5 lines
b/include/dt-bindings/pinctrl/imx7ulp-pinfunc.h
new file mode 100644
index 0000000..b6db73f
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +0 -0
The header will only be used by dts files, right? If so, arch/arm/boot/dts is the better place.

I can do it, but I'm just a bit confused that only IMX is still Putting pinctrl headfile under arch/arm/boot/dts/.

Actually I even planned to cook a patch move them all Into include/dt-bindings/pinctrl.

Quoted 7 lines

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +6 -0

@@ -0,0 +1,468 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+modify

Quoted 9 lines

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 11
Quoted 6 lines
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +6 -0
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_ULP1_PINFUNC_H
s/ULP1/IMX7ULP?

Yes, Will change.

Thanks for the careful review!

Regards
Dong Aisheng

Quoted 914 lines

Shawn
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h
Quoted 7 lines
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +7 -0
+#define __DTS_ULP1_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_conf_reg conf_reg input_reg mux_mode input_val>  */
+
+#define ULP1_PAD_PTC0__PTC0
0x0000 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 20
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC0__TRACE_D15
0x0000 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 21
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC0__LPUART4_CTS_B
0x0000 0x0244 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 22
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC0__LPI2C4_SCL
0x0000 0x0278 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 23
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC0__TPM4_CLKIN
0x0000 0x0298 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 24
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC0__FB_AD0
0x0000 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 25
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC1__PTC1
0x0004 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 26
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC1__TRACE_D14
0x0004 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 27
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC1__LPUART4_RTS_B
0x0004 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 28
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC1__LPI2C4_SDA
0x0004 0x027c 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 29
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC1__TPM4_CH0
0x0004 0x0280 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 30
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC1__FB_AD1
0x0004 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 31
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC2__PTC2
0x0008 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 32
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC2__TRACE_D13
0x0008 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 33
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC2__LPUART4_TX
0x0008 0x024c 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 34
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC2__LPI2C4_HREQ
0x0008 0x0274 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 35
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC2__TPM4_CH1
0x0008 0x0284 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 36
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC2__FB_AD2
0x0008 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 37
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC3__PTC3
0x000c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 38
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC3__TRACE_D12
0x000c 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 39
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC3__LPUART4_RX
0x000c 0x0248 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 40
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC3__TPM4_CH2
0x000c 0x0288 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 41
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC3__FB_AD3
0x000c 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 42
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC4__PTC4
0x0010 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 43
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC4__TRACE_D11
0x0010 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 44
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC4__FXIO1_D0
0x0010 0x0204 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 45
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC4__LPSPI2_PCS1
0x0010 0x02a0 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 46
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC4__LPUART5_CTS_B
0x0010 0x0250 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 47
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC4__LPI2C5_SCL
0x0010 0x02bc 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 48
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC4__TPM4_CH3
0x0010 0x028c 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 49
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC4__FB_AD4
0x0010 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 50
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC5__PTC5
0x0014 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 51
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC5__TRACE_D10
0x0014 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 52
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC5__FXIO1_D1
0x0014 0x0208 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 53
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC5__LPSPI2_PCS2
0x0014 0x02a4 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 54
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC5__LPUART5_RTS_B
0x0014 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 55
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC5__LPI2C5_SDA
0x0014 0x02c0 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 56
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC5__TPM4_CH4
0x0014 0x0290 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 57
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC5__FB_AD5
0x0014 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 58
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC6__PTC6
0x0018 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 59
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC6__TRACE_D9
0x0018 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 60
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC6__FXIO1_D2
0x0018 0x020c 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 61
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC6__LPSPI2_PCS3
0x0018 0x02a8 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 62
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC6__LPUART5_TX
0x0018 0x0258 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 63
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC6__LPI2C5_HREQ
0x0018 0x02b8 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 64
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC6__TPM4_CH5
0x0018 0x0294 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 65
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC6__FB_AD6
0x0018 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 66
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC7__PTC7
0x001c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 67
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC7__TRACE_D8
0x001c 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 68
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC7__FXIO1_D3
0x001c 0x0210 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 69
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC7__LPUART5_RX
0x001c 0x0254 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 70
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC7__TPM5_CH1
0x001c 0x02c8 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 71
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC7__FB_AD7
0x001c 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 72
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC8__PTC8
0x0020 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 73
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC8__TRACE_D7
0x0020 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 74
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC8__FXIO1_D4
0x0020 0x0214 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 75
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC8__LPSPI2_SIN
0x0020 0x02b0 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 76
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC8__LPUART6_CTS_B
0x0020 0x025c 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 77
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC8__LPI2C6_SCL
0x0020 0x02fc 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 78
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC8__TPM5_CLKIN
0x0020 0x02cc 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 79
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC8__FB_AD8
0x0020 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 80
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC9__PTC9
0x0024 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 81
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC9__TRACE_D6
0x0024 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 82
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC9__FXIO1_D5
0x0024 0x0218 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 83
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC9__LPSPI2_SOUT
0x0024 0x02b4 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 84
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC9__LPUART6_RTS_B
0x0024 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 85
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC9__LPI2C6_SDA
0x0024 0x0300 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 86
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC9__TPM5_CH0
0x0024 0x02c4 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 87
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC9__FB_AD9
0x0024 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 88
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC10__PTC10
0x0028 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 89
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC10__TRACE_D5
0x0028 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 90
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC10__FXIO1_D6
0x0028 0x021c 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 91
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC10__LPSPI2_SCK
0x0028 0x02ac 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 92
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC10__LPUART6_TX
0x0028 0x0264 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 93
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC10__LPI2C6_HREQ
0x0028 0x02f8 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 94
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC10__TPM7_CH3
0x0028 0x02e8 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 95
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC10__FB_AD10
0x0028 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 96
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC11__PTC11
0x002c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 97
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC11__TRACE_D4
0x002c 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 98
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC11__FXIO1_D7
0x002c 0x0220 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 99
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC11__LPSPI2_PCS0
0x002c 0x029c 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 100
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC11__LPUART6_RX
0x002c 0x0260 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 101
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC11__TPM7_CH4
0x002c 0x02ec 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 102
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC11__FB_AD11
0x002c 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 103
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC12__PTC12
0x0030 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 104
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC12__TRACE_D3
0x0030 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 105
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC12__FXIO1_D8
0x0030 0x0224 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 106
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC12__LPSPI3_PCS1
0x0030 0x0314 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 107
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC12__LPUART7_CTS_B
0x0030 0x0268 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 108
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC12__LPI2C7_SCL
0x0030 0x0308 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 109
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC12__TPM7_CH5
0x0030 0x02f0 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 110
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC12__FB_AD12
0x0030 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 111
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC13__PTC13
0x0034 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 112
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC13__TRACE_D2
0x0034 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 113
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC13__FXIO1_D9
0x0034 0x0228 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 114
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC13__LPSPI3_PCS2
0x0034 0x0318 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 115
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC13__LPUART7_RTS_B
0x0034 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 116
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC13__LPI2C7_SDA
0x0034 0x030c 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 117
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC13__TPM7_CLKIN
0x0034 0x02f4 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 118
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC13__FB_AD13
0x0034 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 119
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC14__PTC14
0x0038 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 120
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC14__TRACE_D1
0x0038 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 121
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC14__FXIO1_D10
0x0038 0x022c 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 122
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC14__LPSPI3_PCS3
0x0038 0x031c 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 123
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC14__LPUART7_TX
0x0038 0x0270 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 124
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC14__LPI2C7_HREQ
0x0038 0x0304 0x5 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 125
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC14__TPM7_CH0
0x0038 0x02dc 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 126
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC14__FB_AD14
0x0038 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 127
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC15__PTC15
0x003c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 128
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC15__TRACE_D0
0x003c 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 129
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC15__FXIO1_D11
0x003c 0x0230 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 130
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC15__LPUART7_RX
0x003c 0x026c 0x4 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 131
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC15__TPM7_CH1
0x003c 0x02e0 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 132
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC15__FB_AD15
0x003c 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 133
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC16__PTC16
0x0040 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 134
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC16__TRACE_CLKOUT
0x0040 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 135
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC16__FXIO1_D12
0x0040 0x0234 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 136
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC16__LPSPI3_SIN
0x0040 0x0324 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 137
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC16__TPM7_CH2
0x0040 0x02e4 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 138
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B
0x0040 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 139
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC17__PTC17
0x0044 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 140
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC17__FXIO1_D13
0x0044 0x0238 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 141
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC17__LPSPI3_SOUT
0x0044 0x0328 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 142
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC17__TPM6_CLKIN
0x0044 0x02d8 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 143
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC17__FB_CS0_B
0x0044 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 144
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC18__PTC18
0x0048 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 145
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC18__FXIO1_D14
0x0048 0x023c 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 146
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC18__LPSPI3_SCK
0x0048 0x0320 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 147
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC18__TPM6_CH0
0x0048 0x02d0 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 148
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC18__FB_OE_B
0x0048 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 149
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC19__PTC19
0x004c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 150
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC19__FXIO1_D15
0x004c 0x0240 0x2 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 151
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC19__LPSPI3_PCS0
0x004c 0x0310 0x3 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 152
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC19__TPM6_CH1
0x004c 0x02d4 0x6 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 153
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC19__FB_A16
0x004c 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 154
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD0__PTD0
0x0080 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 155
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD0__SDHC0_RESET_B
0x0080 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 156
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD1__PTD1
0x0084 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 157
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD1__SDHC0_CMD
0x0084 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 158
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD2__PTD2
0x0088 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 159
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD2__SDHC0_CLK
0x0088 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 160
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD3__PTD3
0x008c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 161
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD3__SDHC0_D7
0x008c 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 162
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD4__PTD4
0x0090 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 163
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD4__SDHC0_D6
0x0090 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 164
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD5__PTD5
0x0094 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 165
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD5__SDHC0_D5
0x0094 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 166
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD6__PTD6
0x0098 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 167
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD6__SDHC0_D4
0x0098 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 168
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD7__PTD7
0x009c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 169
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD7__SDHC0_D3
0x009c 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 170
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD8__PTD8
0x00a0 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 171
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD8__TPM4_CLKIN
0x00a0 0x0298 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 172
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD8__SDHC0_D2
0x00a0 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 173
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD9__PTD9
0x00a4 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 174
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD9__TPM4_CH0
0x00a4 0x0280 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 175
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD9__SDHC0_D1
0x00a4 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 176
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD10__PTD10
0x00a8 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 177
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD10__TPM4_CH1
0x00a8 0x0284 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 178
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD10__SDHC0_D0
0x00a8 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 179
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD11__PTD11
0x00ac 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 180
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD11__TPM4_CH2
0x00ac 0x0288 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 181
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTD11__SDHC0_DQS
0x00ac 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 182
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE0__PTE0
0x0100 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 183
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE0__FXIO1_D31
0x0100 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 184
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE0__LPSPI2_PCS1
0x0100 0x02a0 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 185
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE0__LPUART4_CTS_B
0x0100 0x0244 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 186
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE0__LPI2C4_SCL
0x0100 0x0278 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 187
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE0__SDHC1_D1
0x0100 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 188
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE0__FB_A25
0x0100 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 189
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE1__PTE1
0x0104 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 190
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE1__FXIO1_D30
0x0104 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 191
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE1__LPSPI2_PCS2
0x0104 0x02a4 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 192
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE1__LPUART4_RTS_B
0x0104 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 193
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE1__LPI2C4_SDA
0x0104 0x027c 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 194
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE1__SDHC1_D0
0x0104 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 195
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE1__FB_A26
0x0104 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 196
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE2__PTE2
0x0108 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 197
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE2__FXIO1_D29
0x0108 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 198
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE2__LPSPI2_PCS3
0x0108 0x02a8 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 199
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE2__LPUART4_TX
0x0108 0x024c 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 200
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE2__LPI2C4_HREQ
0x0108 0x0274 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 201
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE2__SDHC1_CLK
0x0108 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 202
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE3__PTE3
0x010c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 203
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE3__FXIO1_D28
0x010c 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 204
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE3__LPUART4_RX
0x010c 0x0248 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 205
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE3__TPM5_CH1
0x010c 0x02c8 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 206
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE3__SDHC1_CMD
0x010c 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 207
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE4__PTE4
0x0110 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 208
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE4__FXIO1_D27
0x0110 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 209
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE4__LPSPI2_SIN
0x0110 0x02b0 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 210
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE4__LPUART5_CTS_B
0x0110 0x0250 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 211
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE4__LPI2C5_SCL
0x0110 0x02bc 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 212
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE4__TPM5_CLKIN
0x0110 0x02cc 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 213
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE4__SDHC1_D3
0x0110 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 214
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE5__PTE5
0x0114 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 215
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE5__FXIO1_D26
0x0114 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 216
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE5__LPSPI2_SOUT
0x0114 0x02b4 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 217
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE5__LPUART5_RTS_B
0x0114 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 218
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE5__LPI2C5_SDA
0x0114 0x02c0 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 219
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE5__TPM5_CH0
0x0114 0x02c4 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 220
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE5__SDHC1_D2
0x0114 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 221
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE6__PTE6
0x0118 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 222
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE6__FXIO1_D25
0x0118 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 223
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE6__LPSPI2_SCK
0x0118 0x02ac 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 224
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE6__LPUART5_TX
0x0118 0x0258 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 225
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE6__LPI2C5_HREQ
0x0118 0x02b8 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 226
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE6__TPM7_CH3
0x0118 0x02e8 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 227
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE6__SDHC1_D4
0x0118 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 228
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE6__FB_A17
0x0118 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 229
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE7__PTE7
0x011c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 230
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE7__TRACE_D7
0x011c 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 231
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE7__VIU_FID
0x011c 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 232
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE7__FXIO1_D24
0x011c 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 233
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE7__LPSPI2_PCS0
0x011c 0x029c 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 234
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE7__LPUART5_RX
0x011c 0x0254 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 235
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE7__TPM7_CH4
0x011c 0x02ec 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 236
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE7__SDHC1_D5
0x011c 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 237
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE7__FB_A18
0x011c 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 238
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__PTE8
0x0120 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 239
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__TRACE_D6
0x0120 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 240
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__VIU_D16
0x0120 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 241
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__FXIO1_D23
0x0120 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 242
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__LPSPI3_PCS1
0x0120 0x0314 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 243
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__LPUART6_CTS_B
0x0120 0x025c 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 244
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__LPI2C6_SCL
0x0120 0x02fc 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 245
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__TPM7_CH5
0x0120 0x02f0 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 246
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__SDHC1_WP
0x0120 0x0200 0x7 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 247
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__SDHC1_D6
0x0120 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 248
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B
0x0120 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 249
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__PTE9
0x0124 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 250
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__TRACE_D5
0x0124 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 251
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__VIU_D17
0x0124 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 252
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__FXIO1_D22
0x0124 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 253
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__LPSPI3_PCS2
0x0124 0x0318 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 254
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__LPUART6_RTS_B
0x0124 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 255
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__LPI2C6_SDA
0x0124 0x0300 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 256
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__TPM7_CLKIN
0x0124 0x02f4 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 257
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__SDHC1_CD
0x0124 0x032c 0x7 0x1
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 258
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__SDHC1_D7
0x0124 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 259
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B
0x0124 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 260
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__PTE10
0x0128 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 261
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__TRACE_D4
0x0128 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 262
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__VIU_D18
0x0128 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 263
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__FXIO1_D21
0x0128 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 264
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__LPSPI3_PCS3
0x0128 0x031c 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 265
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__LPUART6_TX
0x0128 0x0264 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 266
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__LPI2C6_HREQ
0x0128 0x02f8 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 267
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__TPM7_CH0
0x0128 0x02dc 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 268
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__SDHC1_VS
0x0128 0x0000 0x7 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 269
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__SDHC1_DQS
0x0128 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 270
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE10__FB_A19
0x0128 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 271
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE11__PTE11
0x012c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 272
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE11__TRACE_D3
0x012c 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 273
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE11__VIU_D19
0x012c 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 274
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE11__FXIO1_D20
0x012c 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 275
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE11__LPUART6_RX
0x012c 0x0260 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 276
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE11__TPM7_CH1
0x012c 0x02e0 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 277
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE11__SDHC1_RESET_B
0x012c 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 278
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE11__FB_A20
0x012c 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 279
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE12__PTE12
0x0130 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 280
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE12__TRACE_D2
0x0130 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 281
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE12__VIU_D20
0x0130 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 282
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE12__FXIO1_D19
0x0130 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 283
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE12__LPSPI3_SIN
0x0130 0x0324 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 284
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE12__LPUART7_CTS_B
0x0130 0x0268 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 285
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE12__LPI2C7_SCL
0x0130 0x0308 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 286
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE12__TPM7_CH2
0x0130 0x02e4 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 287
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE12__SDHC1_WP
0x0130 0x0200 0x8 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 288
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE12__FB_A21
0x0130 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 289
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE13__PTE13
0x0134 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 290
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE13__TRACE_D1
0x0134 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 291
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE13__VIU_D21
0x0134 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 292
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE13__FXIO1_D18
0x0134 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 293
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE13__LPSPI3_SOUT
0x0134 0x0328 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 294
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE13__LPUART7_RTS_B
0x0134 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 295
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE13__LPI2C7_SDA
0x0134 0x030c 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 296
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE13__TPM6_CLKIN
0x0134 0x02d8 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 297
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE13__SDHC1_CD
0x0134 0x032c 0x8 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 298
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE13__FB_A22
0x0134 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 299
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE14__PTE14
0x0138 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 300
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE14__TRACE_D0
0x0138 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 301
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE14__VIU_D22
0x0138 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 302
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE14__FXIO1_D17
0x0138 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 303
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE14__LPSPI3_SCK
0x0138 0x0320 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 304
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE14__LPUART7_TX
0x0138 0x0270 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 305
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE14__LPI2C7_HREQ
0x0138 0x0304 0x5 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 306
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE14__TPM6_CH0
0x0138 0x02d0 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 307
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE14__SDHC1_VS
0x0138 0x0000 0x8 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 308
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE14__FB_A23
0x0138 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 309
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE15__PTE15
0x013c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 310
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE15__TRACE_CLKOUT
0x013c 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 311
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE15__VIU_D23
0x013c 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 312
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE15__FXIO1_D16
0x013c 0x0000 0x2 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 313
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE15__LPSPI3_PCS0
0x013c 0x0310 0x3 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 314
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE15__LPUART7_RX
0x013c 0x026c 0x4 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 315
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE15__TPM6_CH1
0x013c 0x02d4 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 316
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTE15__FB_A24
0x013c 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 317
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF0__PTF0
0x0180 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 318
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF0__VIU_DE
0x0180 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 319
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF0__LPUART4_CTS_B
0x0180 0x0244 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 320
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF0__LPI2C4_SCL
0x0180 0x0278 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 321
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF0__TPM4_CLKIN
0x0180 0x0298 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 322
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF0__FB_RW_B
0x0180 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 323
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF1__PTF1
0x0184 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 324
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF1__VIU_HSYNC
0x0184 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 325
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF1__LPUART4_RTS_B
0x0184 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 326
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF1__LPI2C4_SDA
0x0184 0x027c 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 327
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF1__TPM4_CH0
0x0184 0x0280 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 328
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF1__CLKOUT
0x0184 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 329
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF2__PTF2
0x0188 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 330
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF2__VIU_VSYNC
0x0188 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 331
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF2__LPUART4_TX
0x0188 0x024c 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 332
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF2__LPI2C4_HREQ
0x0188 0x0274 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 333
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF2__TPM4_CH1
0x0188 0x0284 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 334
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B
0x0188 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 335
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF3__PTF3
0x018c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 336
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF3__VIU_PCLK
0x018c 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 337
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF3__LPUART4_RX
0x018c 0x0248 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 338
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF3__TPM4_CH2
0x018c 0x0288 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 339
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF3__FB_AD16
0x018c 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 340
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF4__PTF4
0x0190 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 341
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF4__VIU_D0
0x0190 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 342
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF4__FXIO1_D0
0x0190 0x0204 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 343
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF4__LPSPI2_PCS1
0x0190 0x02a0 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 344
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF4__LPUART5_CTS_B
0x0190 0x0250 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 345
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF4__LPI2C5_SCL
0x0190 0x02bc 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 346
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF4__TPM4_CH3
0x0190 0x028c 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 347
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF4__FB_AD17
0x0190 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 348
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF5__PTF5
0x0194 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 349
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF5__VIU_D1
0x0194 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 350
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF5__FXIO1_D1
0x0194 0x0208 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 351
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF5__LPSPI2_PCS2
0x0194 0x02a4 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 352
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF5__LPUART5_RTS_B
0x0194 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 353
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF5__LPI2C5_SDA
0x0194 0x02c0 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 354
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF5__TPM4_CH4
0x0194 0x0290 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 355
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF5__FB_AD18
0x0194 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 356
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF6__PTF6
0x0198 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 357
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF6__VIU_D2
0x0198 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 358
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF6__FXIO1_D2
0x0198 0x020c 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 359
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF6__LPSPI2_PCS3
0x0198 0x02a8 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 360
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF6__LPUART5_TX
0x0198 0x0258 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 361
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF6__LPI2C5_HREQ
0x0198 0x02b8 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 362
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF6__TPM4_CH5
0x0198 0x0294 0x6 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 363
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF6__FB_AD19
0x0198 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 364
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF7__PTF7
0x019c 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 365
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF7__VIU_D3
0x019c 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 366
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF7__FXIO1_D3
0x019c 0x0210 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 367
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF7__LPUART5_RX
0x019c 0x0254 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 368
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF7__TPM5_CH1
0x019c 0x02c8 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 369
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF7__FB_AD20
0x019c 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 370
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF8__PTF8
0x01a0 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 371
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF8__USB1_ULPI_CLK
0x01a0 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 372
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF8__VIU_D4
0x01a0 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 373
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF8__FXIO1_D4
0x01a0 0x0214 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 374
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF8__LPSPI2_SIN
0x01a0 0x02b0 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 375
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF8__LPUART6_CTS_B
0x01a0 0x025c 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 376
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF8__LPI2C6_SCL
0x01a0 0x02fc 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 377
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF8__TPM5_CLKIN
0x01a0 0x02cc 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 378
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF8__FB_AD21
0x01a0 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 379
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF9__PTF9
0x01a4 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 380
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF9__USB1_ULPI_NXT
0x01a4 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 381
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF9__VIU_D5
0x01a4 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 382
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF9__FXIO1_D5
0x01a4 0x0218 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 383
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF9__LPSPI2_SOUT
0x01a4 0x02b4 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 384
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF9__LPUART6_RTS_B
0x01a4 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 385
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF9__LPI2C6_SDA
0x01a4 0x0300 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 386
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF9__TPM5_CH0
0x01a4 0x02c4 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 387
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF9__FB_AD22
0x01a4 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 388
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF10__PTF10
0x01a8 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 389
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF10__USB1_ULPI_STP
0x01a8 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 390
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF10__VIU_D6
0x01a8 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 391
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF10__FXIO1_D6
0x01a8 0x021c 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 392
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF10__LPSPI2_SCK
0x01a8 0x02ac 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 393
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF10__LPUART6_TX
0x01a8 0x0264 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 394
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF10__LPI2C6_HREQ
0x01a8 0x02f8 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 395
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF10__TPM7_CH3
0x01a8 0x02e8 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 396
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF10__FB_AD23
0x01a8 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 397
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF11__PTF11
0x01ac 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 398
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF11__USB1_ULPI_DIR
0x01ac 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 399
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF11__VIU_D7
0x01ac 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 400
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF11__FXIO1_D7
0x01ac 0x0220 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 401
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF11__LPSPI2_PCS0
0x01ac 0x029c 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 402
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF11__LPUART6_RX
0x01ac 0x0260 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 403
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF11__TPM7_CH4
0x01ac 0x02ec 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 404
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B
0x01ac 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 405
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF12__PTF12
0x01b0 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 406
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF12__USB1_ULPI_DATA0
0x01b0 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 407
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF12__VIU_D8
0x01b0 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 408
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF12__FXIO1_D8
0x01b0 0x0224 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 409
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF12__LPSPI3_PCS1
0x01b0 0x0314 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 410
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF12__LPUART7_CTS_B
0x01b0 0x0268 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 411
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF12__LPI2C7_SCL
0x01b0 0x0308 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 412
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF12__TPM7_CH5
0x01b0 0x02f0 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 413
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF12__FB_AD24
0x01b0 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 414
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF13__PTF13
0x01b4 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 415
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF13__USB1_ULPI_DATA1
0x01b4 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 416
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF13__VIU_D9
0x01b4 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 417
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF13__FXIO1_D9
0x01b4 0x0228 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 418
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF13__LPSPI3_PCS2
0x01b4 0x0318 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 419
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF13__LPUART7_RTS_B
0x01b4 0x0000 0x4 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 420
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF13__LPI2C7_SDA
0x01b4 0x030c 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 421
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF13__TPM7_CLKIN
0x01b4 0x02f4 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 422
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF13__FB_AD25
0x01b4 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 423
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF14__PTF14
0x01b8 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 424
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF14__USB1_ULPI_DATA2
0x01b8 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 425
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF14__VIU_D10
0x01b8 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 426
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF14__FXIO1_D10
0x01b8 0x022c 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 427
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF14__LPSPI3_PCS3
0x01b8 0x031c 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 428
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF14__LPUART7_TX
0x01b8 0x0270 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 429
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF14__LPI2C7_HREQ
0x01b8 0x0304 0x5 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 430
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF14__TPM7_CH0
0x01b8 0x02dc 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 431
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF14__FB_AD26
0x01b8 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 432
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF15__PTF15
0x01bc 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 433
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF15__USB1_ULPI_DATA3
0x01bc 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 434
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF15__VIU_D11
0x01bc 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 435
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF15__FXIO1_D11
0x01bc 0x0230 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 436
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF15__LPUART7_RX
0x01bc 0x026c 0x4 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 437
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF15__TPM7_CH1
0x01bc 0x02e0 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 438
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF15__FB_AD27
0x01bc 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 439
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF16__PTF16
0x01c0 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 440
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF16__USB1_ULPI_DATA4
0x01c0 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 441
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF16__VIU_D12
0x01c0 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 442
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF16__FXIO1_D12
0x01c0 0x0234 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 443
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF16__LPSPI3_SIN
0x01c0 0x0324 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 444
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF16__TPM7_CH2
0x01c0 0x02e4 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 445
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF16__FB_AD28
0x01c0 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 446
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF17__PTF17
0x01c4 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 447
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF17__USB1_ULPI_DATA5
0x01c4 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 448
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF17__VIU_D13
0x01c4 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 449
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF17__FXIO1_D13
0x01c4 0x0238 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 450
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF17__LPSPI3_SOUT
0x01c4 0x0328 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 451
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF17__TPM6_CLKIN
0x01c4 0x02d8 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 452
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF17__FB_AD29
0x01c4 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 453
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF18__PTF18
0x01c8 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 454
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF18__USB1_ULPI_DATA6
0x01c8 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 455
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF18__VIU_D14
0x01c8 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 456
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF18__FXIO1_D14
0x01c8 0x023c 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 457
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF18__LPSPI3_SCK
0x01c8 0x0320 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 458
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF18__TPM6_CH0
0x01c8 0x02d0 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 459
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF18__FB_AD30
0x01c8 0x0000 0x9 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 460
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF19__PTF19
0x01cc 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 461
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF19__USB1_ULPI_DATA7
0x01cc 0x0000 0xb 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 462
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF19__VIU_D15
0x01cc 0x0000 0xc 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 463
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF19__FXIO1_D15
0x01cc 0x0240 0x2 0x2
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 464
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF19__LPSPI3_PCS0
0x01cc 0x0310 0x3 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 465
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF19__TPM6_CH1
0x01cc 0x02d4 0x6 0x3
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 466
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTF19__FB_AD31
0x01cc 0x0000 0x9 0x0
Quoted 10 lines
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +2 -1
+
+#endif /* __DTS_ULP1_PINFUNC_H */
--
2.7.4
_______________________________________________
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linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Shawn Guo

2017-05-15 12:20 UTC #18 lore raw

PATCH 3/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 12 lines · A.S. Dong

Quoted 11 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 4
Quoted 5 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +4 -0
@@ -0,0 +1,56 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common
+binding part and usage.
Are imx7ulp-pinctrl bindings more alike to fsl,imx-pinctrl.txt or generic pinctrl-bindings.txt? My personal feeling is that it might be better to take pinctrl-bindings.txt as the reference base and highlight how imx7ulp- pinctrl bindings differ from it.

Quoted 7 lines

It seems still more like fsl,imx-pinctrl.txt.
I know fsl,imx-pinctrl.txt is a bit out of date, especially after we add generic pinconf.
I plan to update it later after adding generic pin conf support to legacy SoCs (MX6 & 7) as well, do you think it's ok?

Please do not. Let's use generic pinconf support only for new SoCs, and not bother with legacy SoCs.

<snip>

Quoted 11 lines

Quoted 10 lines
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h
Quoted 6 lines
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +0 -0
new file mode 100644
index 0000000..b6db73f
The header will only be used by dts files, right? If so, arch/arm/boot/dts is the better place.

Quoted 2 lines

I can do it, but I'm just a bit confused that only IMX is still Putting pinctrl headfile under arch/arm/boot/dts/.

It makes sense to define DT constants in include/dt-bindings/pinctrl/ only when they are referenced by both kernel and dts. If it's only included by dts, arch/arm/boot/dts/ should definitely be the better place.

Shawn

A.S. Dong

author maintainer

2017-05-15 12:41 UTC #19 lore raw

PATCH 3/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 25 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 8:21 PM
To: A.S. Dong
Cc: Mark Rutland; devicetree at vger.kernel.org; Andy Duan; Jacky Bai; linus.walleij at linaro.org; stefan at agner.ch; linux-gpio at vger.kernel.org; Rob Herring; kernel at pengutronix.de; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 3/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc
Quoted 14 lines · A.S. Dong
Quoted 11 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 4
Quoted 5 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +4 -0
@@ -0,0 +1,56 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common
+binding part and usage.
Are imx7ulp-pinctrl bindings more alike to fsl,imx-pinctrl.txt or generic pinctrl-bindings.txt? My personal feeling is that it might be better to take pinctrl-bindings.txt as the reference base and highlight how imx7ulp- pinctrl bindings differ from it.
It seems still more like fsl,imx-pinctrl.txt.

Quoted 9 lines

Quoted 5 lines
I know fsl,imx-pinctrl.txt is a bit out of date, especially after we add generic pinconf.
I plan to update it later after adding generic pin conf support to legacy SoCs (MX6 & 7) as well, do you think it's ok?
Please do not. Let's use generic pinconf support only for new SoCs, and not bother with legacy SoCs.

I wonder there may be some guys interested more in generic Pinconfig format rather than old one when they add new board support, or someone else adding the support for legacy SoCs as the pinctrl-imx core already supports it after this patch series.

So I'm not quite sure if there's strong reason to block to them to do it.

Quoted 13 lines

<snip>
Quoted 11 lines
Quoted 10 lines
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h
Quoted 6 lines
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +0 -0
new file mode 100644
index 0000000..b6db73f
The header will only be used by dts files, right? If so, arch/arm/boot/dts is the better place.

Quoted 7 lines

Quoted 2 lines
I can do it, but I'm just a bit confused that only IMX is still Putting pinctrl headfile under arch/arm/boot/dts/.
It makes sense to define DT constants in include/dt-bindings/pinctrl/ only when they are referenced by both kernel and dts. If it's only included by dts, arch/arm/boot/dts/ should definitely be the better place.

Okay, understand.
In the future, I probably may added a pinctrl headfile for config macro defines. But since that is for config only, probably may need create a new file. e.g.
include/dt-binding/pinctrl/imx7ulp.h
or
include/dt-binding/pinctrl/imx.h (if we supports legacy SoCs)

So we could still keep imx7ulp-pinfunc.h in arch/arm/boot/dts.

Regards
Dong Aisheng

Quoted 1 line

Shawn

Shawn Guo

2017-05-15 12:59 UTC #20 lore raw

PATCH 3/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 21 lines · A.S. Dong

Quoted 21 lines · A.S. Dong
Quoted 19 lines
Quoted 11 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 4
Quoted 5 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +4 -0
@@ -0,0 +1,56 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common
+binding part and usage.
Are imx7ulp-pinctrl bindings more alike to fsl,imx-pinctrl.txt or generic pinctrl-bindings.txt? My personal feeling is that it might be better to take pinctrl-bindings.txt as the reference base and highlight how imx7ulp- pinctrl bindings differ from it.
It seems still more like fsl,imx-pinctrl.txt.
I know fsl,imx-pinctrl.txt is a bit out of date, especially after we add generic pinconf.
I plan to update it later after adding generic pin conf support to legacy SoCs (MX6 & 7) as well, do you think it's ok?

Quoted 8 lines

Quoted 3 lines
Please do not. Let's use generic pinconf support only for new SoCs, and not bother with legacy SoCs.
I wonder there may be some guys interested more in generic Pinconfig format rather than old one when they add new board support, or someone else adding the support for legacy SoCs as the pinctrl-imx core already supports it after this patch series.

I would take this as an unnecessary churn on existing code and increase of maintenance burden. So that's definitely a NO from me.

Shawn

A.S. Dong

author maintainer

2017-05-15 13:12 UTC #21 lore raw

PATCH 3/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 36 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 8:59 PM
To: A.S. Dong
Cc: Mark Rutland; devicetree at vger.kernel.org; Andy Duan; Jacky Bai; linus.walleij at linaro.org; stefan at agner.ch; linux-gpio at vger.kernel.org; Rob Herring; kernel at pengutronix.de; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 3/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc
Quoted 25 lines · A.S. Dong
Quoted 24 lines · A.S. Dong
Quoted 12 lines
Quoted 11 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 4
Quoted 5 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +4 -0
@@ -0,0 +1,56 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for
+common binding part and usage.
Are imx7ulp-pinctrl bindings more alike to fsl,imx-pinctrl.txt or generic pinctrl-bindings.txt? My personal feeling is that it might be better to take pinctrl-bindings.txt as the reference base and highlight how imx7ulp- pinctrl bindings differ from it.
Quoted 7 lines
It seems still more like fsl,imx-pinctrl.txt.
I know fsl,imx-pinctrl.txt is a bit out of date, especially after we add generic pinconf.
I plan to update it later after adding generic pin conf support to legacy SoCs (MX6 & 7) as well, do you think it's ok?
Please do not. Let's use generic pinconf support only for new SoCs, and not bother with legacy SoCs.

Quoted 8 lines

Quoted 4 lines
I wonder there may be some guys interested more in generic Pinconfig format rather than old one when they add new board support, or someone else adding the support for legacy SoCs as the pinctrl-imx core already supports it after this patch series.
I would take this as an unnecessary churn on existing code and increase of maintenance burden. So that's definitely a NO from me.

Okay, personally I would be with you!

Regards
Dong Aisheng

Shawn Guo

2017-05-15 13:31 UTC #22 lore raw

PATCH 3/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

In reply to Dong Aisheng

Quoted 12 lines · Dong Aisheng

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +6 -0

new file mode 100644
index 0000000..b6db73f
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 16

Quoted 10 lines

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +10 -0

+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_ULP1_PINFUNC_H
+#define __DTS_ULP1_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_conf_reg conf_reg input_reg mux_mode input_val>

Forgot this one: it should have only 4 integers.

Shawn

Quoted 5 lines

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +5 -0

+ */
+
+#define ULP1_PAD_PTC0__PTC0                                       0x0000 0x0000 0x1 0x0
+#define ULP1_PAD_PTC0__TRACE_D15                                  0x0000 0x0000 0xa 0x0
+#define ULP1_PAD_PTC0__LPUART4_CTS_B                              0x0000 0x0244 0x4 0x1

A.S. Dong

author maintainer

2017-05-15 13:32 UTC #23 lore raw

PATCH 3/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 28 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 9:31 PM
To: A.S. Dong
Cc: linux-gpio at vger.kernel.org; Mark Rutland; Andy Duan; Jacky Bai; devicetree at vger.kernel.org; linus.walleij at linaro.org; stefan at agner.ch; Rob Herring; kernel at pengutronix.de; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 3/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc
include/dt-
Quoted 1 line · Dong Aisheng
include/dt- renamed from include/dt-bindings/pinctrl/imx7ulp-pinfunc.h +0 -0
bindings/pinctrl/imx7ulp-pinfunc.h
Quoted 15 lines
new file mode 100644
index 0000000..b6db73f
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +10 -0
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+

Quoted 9 lines

include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 16
Quoted 6 lines
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +6 -0
+#ifndef __DTS_ULP1_PINFUNC_H
+#define __DTS_ULP1_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_conf_reg conf_reg input_reg mux_mode input_val>
Forgot this one: it should have only 4 integers.

Good catch!
Thanks a lot

Regards
Dong Aisheng

Quoted 10 lines

Shawn
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h
Quoted 3 lines
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +3 -0
+ */
+
+#define ULP1_PAD_PTC0__PTC0
0x0000 0x0000 0x1 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 20
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC0__TRACE_D15
0x0000 0x0000 0xa 0x0
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h line 21
Quoted 1 line
include/dt-bindings/pinctrl/imx7ulp-pinfunc.h new file +1 -0
+#define ULP1_PAD_PTC0__LPUART4_CTS_B
0x0000 0x0244 0x4 0x1

Dong Aisheng

author maintainer

2017-05-12 12:38 UTC #24 lore raw

PATCH 4/5 pinctrl: imx: add imx7ulp driver

In reply to Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.
It only supports generic pin config.

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Bai Ping <[email protected]>

Signed-off-by Fugang Duan <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 drivers/pinctrl/freescale/Kconfig           |   7 +
 drivers/pinctrl/freescale/Makefile          |   1 +
 drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 358 ++++++++++++++++++++++++++++
 3 files changed, 366 insertions(+)
 create mode 100644 drivers/pinctrl/freescale/pinctrl-imx7ulp.c

drivers/pinctrl/freescale/Kconfig +7 -0

index 0b266b2..4dbc576 100644
@@ -103,6 +103,13 @@ config PINCTRL_IMX7D
 	help
 	  Say Y here to enable the imx7d pinctrl driver
 
+config PINCTRL_IMX7ULP
+	bool "IMX7ULP pinctrl driver"
+	depends on SOC_IMX7ULP
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the imx7ulp pinctrl driver
+
 config PINCTRL_VF610
 	bool "Freescale Vybrid VF610 pinctrl driver"
 	depends on SOC_VF610

drivers/pinctrl/freescale/Makefile +1 -0

index d44c9e2..525a5ff 100644
@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_IMX6SL)	+= pinctrl-imx6sl.o
 obj-$(CONFIG_PINCTRL_IMX6SX)	+= pinctrl-imx6sx.o
 obj-$(CONFIG_PINCTRL_IMX6UL)	+= pinctrl-imx6ul.o
 obj-$(CONFIG_PINCTRL_IMX7D)	+= pinctrl-imx7d.o
+obj-$(CONFIG_PINCTRL_IMX7ULP)	+= pinctrl-imx7ulp.o
 obj-$(CONFIG_PINCTRL_VF610)	+= pinctrl-vf610.o
 obj-$(CONFIG_PINCTRL_MXS)	+= pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_IMX23)	+= pinctrl-imx23.o

drivers/pinctrl/freescale/pinctrl-imx7ulp.c new file +358 -0

358 lines not on this page · raw message

Signature · 1 line

2.7.4

Dong Aisheng

author maintainer

2017-05-12 12:38 UTC #25 lore raw

PATCH 5/5 pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case

In reply to Dong Aisheng

The original implemented debug message does not work for SHARE_MUX_CONF_REG case. This patch fixes it.

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Fixes bf5a530971af ("pinctrl: imx: add VF610 support to imx pinctrl framework")

Signed-off-by Dong Aisheng <[email protected]>

---
 drivers/pinctrl/freescale/pinctrl-imx.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +8 -4

index 8347197..57e1f7a 100644
@@ -200,11 +200,13 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 			reg &= ~info->mux_mask;
 			reg |= (pin->mux_mode << info->mux_shift);
 			writel(reg, ipctl->base + pin_reg->mux_reg);
+			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+				pin_reg->mux_reg, reg);
 		} else {
 			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
+			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+				pin_reg->mux_reg, pin->mux_mode);
 		}
-		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
-			pin_reg->mux_reg, pin->mux_mode);
 
 		/*
 		 * If the select input value begins with 0xff, it's a quirky

@@ -462,11 +464,13 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 			reg &= info->mux_mask;
 			reg |= configs[i];
 			writel(reg, ipctl->base + pin_reg->conf_reg);
+			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+				pin_reg->conf_reg, reg);
 		} else {
 			writel(configs[i], ipctl->base + pin_reg->conf_reg);
+			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
+				pin_reg->conf_reg, configs[i]);
 		}
-		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
-			pin_reg->conf_reg, configs[i]);
 	} /* for each config */
 
 	return 0;

Signature · 1 line

2.7.4

Shawn Guo

2017-05-15 12:05 UTC #26 lore raw

PATCH 5/5 pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case

Quoted 7 lines · Dong Aisheng

The original implemented debug message does not work for SHARE_MUX_CONF_REG case. This patch fixes it.
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Fixes bf5a530971af ("pinctrl: imx: add VF610 support to imx pinctrl framework")
Signed-off-by Dong Aisheng <[email protected]>

Fixes should go first in a patch series.

Shawn

A.S. Dong

author maintainer

2017-05-15 12:08 UTC #27 lore raw

PATCH 5/5 pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case

Quoted 14 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, May 15, 2017 8:06 PM
To: A.S. Dong
Cc: linux-gpio at vger.kernel.org; Andy Duan; Jacky Bai; linus.walleij at linaro.org; stefan at agner.ch; kernel at pengutronix.de; linux- arm-kernel at lists.infradead.org
Subject: Re: [PATCH 5/5] pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case
Quoted 3 lines · Dong Aisheng
The original implemented debug message does not work for SHARE_MUX_CONF_REG case. This patch fixes it.

Quoted 8 lines

Quoted 5 lines
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Fixes bf5a530971af ("pinctrl: imx: add VF610 support to imx pinctrl
framework")
Signed-off-by Dong Aisheng <[email protected]>
Fixes should go first in a patch series.

That's true.
Thanks for the suggestion.

Regards
Dong Aisheng

Quoted 1 line

Shawn