dm: tegra: Move nyan-big to livetree

index e9a90b1b9b..b5afd72227 100644
@@ -77,6 +77,7 @@ static int vidconsole_back(struct udevice *dev)
 		if (priv->ycur < 0)
 			priv->ycur = 0;
 	}
+	video_sync(dev->parent);
 
 	return 0;
 }

index 3697f4905c..359f8fa186 100644
@@ -28,11 +28,13 @@ struct pwm_backlight_priv {
 static int pwm_backlight_enable(struct udevice *dev)
 {
 	struct pwm_backlight_priv *priv = dev_get_priv(dev);
+	struct dm_regulator_uclass_platdata *plat;
 	uint duty_cycle;
 	int ret;
 
-	debug("%s: Enable '%s', regulator '%s'\n", __func__, dev->name,
-	      priv->reg->name);
+	plat = dev_get_uclass_platdata(priv->reg);
+	debug("%s: Enable '%s', regulator '%s'/'%s'\n", __func__, dev->name,
+	      priv->reg->name, plat->name);
 	ret = regulator_set_enable(priv->reg, true);
 	if (ret) {
 		debug("%s: Cannot enable regulator for PWM '%s'\n", __func__,

@@ -59,12 +61,11 @@ static int pwm_backlight_enable(struct udevice *dev)
 static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
 {
 	struct pwm_backlight_priv *priv = dev_get_priv(dev);
-	struct fdtdec_phandle_args args;
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(dev);
+	struct ofnode_phandle_args args;
 	int index, ret, count, len;
 	const u32 *cell;
 
+	debug("%s: start\n", __func__);
 	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
 					   "power-supply", &priv->reg);
 	if (ret) {

@@ -79,14 +80,15 @@ static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
 		if (ret != -ENOENT)
 			return ret;
 	}
-	ret = fdtdec_parse_phandle_with_args(blob, node, "pwms", "#pwm-cells",
-					     0, 0, &args);
+	ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0,
+					  &args);
 	if (ret) {
 		debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
 		return ret;
 	}
 
-	ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
+	ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node,
+					  &priv->pwm);
 	if (ret) {
 		debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
 		return ret;

@@ -94,8 +96,8 @@ static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
 	priv->channel = args.args[0];
 	priv->period_ns = args.args[1];
 
-	index = fdtdec_get_int(blob, node, "default-brightness-level", 255);
-	cell = fdt_getprop(blob, node, "brightness-levels", &len);
+	index = dev_read_u32_default(dev, "default-brightness-level", 255);
+	cell = dev_read_prop(dev, "brightness-levels", &len);
 	count = len / sizeof(u32);
 	if (cell && count > index) {
 		priv->default_level = fdt32_to_cpu(cell[index]);

@@ -104,6 +106,7 @@ static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
 		priv->default_level = index;
 		priv->max_level = 255;
 	}
+	debug("%s: done\n", __func__);
 
 
 	return 0;

index baa95f6a12..c0ce199c6a 100644
@@ -25,8 +25,10 @@ static int simple_panel_enable_backlight(struct udevice *dev)
 	struct simple_panel_priv *priv = dev_get_priv(dev);
 	int ret;
 
+	debug("%s: start, backlight = '%s'\n", __func__, priv->backlight->name);
 	dm_gpio_set_value(&priv->enable, 1);
 	ret = backlight_enable(priv->backlight);
+	debug("%s: done, ret = %d\n", __func__, ret);
 	if (ret)
 		return ret;
 

index 84f1ee5035..943ee24e59 100644
@@ -9,14 +9,8 @@
 #include <dm.h>
 #include <errno.h>
 #include <ns16550.h>
-#include <linux/compiler.h>
-#include <linux/sizes.h>
+#include <usb.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/pmu.h>
-#include <asm/arch/tegra.h>
 #include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/clk_rst.h>

@@ -25,17 +19,17 @@
 #include <asm/arch-tegra/uart.h>
 #include <asm/arch-tegra/warmboot.h>
 #include <asm/arch-tegra/gpu.h>
+#include <asm/arch-tegra/usb.h>
+#include <asm/arch-tegra/xusb-padctl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/pmu.h>
+#include <asm/arch/tegra.h>
 #ifdef CONFIG_TEGRA_CLOCK_SCALING
 #include <asm/arch/emc.h>
 #endif
-#include <asm/arch-tegra/usb.h>
-#ifdef CONFIG_USB_EHCI_TEGRA
-#include <usb.h>
-#endif
-#include <asm/arch-tegra/xusb-padctl.h>
 #include <power/as3722.h>
-#include <i2c.h>
-#include <spi.h>
 #include "emc.h"
 
 DECLARE_GLOBAL_DATA_PTR;

index 3bb72331a4..f547942022 100644
@@ -7,6 +7,8 @@
 /* Tegra SoC common clock control functions */
 
 #include <common.h>
+#include <div64.h>
+#include <dm.h>
 #include <errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>

@@ -15,8 +17,6 @@
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/timer.h>
-#include <div64.h>
-#include <fdtdec.h>
 
 /*
  * This is our record of the current clock rate of each clock. We don't

index 41c88cb2b4..189b3da026 100644
@@ -7,6 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <debug_uart.h>
 #include <spl.h>
 
 #include <asm/io.h>

@@ -32,6 +33,9 @@ void spl_board_init(void)
 	gpio_early_init_uart();
 
 	clock_early_init();
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	preloader_console_init();
 }
 

index 3add1b3c09..3b9711d28e 100644
@@ -97,6 +97,11 @@ enum {
 	TEGRA_SOC_UNKNOWN	= -1,
 };
 
+/* Tegra system controller (SYSCON) devices */
+enum {
+	TEGRA_SYSCON_PMC,
+};
+
 #else  /* __ASSEMBLY__ */
 #define PRM_RSTCTRL		NV_PA_PMC_BASE
 #endif

new file mode 100644
index 0000000000..be82acf11e
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+
+static const struct udevice_id tegra124_syscon_ids[] = {
+	{ .compatible = "nvidia,tegra124-pmc", .data = TEGRA_SYSCON_PMC },
+};
+
+U_BOOT_DRIVER(syscon_tegra124) = {
+	.name = "tegra124_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = tegra124_syscon_ids,
+};

index b4b4c8ba4d..deccdf455d 100644
@@ -15,7 +15,7 @@ struct tegra_xusb_phy;
  */
 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
 
-void tegra_xusb_padctl_init(const void *fdt);
+void tegra_xusb_padctl_init(void);
 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);

index 943ee24e59..5aedd3ef9d 100644
@@ -164,7 +164,7 @@ int board_init(void)
 	pin_mux_nand();
 #endif
 
-	tegra_xusb_padctl_init(gd->fdt_blob);
+	tegra_xusb_padctl_init();
 
 #ifdef CONFIG_TEGRA_LP0
 	/* save Sdram params to PMC 2, 4, and 24 for WB0 */

index 76af924b94..d326a6ae57 100644
@@ -8,6 +8,8 @@
 
 #include <common.h>
 #include <errno.h>
+#include <dm/of_access.h>
+#include <dm/ofnode.h>
 
 #include "../xusb-padctl-common.h"
 

@@ -317,13 +319,33 @@ static const struct tegra_xusb_padctl_soc tegra124_socdata = {
 	.num_phys = ARRAY_SIZE(tegra124_phys),
 };
 
-void tegra_xusb_padctl_init(const void *fdt)
+void tegra_xusb_padctl_init(void)
 {
-	int count, nodes[1];
+	ofnode nodes[1];
+	int count = 0;
+	int ret;
+
+	debug("%s: start\n", __func__);
+	if (of_live_active()) {
+		struct device_node *np = of_find_compatible_node(NULL, NULL,
+						"nvidia,tegra124-xusb-padctl");
+
+		debug("np=%p\n", np);
+		if (np) {
+			nodes[0] = np_to_ofnode(np);
+			count = 1;
+		}
+	} else {
+		int node_offsets[1];
+		int i;
+
+		count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
+				COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
+				node_offsets, ARRAY_SIZE(node_offsets));
+		for (i = 0; i < count; i++)
+			nodes[i] = offset_to_ofnode(node_offsets[i]);
+	}
 
-	count = fdtdec_find_aliases_for_id(fdt, "padctl",
-					   COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
-					   nodes, ARRAY_SIZE(nodes));
-	if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra124_socdata))
-		return;
+	ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata);
+	debug("%s: done, ret=%d\n", __func__, ret);
 }

index 9ec93e7c4c..fde76dda01 100644
@@ -8,6 +8,8 @@
 
 #include <common.h>
 #include <errno.h>
+#include <dm/of_access.h>
+#include <dm/ofnode.h>
 
 #include "../xusb-padctl-common.h"
 

@@ -421,17 +423,33 @@ static const struct tegra_xusb_padctl_soc tegra210_socdata = {
 	.num_phys = ARRAY_SIZE(tegra210_phys),
 };
 
-void tegra_xusb_padctl_init(const void *fdt)
+void tegra_xusb_padctl_init(void)
 {
-	int count, nodes[1];
-
-	debug("> %s(fdt=%p)\n", __func__, fdt);
-
-	count = fdtdec_find_aliases_for_id(fdt, "padctl",
-					   COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
-					   nodes, ARRAY_SIZE(nodes));
-	if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata))
-		return;
+	ofnode nodes[1];
+	int count = 0;
+	int ret;
+
+	debug("%s: start\n", __func__);
+	if (of_live_active()) {
+		struct device_node *np = of_find_compatible_node(NULL, NULL,
+						"nvidia,tegra210-xusb-padctl");
+
+		debug("np=%p\n", np);
+		if (np) {
+			nodes[0] = np_to_ofnode(np);
+			count = 1;
+		}
+	} else {
+		int node_offsets[1];
+		int i;
+
+		count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
+				COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
+				node_offsets, ARRAY_SIZE(node_offsets));
+		for (i = 0; i < count; i++)
+			nodes[i] = offset_to_ofnode(node_offsets[i]);
+	}
 
-	debug("< %s()\n", __func__);
+	ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
+	debug("%s: done, ret=%d\n", __func__, ret);
 }

155 lines not on this page · raw message

index f44790a650..afb62a9adc 100644
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <fdtdec.h>
+#include <dm/ofnode.h>
 
 #include <asm/io.h>
 #include <asm/arch-tegra/xusb-padctl.h>

@@ -77,7 +78,7 @@ struct tegra_xusb_padctl_config {
 struct tegra_xusb_padctl {
 	const struct tegra_xusb_padctl_soc *socdata;
 	struct tegra_xusb_padctl_config config;
-	struct fdt_resource regs;
+	ulong regs;
 	unsigned int enable;
 
 };

@@ -86,16 +87,16 @@ extern struct tegra_xusb_padctl padctl;
 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
 			       unsigned long offset)
 {
-	return readl(padctl->regs.start + offset);
+	return readl(padctl->regs + offset);
 }
 
 static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
 				 u32 value, unsigned long offset)
 {
-	writel(value, padctl->regs.start + offset);
+	writel(value, padctl->regs + offset);
 }
 
-int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
-	const struct tegra_xusb_padctl_soc *socdata);
+int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
+			     const struct tegra_xusb_padctl_soc *socdata);
 
 #endif

index 65f8d2ea96..856d712512 100644
@@ -34,6 +34,6 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
 	return -ENOSYS;
 }
 
-void __weak tegra_xusb_padctl_init(const void *fdt)
+void __weak tegra_xusb_padctl_init(void)
 {
 }

index 388afcb723..301de4a899 100644
@@ -266,7 +266,7 @@ void clock_ll_start_uart(enum periph_id periph_id);
  * @param node		Node to look at
  * @return peripheral ID, or PERIPH_ID_NONE if none
  */
-enum periph_id clock_decode_periph_id(const void *blob, int node);
+int clock_decode_periph_id(struct udevice *dev);
 
 /**
  * Checks if the oscillator bypass is enabled (XOBP bit)

index f547942022..090dba629c 100644
@@ -652,14 +652,13 @@ void clock_ll_start_uart(enum periph_id periph_id)
 }
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
-int clock_decode_periph_id(const void *blob, int node)
+int clock_decode_periph_id(struct udevice *dev)
 {
 	enum periph_id id;
 	u32 cell[2];
 	int err;
 
-	err = fdtdec_get_int_array(blob, node, "clocks", cell,
-				   ARRAY_SIZE(cell));
+	err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
 	if (err)
 		return -1;
 	id = clk_id_to_periph_id(cell[1]);

index 802117eb49..86b1019585 100644
@@ -104,7 +104,7 @@ static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
 	int node = dev_of_offset(bus);
 
 	plat->base = devfdt_get_addr(bus);
-	plat->periph_id = clock_decode_periph_id(blob, node);
+	plat->periph_id = clock_decode_periph_id(bus);
 
 	if (plat->periph_id == PERIPH_ID_NONE) {
 		debug("%s: could not decode periph id %d\n", __func__,

index 299e1b44fa..e70210d7ab 100644
@@ -91,7 +91,7 @@ static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
 	int node = dev_of_offset(bus);
 
 	plat->base = devfdt_get_addr(bus);
-	plat->periph_id = clock_decode_periph_id(blob, node);
+	plat->periph_id = clock_decode_periph_id(bus);
 
 	if (plat->periph_id == PERIPH_ID_NONE) {
 		debug("%s: could not decode periph id %d\n", __func__,

index 4cbde7b22f..f242574760 100644
@@ -97,7 +97,7 @@ static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
 	int node = dev_of_offset(bus);
 
 	plat->base = devfdt_get_addr(bus);
-	plat->periph_id = clock_decode_periph_id(blob, node);
+	plat->periph_id = clock_decode_periph_id(bus);
 
 	if (plat->periph_id == PERIPH_ID_NONE) {
 		debug("%s: could not decode periph id %d\n", __func__,

index 6d0b5da261..2a35a583f5 100644
@@ -100,7 +100,7 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
 	int node = dev_of_offset(bus);
 
 	plat->base = devfdt_get_addr(bus);
-	plat->periph_id = clock_decode_periph_id(blob, node);
+	plat->periph_id = clock_decode_periph_id(bus);
 
 	if (plat->periph_id == PERIPH_ID_NONE) {
 		debug("%s: could not decode periph id %d\n", __func__,

index 7dc37f045d..873bf8ecfd 100644
@@ -723,7 +723,7 @@ static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
 	config->enabled = fdtdec_get_is_enabled(blob, node);
 	config->has_legacy_mode = fdtdec_get_bool(blob, node,
 						  "nvidia,has-legacy-mode");
-	config->periph_id = clock_decode_periph_id(blob, node);
+	config->periph_id = clock_decode_periph_id(dev);
 	if (config->periph_id == PERIPH_ID_NONE) {
 		debug("%s: Missing/invalid peripheral ID\n", __func__);
 		return -EINVAL;

index 47752b27f1..4164fa1bd9 100644
@@ -12,7 +12,6 @@
 #include <errno.h>
 #include <display.h>
 #include <edid.h>
-#include <fdtdec.h>
 #include <lcd.h>
 #include <video.h>
 #include <asm/gpio.h>

@@ -334,7 +333,6 @@ static int display_init(struct udevice *dev, void *lcdbase,
 {
 	struct display_plat *disp_uc_plat;
 	struct dc_ctlr *dc_ctlr;
-	const void *blob = gd->fdt_blob;
 	struct udevice *dp_dev;
 	const int href_to_sync = 1, vref_to_sync = 1;
 	int panel_bpp = 18;	/* default 18 bits per pixel */

@@ -363,9 +361,8 @@ static int display_init(struct udevice *dev, void *lcdbase,
 		return ret;
 	}
 
-	dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev_of_offset(dev),
-						    "reg");
-	if (fdtdec_decode_display_timing(blob, dev_of_offset(dev), 0, timing)) {
+	dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
+	if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
 		debug("%s: Failed to decode display timing\n", __func__);
 		return -EINVAL;
 	}

@@ -416,6 +413,7 @@ static int display_init(struct udevice *dev, void *lcdbase,
 		debug("dc: failed to update window\n");
 		return ret;
 	}
+	debug("%s: ready\n", __func__);
 
 	return 0;
 }

index c38b3e5335..95d743d0f4 100644
@@ -10,7 +10,6 @@
 #include <dm.h>
 #include <div64.h>
 #include <errno.h>
-#include <fdtdec.h>
 #include <video_bridge.h>
 #include <asm/io.h>
 #include <asm/arch-tegra/dc.h>

@@ -1572,7 +1571,7 @@ static int tegra_dp_ofdata_to_platdata(struct udevice *dev)
 {
 	struct tegra_dp_plat *plat = dev_get_platdata(dev);
 
-	plat->base = devfdt_get_addr(dev);
+	plat->base = dev_read_addr(dev);
 
 	return 0;
 }

index 5e4140ff53..1f5e572bda 100644
@@ -7,9 +7,9 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <fdtdec.h>
 #include <malloc.h>
 #include <panel.h>
+#include <syscon.h>
 #include <video_bridge.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>

@@ -750,15 +750,12 @@ int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev,
 			const struct display_timing *timing)
 {
 	struct tegra_dc_sor_data *sor = dev_get_priv(dev);
-	const void *blob = gd->fdt_blob;
 	struct dc_ctlr *disp_ctrl;
 	u32 reg_val;
-	int node;
 
 	/* Use the first display controller */
 	debug("%s\n", __func__);
-	node = dev_of_offset(dc_dev);
-	disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
 
 	tegra_dc_sor_enable_dc(disp_ctrl);
 	tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);

@@ -965,16 +962,13 @@ int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev)
 {
 	struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 	int dc_reg_ctx[DC_REG_SAVE_SPACE];
-	const void *blob = gd->fdt_blob;
 	struct dc_ctlr *disp_ctrl;
 	unsigned long dc_int_mask;
-	int node;
 	int ret;
 
 	debug("%s\n", __func__);
 	/* Use the first display controller */
-	node = dev_of_offset(dc_dev);
-	disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
 
 	/* Sleep mode */
 	tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |

@@ -1041,18 +1035,13 @@ static int tegra_sor_set_backlight(struct udevice *dev, int percent)
 static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
 {
 	struct tegra_dc_sor_data *priv = dev_get_priv(dev);
-	const void *blob = gd->fdt_blob;
-	int node;
 	int ret;
 
-	priv->base = (void *)fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
+	priv->base = (void *)dev_read_addr(dev);
 
-	node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
-	if (node < 0) {
-		debug("%s: Cannot find PMC\n", __func__);
-		return -ENOENT;
-	}
-	priv->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
+	priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
+	if (IS_ERR(priv->pmc_base))
+		return PTR_ERR(priv->pmc_base);
 
 	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
 					   &priv->panel);

index b3a041b539..c478420655 100644
@@ -187,7 +187,9 @@ static void setup_uarts(int uart_ids)
 			enum periph_id id = id_for_uart[i];
 
 			funcmux_select(id, uart_configs[i]);
+#ifdef CONFIG_SPL_BUILD
 			clock_ll_start_uart(id);
+#endif
 		}
 	}
 }

index 687cd74fee..4965583158 100644
@@ -337,11 +337,13 @@ static int gpio_tegra_bind(struct udevice *parent)
 	 * This driver does not make use of interrupts, other than to figure
 	 * out the number of GPIO banks
 	 */
-	if (!fdt_getprop(gd->fdt_blob, dev_of_offset(parent), "interrupts",
-			 &len))
-		return -EINVAL;
+	len = dev_read_size(parent, "interrupts");
+	if (len < 0)
+		return len;
 	bank_count = len / 3 / sizeof(u32);
-	ctlr = (struct gpio_ctlr *)devfdt_get_addr(parent);
+	ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
+	if ((ulong)ctlr == FDT_ADDR_T_NONE)
+		return -EINVAL;
 	}
 #endif
 	for (bank = 0; bank < bank_count; bank++) {

index 873bf8ecfd..1c72330b0c 100644
@@ -17,7 +17,6 @@
 #include <usb.h>
 #include <usb/ulpi.h>
 #include <libfdt.h>
-#include <fdtdec.h>
 
 #include "ehci.h"
 

@@ -695,12 +694,11 @@ static void config_clock(const u32 timing[])
 
 static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
 {
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(dev);
 	const char *phy, *mode;
 
-	config->reg = (struct usb_ctlr *)devfdt_get_addr(dev);
-	mode = fdt_getprop(blob, node, "dr_mode", NULL);
+	config->reg = (struct usb_ctlr *)dev_read_addr(dev);
+	debug("reg=%p\n", config->reg);
+	mode = dev_read_string(dev, "dr_mode");
 	if (mode) {
 		if (0 == strcmp(mode, "host"))
 			config->dr_mode = DR_MODE_HOST;

@@ -717,28 +715,24 @@ static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
 		config->dr_mode = DR_MODE_HOST;
 	}
 
-	phy = fdt_getprop(blob, node, "phy_type", NULL);
+	phy = dev_read_string(dev, "phy_type");
 	config->utmi = phy && 0 == strcmp("utmi", phy);
 	config->ulpi = phy && 0 == strcmp("ulpi", phy);
-	config->enabled = fdtdec_get_is_enabled(blob, node);
-	config->has_legacy_mode = fdtdec_get_bool(blob, node,
-						  "nvidia,has-legacy-mode");
+	config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode");
 	config->periph_id = clock_decode_periph_id(dev);
 	if (config->periph_id == PERIPH_ID_NONE) {
 		debug("%s: Missing/invalid peripheral ID\n", __func__);
 		return -EINVAL;
 	}
-	gpio_request_by_name_nodev(offset_to_ofnode(node), "nvidia,vbus-gpio",
-				   0, &config->vbus_gpio, GPIOD_IS_OUT);
-	gpio_request_by_name_nodev(offset_to_ofnode(node),
-				   "nvidia,phy-reset-gpio", 0,
-				   &config->phy_reset_gpio, GPIOD_IS_OUT);
-	debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
-		"vbus=%d, phy_reset=%d, dr_mode=%d\n",
-		config->enabled, config->has_legacy_mode, config->utmi,
-		config->ulpi, config->periph_id,
-		gpio_get_number(&config->vbus_gpio),
-		gpio_get_number(&config->phy_reset_gpio), config->dr_mode);
+	gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio,
+			     GPIOD_IS_OUT);
+	gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0,
+			     &config->phy_reset_gpio, GPIOD_IS_OUT);
+	debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n",
+	      config->has_legacy_mode, config->utmi, config->ulpi,
+	      config->periph_id, gpio_get_number(&config->vbus_gpio),
+	      gpio_get_number(&config->phy_reset_gpio), config->dr_mode,
+	      config->reg);
 
 	return 0;
 }

index 86b1019585..013bc82380 100644
@@ -12,7 +12,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <spi.h>
-#include <fdtdec.h>
 #include "tegra_spi.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -100,10 +99,8 @@ struct tegra114_spi_priv {
 static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
 {
 	struct tegra_spi_platdata *plat = bus->platdata;
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(bus);
 
-	plat->base = devfdt_get_addr(bus);
+	plat->base = dev_read_addr(bus);
 	plat->periph_id = clock_decode_periph_id(bus);
 
 	if (plat->periph_id == PERIPH_ID_NONE) {

@@ -113,10 +110,10 @@ static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
 	}
 
 	/* Use 500KHz as a suitable default */
-	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
-					500000);
-	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
-					"spi-deactivate-delay", 0);
+	plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
+					       500000);
+	plat->deactivate_delay_us = dev_read_u32_default(bus,
+						"spi-deactivate-delay", 0);
 	debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
 	      __func__, plat->base, plat->periph_id, plat->frequency,
 	      plat->deactivate_delay_us);

index 055f48153a..4163d798d5 100644
@@ -365,7 +365,11 @@ static int tegra_i2c_probe(struct udevice *dev)
 
 	i2c_bus->id = dev->seq;
 	i2c_bus->type = dev_get_driver_data(dev);
-	i2c_bus->regs = (struct i2c_ctlr *)devfdt_get_addr(dev);
+	i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
+	if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
+		debug("%s: Cannot get regs address\n", __func__);
+		return -EINVAL;
+	}
 
 	ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
 	if (ret) {

index d93ac28c31..b8acc1583f 100644
@@ -59,7 +59,7 @@ static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
 {
 	struct tegra_pwm_priv *priv = dev_get_priv(dev);
 
-	priv->regs = (struct pwm_ctlr *)devfdt_get_addr(dev);
+	priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
 
 	return 0;
 }

index 338e42b528..9f7e7195f1 100644
@@ -11,10 +11,10 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
+#include <mmc.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch-tegra/tegra_mmc.h>
-#include <mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -599,8 +599,7 @@ static int tegra_mmc_probe(struct udevice *dev)
 
 	cfg->name = dev->name;
 
-	bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-				   "bus-width", 1);
+	bus_width = dev_read_u32_default(dev, "bus-width", 1);
 
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 	cfg->host_caps = 0;

@@ -621,7 +620,7 @@ static int tegra_mmc_probe(struct udevice *dev)
 
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-	priv->reg = (void *)devfdt_get_addr(dev);
+	priv->reg = (void *)dev_read_addr(dev);
 
 	ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
 	if (ret) {

@@ -648,12 +647,10 @@ static int tegra_mmc_probe(struct udevice *dev)
 		return ret;
 
 	/* These GPIOs are optional */
-	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
-			     GPIOD_IS_IN);
-	gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
-			     GPIOD_IS_IN);
-	gpio_request_by_name(dev, "power-gpios", 0,
-			     &priv->pwr_gpio, GPIOD_IS_OUT);
+	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
+	gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
+	gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
+			     GPIOD_IS_OUT);
 	if (dm_gpio_is_valid(&priv->pwr_gpio))
 		dm_gpio_set_value(&priv->pwr_gpio, 1);
 

149 lines not on this page · raw message

index 0f22482ff7..14afa0c81a 100644
@@ -12,6 +12,14 @@
 #define AS3722_GPIO_OUTPUT_VDDH (1 << 0)
 #define AS3722_GPIO_INVERT (1 << 1)
 
+#define AS3722_DEVICE_ID 0x0c
+#define AS3722_SD_VOLTAGE(n) (0x00 + (n))
+#define AS3722_LDO_VOLTAGE(n) (0x10 + (n))
+#define AS3722_SD_CONTROL 0x4d
+#define AS3722_LDO_CONTROL 0x4e
+#define AS3722_ASIC_ID1 0x90
+#define AS3722_ASIC_ID2 0x91
+
 struct udevice;
 
 int as3722_init(struct udevice **devp);

new file mode 100644
index 0000000000..d0b681ca4a
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <power/as3722.h>
+#include <power/pmic.h>
+
+#define NUM_GPIOS	8
+
+int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
+			  unsigned long flags)
+{
+	u8 value = 0;
+	int err;
+
+	if (flags & AS3722_GPIO_OUTPUT_VDDH)
+		value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+
+	if (flags & AS3722_GPIO_INVERT)
+		value |= AS3722_GPIO_CONTROL_INVERT;
+
+	err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
+	if (err) {
+		error("failed to configure GPIO#%u: %d", gpio, err);
+		return err;
+	}
+
+	return 0;
+}
+
+static int as3722_gpio_set_value(struct udevice *dev, unsigned int gpio,
+				 int level)
+{
+	struct udevice *pmic = dev_get_parent(dev);
+	const char *l;
+	u8 value;
+	int err;
+
+	if (gpio >= NUM_GPIOS)
+		return -EINVAL;
+
+	err = pmic_reg_read(pmic, AS3722_GPIO_SIGNAL_OUT);
+	if (err < 0) {
+		error("failed to read GPIO signal out register: %d", err);
+		return err;
+	}
+	value = err;
+
+	if (level == 0) {
+		value &= ~(1 << gpio);
+		l = "low";
+	} else {
+		value |= 1 << gpio;
+		l = "high";
+	}
+
+	err = pmic_reg_write(pmic, AS3722_GPIO_SIGNAL_OUT, value);
+	if (err) {
+		error("failed to set GPIO#%u %s: %d", gpio, l, err);
+		return err;
+	}
+
+	return 0;
+}
+
+int as3722_gpio_direction_output(struct udevice *dev, unsigned int gpio,
+				 int value)
+{
+	struct udevice *pmic = dev_get_parent(dev);
+	int err;
+
+	if (gpio > 7)
+		return -EINVAL;
+
+	if (value == 0)
+		value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL;
+	else
+		value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+
+	err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
+	if (err) {
+		error("failed to configure GPIO#%u as output: %d", gpio, err);
+		return err;
+	}
+
+	err = as3722_gpio_set_value(pmic, gpio, value);
+	if (err < 0) {
+		error("failed to set GPIO#%u high: %d", gpio, err);
+		return err;
+	}
+
+	return 0;
+}
+
+static int as3722_gpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	uc_priv->gpio_count = NUM_GPIOS;
+	uc_priv->bank_name = "as3722_";
+
+	return 0;
+}
+
+static const struct dm_gpio_ops gpio_as3722_ops = {
+	.direction_output	= as3722_gpio_direction_output,
+	.set_value		= as3722_gpio_set_value,
+};
+
+U_BOOT_DRIVER(gpio_as3722) = {
+	.name	= "gpio_as3722",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_as3722_ops,
+	.probe	= as3722_gpio_probe,
+};

index 14afa0c81a..713e79840f 100644
@@ -20,6 +20,11 @@
 #define AS3722_ASIC_ID1 0x90
 #define AS3722_ASIC_ID2 0x91
 
+#define AS3722_GPIO_CONTROL(n) (0x08 + (n))
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
+#define AS3722_GPIO_CONTROL_INVERT (1 << 7)
+
 struct udevice;
 
 int as3722_init(struct udevice **devp);

index 5aedd3ef9d..0291c7fb33 100644
@@ -29,7 +29,6 @@
 #ifdef CONFIG_TEGRA_CLOCK_SCALING
 #include <asm/arch/emc.h>
 #endif
-#include <power/as3722.h>
 #include "emc.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -142,11 +141,6 @@ int board_init(void)
 		debug("Memory controller init failed: %d\n", err);
 #  endif
 # endif /* CONFIG_TEGRA_PMU */
-#ifdef CONFIG_PMIC_AS3722
-	err = as3722_init(NULL);
-	if (err && err != -ENODEV)
-		return err;
-#endif
 #endif /* CONFIG_SYS_I2C_TEGRA */
 
 #ifdef CONFIG_USB_EHCI_TEGRA

index 8f68ae9fbe..54acf5418d 100644
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <asm/gpio.h>
 #include <asm/io.h>

@@ -46,20 +47,23 @@ int tegra_board_id(void)
 
 int tegra_lcd_pmic_init(int board_id)
 {
-	struct udevice *pmic;
+	struct udevice *dev;
 	int ret;
 
-	ret = as3722_get(&pmic);
-	if (ret)
-		return -ENOENT;
+	ret = uclass_get_device_by_driver(UCLASS_PMIC,
+					  DM_GET_DRIVER(pmic_as3722), &dev);
+	if (ret) {
+		debug("%s: Failed to find PMIC\n", __func__);
+		return ret;
+	}
 
 	if (board_id == 0)
-		as3722_write(pmic, 0x00, 0x3c);
+		pmic_reg_write(dev, 0x00, 0x3c);
 	else
-		as3722_write(pmic, 0x00, 0x50);
-	as3722_write(pmic, 0x12, 0x10);
-	as3722_write(pmic, 0x0c, 0x07);
-	as3722_write(pmic, 0x20, 0x10);
+		pmic_reg_write(dev, 0x00, 0x50);
+	pmic_reg_write(dev, 0x12, 0x10);
+	pmic_reg_write(dev, 0x0c, 0x07);
+	pmic_reg_write(dev, 0x20, 0x10);
 
 	return 0;
 }

362 lines not on this page · raw message

index 713e79840f..491f1b7ea7 100644
@@ -7,8 +7,6 @@
 #ifndef __POWER_AS3722_H__
 #define __POWER_AS3722_H__
 
-#include <asm/types.h>
-
 #define AS3722_GPIO_OUTPUT_VDDH (1 << 0)
 #define AS3722_GPIO_INVERT (1 << 1)
 

@@ -21,23 +19,9 @@
 #define AS3722_ASIC_ID2 0x91
 
 #define AS3722_GPIO_CONTROL(n) (0x08 + (n))
+#define AS3722_GPIO_SIGNAL_OUT 0x20
 #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
 #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
 #define AS3722_GPIO_CONTROL_INVERT (1 << 7)
 
-struct udevice;
-
-int as3722_init(struct udevice **devp);
-int as3722_sd_enable(struct udevice *pmic, unsigned int sd);
-int as3722_sd_set_voltage(struct udevice *pmic, unsigned int sd, u8 value);
-int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo);
-int as3722_ldo_set_voltage(struct udevice *pmic, unsigned int ldo, u8 value);
-int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
-			  unsigned long flags);
-int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio,
-				 unsigned int level);
-int as3722_read(struct udevice *pmic, u8 reg, u8 *value);
-int as3722_write(struct udevice *pmic, u8 reg, u8 value);
-int as3722_get(struct udevice **devp);
-
 #endif /* __POWER_AS3722_H__ */

index 52c52c1ad1..330c5e186a 100644
@@ -8,7 +8,6 @@
 #include <clk.h>
 #include <dm.h>
 #include <errno.h>
-#include <fdtdec.h>
 #include <ns16550.h>
 #include <serial.h>
 #include <watchdog.h>

@@ -395,7 +394,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 	int err;
 
 	/* try Processor Local Bus device first */
-	addr = devfdt_get_addr(dev);
+	addr = dev_read_addr(dev);
 #if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
 	if (addr == FDT_ADDR_T_NONE) {
 		/* then try pci device */

@@ -434,11 +433,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 	plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
 #endif
 
-	plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-				     "reg-offset", 0);
-	plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					 "reg-shift", 0);
-
+	plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
+	plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
 	err = clk_get_by_index(dev, 0, &clk);
 	if (!err) {
 		err = clk_get_rate(&clk);

@@ -450,9 +446,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 	}
 
 	if (!plat->clock)
-		plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					     "clock-frequency",
-					     CONFIG_SYS_NS16550_CLK);
+		plat->clock = dev_read_u32_default(dev, "clock-frequency",
+						   CONFIG_SYS_NS16550_CLK);
 	if (!plat->clock) {
 		debug("ns16550 clock not defined\n");
 		return -EINVAL;

index a9c4f89e1a..ede5c2c0be 100644
@@ -8,7 +8,6 @@
 #include <dm.h>
 #include <environment.h>
 #include <errno.h>
-#include <fdtdec.h>
 #include <os.h>
 #include <serial.h>
 #include <stdio_dev.h>

@@ -27,11 +26,53 @@ static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
 #error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN to make this work"
 #endif
 
+static int serial_check_stdout(const void *blob, struct udevice **devp)
+{
+	int node;
+
+	/* Check for a chosen console */
+	node = fdtdec_get_chosen_node(blob, "stdout-path");
+	if (node < 0) {
+		const char *str, *p, *name;
+
+		/*
+		 * Deal with things like
+		 *	stdout-path = "serial0:115200n8";
+		 *
+		 * We need to look up the alias and then follow it to the
+		 * correct node.
+		 */
+		str = fdtdec_get_chosen_prop(blob, "stdout-path");
+		if (str) {
+			p = strchr(str, ':');
+			name = fdt_get_alias_namelen(blob, str,
+					p ? p - str : strlen(str));
+			if (name)
+				node = fdt_path_offset(blob, name);
+		}
+	}
+	if (node < 0)
+		node = fdt_path_offset(blob, "console");
+	if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, devp))
+		return 0;
+
+	/*
+	 * If the console is not marked to be bound before relocation, bind it
+	 * anyway.
+	 */
+	if (node > 0 && !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
+					devp)) {
+		if (!device_probe(*devp))
+			return 0;
+	}
+
+	return -ENODEV;
+}
+
 static void serial_find_console_or_panic(void)
 {
 	const void *blob = gd->fdt_blob;
 	struct udevice *dev;
-	int node;
 
 	if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
 		uclass_first_device(UCLASS_SERIAL, &dev);

@@ -40,47 +81,10 @@ static void serial_find_console_or_panic(void)
 			return;
 		}
 	} else if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) {
-		/* Check for a chosen console */
-		node = fdtdec_get_chosen_node(blob, "stdout-path");
-		if (node < 0) {
-			const char *str, *p, *name;
-
-			/*
-			 * Deal with things like
-			 *	stdout-path = "serial0:115200n8";
-			 *
-			 * We need to look up the alias and then follow it to
-			 * the correct node.
-			 */
-			str = fdtdec_get_chosen_prop(blob, "stdout-path");
-			if (str) {
-				p = strchr(str, ':');
-				name = fdt_get_alias_namelen(blob, str,
-						p ? p - str : strlen(str));
-				if (name)
-					node = fdt_path_offset(blob, name);
-			}
-		}
-		if (node < 0)
-			node = fdt_path_offset(blob, "console");
-		if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node,
-						    &dev)) {
+		if (!serial_check_stdout(blob, &dev)) {
 			gd->cur_serial_dev = dev;
 			return;
 		}
-
-		/*
-		 * If the console is not marked to be bound before relocation,
-		 * bind it anyway.
-		 */
-		if (node > 0 &&
-		    !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
-				    &dev)) {
-			if (!device_probe(dev)) {
-				gd->cur_serial_dev = dev;
-				return;
-			}
-		}
 	}
 	if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !blob) {
 		/*

index ede5c2c0be..976b99ce7c 100644
@@ -14,6 +14,7 @@
 #include <watchdog.h>
 #include <dm/lists.h>
 #include <dm/device-internal.h>
+#include <dm/of_access.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -81,9 +82,20 @@ static void serial_find_console_or_panic(void)
 			return;
 		}
 	} else if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) {
-		if (!serial_check_stdout(blob, &dev)) {
-			gd->cur_serial_dev = dev;
-			return;
+		/* Live tree has support for stdout */
+		if (of_live_active()) {
+			struct device_node *np = of_get_stdout();
+
+			if (np && !uclass_get_device_by_ofnode(UCLASS_SERIAL,
+					np_to_ofnode(np), &dev)) {
+				gd->cur_serial_dev = dev;
+				return;
+			}
+		} else {
+			if (!serial_check_stdout(blob, &dev)) {
+				gd->cur_serial_dev = dev;
+				return;
+			}
 		}
 	}
 	if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !blob) {

index 0291c7fb33..e0a39e1a32 100644
@@ -150,8 +150,10 @@ int board_init(void)
 #if defined(CONFIG_DM_VIDEO)
 	board_id = tegra_board_id();
 	err = tegra_lcd_pmic_init(board_id);
-	if (err)
+	if (err) {
+		debug("Failed to set up LCD PMIC\n");
 		return err;
+	}
 #endif
 
 #ifdef CONFIG_TEGRA_NAND

index eda2ffaf66..4a0947c626 100644
@@ -119,12 +119,6 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_EMC,	/* Tegra20 memory controller */
 	COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
 	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
-	COMPAT_NVIDIA_TEGRA124_PMC,	/* Tegra 124 power mgmt controller */
-	COMPAT_NVIDIA_TEGRA186_SDMMC,	/* Tegra186 SDMMC controller */
-	COMPAT_NVIDIA_TEGRA210_SDMMC,	/* Tegra210 SDMMC controller */
-	COMPAT_NVIDIA_TEGRA124_SDMMC,	/* Tegra124 SDMMC controller */
-	COMPAT_NVIDIA_TEGRA30_SDMMC,	/* Tegra30 SDMMC controller */
-	COMPAT_NVIDIA_TEGRA20_SDMMC,	/* Tegra20 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
 					/* Tegra124 XUSB pad controller */
 	COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,

index 91503b8cb9..9818f78c51 100644
@@ -33,12 +33,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
 	COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
 	COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
-	COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
-	COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
-	COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
-	COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
-	COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
-	COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
 	COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
 	COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
 	COMPAT(SMSC_LAN9215, "smsc,lan9215"),