ARM: imx: add imx7ulp support

PATCH Superseded Dong Aisheng 5 participants 13 messages May 17, 2017 – May 23, 2017

Subsystems (5)

Device tree bindings Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape +1 more subsystems

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Dong Aisheng

author

2017-05-17 15:50 UTC #0 lore raw

cover ARM: imx: add imx7ulp support

This patch series adds the basic support for imx7ulp. It includes machine level support code and device tree.

It depends on some of other driver patch series as follows which were sent out a few days ago and still under review:

[PATCH 0/9] clk: add imx7ulp clk support
https://www.spinics.net/lists/linux-clk/msg17037.html

[PATCH V2 0/6] tty: serial: lpuart: add imx7ulp support
https://www.spinics.net/lists/arm-kernel/msg581005.html

[PATCH 0/2] gpio: add imx7ulp gpio support
https://www.spinics.net/lists/arm-kernel/msg580990.html

[PATCH 0/2] pinctrl: pinctrl-imx: add gpio support for mx7ulp
https://www.spinics.net/lists/arm-kernel/msg580993.html

[PATCH 0/5] pinctrl: imx: add generic pin config and imx7ulp support
https://www.spinics.net/lists/arm-kernel/msg580737.html

[PATCH 1/2] dt-bindings: timer: add nxp tpm timer binding doc
https://www.mail-archive.com/linux-kernel at vger.kernel.org/msg1395534.html

[PATCH 2/2] timer: imx-tpm: add imx tpm timer support
https://www.mail-archive.com/linux-kernel at vger.kernel.org/msg1395536.html

[PATCH 0/2] gpio: add imx7ulp gpio support
https://www.spinics.net/lists/arm-kernel/msg580990.html

Shawn,

i will let you know once they're merged by each subsystem.

Dong Aisheng (4):
dt-bindings: fsl: add compatible for imx7ulp evk
ARM: imx: add initial support for imx7ulp
dts: imx: add imx7ulp evk support
ARM: imx_v6_v7_defconfig: add imx7ulp support

 Documentation/devicetree/bindings/arm/fsl.txt |   8 +
 arch/arm/boot/dts/Makefile                    |   2 +
 arch/arm/boot/dts/imx7ulp-evk.dts             |  98 ++++++++
 arch/arm/boot/dts/imx7ulp.dtsi                | 310 ++++++++++++++++++++++++++
 arch/arm/configs/imx_v6_v7_defconfig          |   5 +-
 arch/arm/mach-imx/Kconfig                     |   9 +
 arch/arm/mach-imx/Makefile                    |   1 +
 arch/arm/mach-imx/common.h                    |   1 +
 arch/arm/mach-imx/cpu.c                       |   3 +
 arch/arm/mach-imx/mach-imx7ulp.c              |  37 +++
 arch/arm/mach-imx/mxc.h                       |   1 +
 arch/arm/mach-imx/pm-imx7ulp.c                |  33 +++
 12 files changed, 506 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
 create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
 create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c

Signature · 1 line

2.7.4

Dong Aisheng

author

2017-05-17 15:50 UTC #1 lore raw

PATCH 1/4 dt-bindings: fsl: add compatible for imx7ulp evk

Cc Rob Herring <[email protected]>

Cc devicetree at vger.kernel.org

Cc Shawn Guo <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

Documentation/devicetree/bindings/arm/fsl.txt +8 -0

index cdb9dd7..ea10b1f 100644
@@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board
 Required root node properties:
     - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
 
+i.MX7ULP Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
+
 Generic i.MX boards
 -------------------

@@ -75,6 +79,10 @@ i.MX6q generic board
 Required root node properties:
     - compatible = "fsl,imx6q";
 
+i.MX7ULP generic board
+Required root node properties:
+    - compatible = "fsl,imx7ulp";
+
 Freescale Vybrid Platform Device Tree Bindings
 ----------------------------------------------

Signature · 1 line

2.7.4

Rob Herring

maintainer

2017-05-23 00:51 UTC #2 lore raw

PATCH 1/4 dt-bindings: fsl: add compatible for imx7ulp evk

Quoted 7 lines · Dong Aisheng

Cc Rob Herring <[email protected]>
Cc devicetree at vger.kernel.org
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
 Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

Acked-by Rob Herring <[email protected]>

Dong Aisheng

author

2017-05-17 15:50 UTC #3 lore raw

PATCH 2/4 ARM: imx: add initial support for imx7ulp

In reply to Dong Aisheng

Add initial support for imx7ulp.

Note that we need configure power mode to Partial Stop mode 3 with system/bus clock enabled first as the default enabled STOP mode will gate off system/bus clock when execute WFI in MX7ULP SoC.

And there's still no MXC_CPU_IMX7ULP IDs read from register as ULP has no anatop as before. So we encode one with 0xff in reverse order in case new ones will be in the future.

Cc Shawn Guo <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 arch/arm/mach-imx/Kconfig        |  9 +++++++++
 arch/arm/mach-imx/Makefile       |  1 +
 arch/arm/mach-imx/common.h       |  1 +
 arch/arm/mach-imx/cpu.c          |  3 +++
 arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/mxc.h          |  1 +
 arch/arm/mach-imx/pm-imx7ulp.c   | 33 +++++++++++++++++++++++++++++++++
 7 files changed, 85 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
 create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c

arch/arm/mach-imx/Kconfig +9 -0

index 936c59d..a07081d 100644
@@ -553,6 +553,15 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
 
 if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
 
+config SOC_IMX7ULP
+	bool "i.MX7ULP support"
+	select ARM_GIC
+	select CLKSRC_IMX_TPM
+	select HAVE_ARM_ARCH_TIMER
+	select PINCTRL_IMX7ULP
+	help
+	  This enables support for Freescale i.MX7 Ultra Low Power processor.
+
 config SOC_VF610
 	bool "Vybrid Family VF610 support"
 	select ARM_GIC if ARCH_MULTI_V7

arch/arm/mach-imx/Makefile +1 -0

index cab1289..c5948b7 100644
@@ -80,6 +80,7 @@ obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
 obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
 obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
 obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
 
 ifeq ($(CONFIG_SUSPEND),y)
 AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a

arch/arm/mach-imx/common.h +1 -0

index b09a2ec..b0e85df 100644
@@ -128,6 +128,7 @@ void imx6dl_pm_init(void);
 void imx6sl_pm_init(void);
 void imx6sx_pm_init(void);
 void imx6ul_pm_init(void);
+void imx7ulp_pm_init(void);
 
 #ifdef CONFIG_PM
 void imx51_pm_init(void);

arch/arm/mach-imx/cpu.c +3 -0

index b3347d3..3867e7f 100644
@@ -134,6 +134,9 @@ struct device * __init imx_soc_device_init(void)
 	case MXC_CPU_IMX7D:
 		soc_id = "i.MX7D";
 		break;
+	case MXC_CPU_IMX7ULP:
+		soc_id = "i.MX7ULP";
+		break;
 	default:
 		soc_id = "Unknown";
 	}

arch/arm/mach-imx/mach-imx7ulp.c new file +37 -0

new file mode 100644
index 0000000..9f7a25c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+#include "hardware.h"
+
+static void __init imx7ulp_init_machine(void)
+{
+	imx7ulp_pm_init();
+
+	mxc_set_cpu_type(MXC_CPU_IMX7ULP);
+	imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_1_0);
+	of_platform_default_populate(NULL, NULL, imx_soc_device_init());
+}
+
+static const char *const imx7ulp_dt_compat[] __initconst = {
+	"fsl,imx7ulp",
+	NULL,
+};
+
+DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
+	.init_machine	= imx7ulp_init_machine,
+	.dt_compat	= imx7ulp_dt_compat,
+MACHINE_END

arch/arm/mach-imx/mxc.h +1 -0

index 34f2ff6..3dfb09c 100644
@@ -40,6 +40,7 @@
 #define MXC_CPU_IMX6Q		0x63
 #define MXC_CPU_IMX6UL		0x64
 #define MXC_CPU_IMX7D		0x72
+#define MXC_CPU_IMX7ULP		0xff
 
 #define IMX_DDR_TYPE_LPDDR2		1

arch/arm/mach-imx/pm-imx7ulp.c new file +33 -0

new file mode 100644
index 0000000..df5d6b6
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SMC_PMCTRL		0x10
+#define BP_PMCTRL_PSTOPO        16
+#define PSTOPO_PSTOP3		0x3
+
+void __init imx7ulp_pm_init(void)
+{
+	struct device_node *np;
+	void __iomem *smc1_base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
+	smc1_base = of_iomap(np, 0);
+	WARN_ON(!smc1_base);
+
+	/* Partial Stop mode 3 with system/bus clock enabled */
+	writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO,
+		       smc1_base + SMC_PMCTRL);
+}

Signature · 1 line

2.7.4

Stefan Wahren

2017-05-17 17:36 UTC #4 lore raw

PATCH 2/4 ARM: imx: add initial support for imx7ulp

Hi Dong,

Quoted 162 lines

Dong Aisheng <[email protected]> hat am 17. Mai 2017 um 17:50 geschrieben:

Add initial support for imx7ulp.

Note that we need configure power mode to Partial Stop mode 3 with system/bus clock enabled first as the default enabled STOP mode will gate off system/bus clock when execute WFI in MX7ULP SoC.

And there's still no MXC_CPU_IMX7ULP IDs read from register as ULP has no anatop as before. So we encode one with 0xff in reverse order in case new ones will be in the future.

Cc Shawn Guo <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 arch/arm/mach-imx/Kconfig        |  9 +++++++++
 arch/arm/mach-imx/Makefile       |  1 +
 arch/arm/mach-imx/common.h       |  1 +
 arch/arm/mach-imx/cpu.c          |  3 +++
 arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/mxc.h          |  1 +
 arch/arm/mach-imx/pm-imx7ulp.c   | 33 +++++++++++++++++++++++++++++++++
 7 files changed, 85 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
 create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c

arch/arm/mach-imx/Kconfig +9 -0

index 936c59d..a07081d 100644
@@ -553,6 +553,15 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
 
 if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
 
+config SOC_IMX7ULP
+	bool "i.MX7ULP support"
+	select ARM_GIC
+	select CLKSRC_IMX_TPM
+	select HAVE_ARM_ARCH_TIMER
+	select PINCTRL_IMX7ULP
+	help
+	  This enables support for Freescale i.MX7 Ultra Low Power processor.
+
 config SOC_VF610
 	bool "Vybrid Family VF610 support"
 	select ARM_GIC if ARCH_MULTI_V7

arch/arm/mach-imx/Makefile +1 -0

index cab1289..c5948b7 100644
@@ -80,6 +80,7 @@ obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
 obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
 obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
 obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
 
 ifeq ($(CONFIG_SUSPEND),y)
 AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a

arch/arm/mach-imx/common.h +1 -0

index b09a2ec..b0e85df 100644
@@ -128,6 +128,7 @@ void imx6dl_pm_init(void);
 void imx6sl_pm_init(void);
 void imx6sx_pm_init(void);
 void imx6ul_pm_init(void);
+void imx7ulp_pm_init(void);
 
 #ifdef CONFIG_PM
 void imx51_pm_init(void);

arch/arm/mach-imx/cpu.c +3 -0

index b3347d3..3867e7f 100644
@@ -134,6 +134,9 @@ struct device * __init imx_soc_device_init(void)
 	case MXC_CPU_IMX7D:
 		soc_id = "i.MX7D";
 		break;
+	case MXC_CPU_IMX7ULP:
+		soc_id = "i.MX7ULP";
+		break;
 	default:
 		soc_id = "Unknown";
 	}

arch/arm/mach-imx/mach-imx7ulp.c new file +37 -0

new file mode 100644
index 0000000..9f7a25c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+#include "hardware.h"
+
+static void __init imx7ulp_init_machine(void)
+{
+	imx7ulp_pm_init();
+
+	mxc_set_cpu_type(MXC_CPU_IMX7ULP);
+	imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_1_0);
+	of_platform_default_populate(NULL, NULL, imx_soc_device_init());
+}
+
+static const char *const imx7ulp_dt_compat[] __initconst = {
+	"fsl,imx7ulp",
+	NULL,
+};
+
+DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
+	.init_machine	= imx7ulp_init_machine,
+	.dt_compat	= imx7ulp_dt_compat,
+MACHINE_END

arch/arm/mach-imx/mxc.h +1 -0

index 34f2ff6..3dfb09c 100644
@@ -40,6 +40,7 @@
 #define MXC_CPU_IMX6Q		0x63
 #define MXC_CPU_IMX6UL		0x64
 #define MXC_CPU_IMX7D		0x72
+#define MXC_CPU_IMX7ULP		0xff
 
 #define IMX_DDR_TYPE_LPDDR2		1

arch/arm/mach-imx/pm-imx7ulp.c new file +16 -0

new file mode 100644
index 0000000..df5d6b6
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+

arch/arm/mach-imx/pm-imx7ulp.c line 26

Quoted 10 lines

arch/arm/mach-imx/pm-imx7ulp.c new file +10 -0

+#define SMC_PMCTRL		0x10
+#define BP_PMCTRL_PSTOPO        16
+#define PSTOPO_PSTOP3		0x3
+
+void __init imx7ulp_pm_init(void)
+{
+	struct device_node *np;
+	void __iomem *smc1_base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");

so actually there no dt-binding for this compatible, because there is no driver?

Dong Aisheng

2017-05-18 05:30 UTC #5 lore raw

PATCH 2/4 ARM: imx: add initial support for imx7ulp

Quoted 168 lines · Stefan Wahren

Hi Dong,

Quoted 166 lines

Dong Aisheng <[email protected]> hat am 17. Mai 2017 um 17:50 geschrieben:

Add initial support for imx7ulp.

Note that we need configure power mode to Partial Stop mode 3 with system/bus clock enabled first as the default enabled STOP mode will gate off system/bus clock when execute WFI in MX7ULP SoC.

And there's still no MXC_CPU_IMX7ULP IDs read from register as ULP has no anatop as before. So we encode one with 0xff in reverse order in case new ones will be in the future.

Cc Shawn Guo <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 arch/arm/mach-imx/Kconfig        |  9 +++++++++
 arch/arm/mach-imx/Makefile       |  1 +
 arch/arm/mach-imx/common.h       |  1 +
 arch/arm/mach-imx/cpu.c          |  3 +++
 arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/mxc.h          |  1 +
 arch/arm/mach-imx/pm-imx7ulp.c   | 33 +++++++++++++++++++++++++++++++++
 7 files changed, 85 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
 create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c

arch/arm/mach-imx/Kconfig +9 -0

index 936c59d..a07081d 100644
@@ -553,6 +553,15 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
 
 if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
 
+config SOC_IMX7ULP
+	bool "i.MX7ULP support"
+	select ARM_GIC
+	select CLKSRC_IMX_TPM
+	select HAVE_ARM_ARCH_TIMER
+	select PINCTRL_IMX7ULP
+	help
+	  This enables support for Freescale i.MX7 Ultra Low Power processor.
+
 config SOC_VF610
 	bool "Vybrid Family VF610 support"
 	select ARM_GIC if ARCH_MULTI_V7

arch/arm/mach-imx/Makefile +1 -0

index cab1289..c5948b7 100644
@@ -80,6 +80,7 @@ obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
 obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
 obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
 obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
 
 ifeq ($(CONFIG_SUSPEND),y)
 AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a

arch/arm/mach-imx/common.h +1 -0

index b09a2ec..b0e85df 100644
@@ -128,6 +128,7 @@ void imx6dl_pm_init(void);
 void imx6sl_pm_init(void);
 void imx6sx_pm_init(void);
 void imx6ul_pm_init(void);
+void imx7ulp_pm_init(void);
 
 #ifdef CONFIG_PM
 void imx51_pm_init(void);

arch/arm/mach-imx/cpu.c +3 -0

index b3347d3..3867e7f 100644
@@ -134,6 +134,9 @@ struct device * __init imx_soc_device_init(void)
 	case MXC_CPU_IMX7D:
 		soc_id = "i.MX7D";
 		break;
+	case MXC_CPU_IMX7ULP:
+		soc_id = "i.MX7ULP";
+		break;
 	default:
 		soc_id = "Unknown";
 	}

arch/arm/mach-imx/mach-imx7ulp.c new file +37 -0

new file mode 100644
index 0000000..9f7a25c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+#include "hardware.h"
+
+static void __init imx7ulp_init_machine(void)
+{
+	imx7ulp_pm_init();
+
+	mxc_set_cpu_type(MXC_CPU_IMX7ULP);
+	imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_1_0);
+	of_platform_default_populate(NULL, NULL, imx_soc_device_init());
+}
+
+static const char *const imx7ulp_dt_compat[] __initconst = {
+	"fsl,imx7ulp",
+	NULL,
+};
+
+DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
+	.init_machine	= imx7ulp_init_machine,
+	.dt_compat	= imx7ulp_dt_compat,
+MACHINE_END

arch/arm/mach-imx/mxc.h +1 -0

index 34f2ff6..3dfb09c 100644
@@ -40,6 +40,7 @@
 #define MXC_CPU_IMX6Q		0x63
 #define MXC_CPU_IMX6UL		0x64
 #define MXC_CPU_IMX7D		0x72
+#define MXC_CPU_IMX7ULP		0xff
 
 #define IMX_DDR_TYPE_LPDDR2		1

arch/arm/mach-imx/pm-imx7ulp.c new file +20 -0

new file mode 100644
index 0000000..df5d6b6
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SMC_PMCTRL		0x10
+#define BP_PMCTRL_PSTOPO        16
+#define PSTOPO_PSTOP3		0x3
+

Quoted 8 lines

arch/arm/mach-imx/pm-imx7ulp.c line 26
Quoted 6 lines
arch/arm/mach-imx/pm-imx7ulp.c new file +6 -0
+void __init imx7ulp_pm_init(void)
+{
+	struct device_node *np;
+	void __iomem *smc1_base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
so actually there no dt-binding for this compatible, because there is no driver?

Yes, probably we'd better add another binding doc for it under Documentation/devicetree/bindings/arm/freescale/.
And there's another fsl,aips-bus also has no binding doc, i'm not sure whether we need add a binding doc it as well. It seems already exist on many imx dts files.

Shawn,
your suggestion?

Regards
Dong Aisheng

Shawn Guo

2017-05-21 07:05 UTC #6 lore raw

PATCH 2/4 ARM: imx: add initial support for imx7ulp

Quoted 35 lines · Dong Aisheng

Quoted 26 lines

arch/arm/mach-imx/pm-imx7ulp.c new file +20 -0

new file mode 100644
index 0000000..df5d6b6
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SMC_PMCTRL		0x10
+#define BP_PMCTRL_PSTOPO        16
+#define PSTOPO_PSTOP3		0x3
+

Quoted 8 lines

arch/arm/mach-imx/pm-imx7ulp.c line 26
Quoted 6 lines
arch/arm/mach-imx/pm-imx7ulp.c new file +6 -0
+void __init imx7ulp_pm_init(void)
+{
+	struct device_node *np;
+	void __iomem *smc1_base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
so actually there no dt-binding for this compatible, because there is no driver?

Quoted 8 lines

Yes, probably we'd better add another binding doc for it under Documentation/devicetree/bindings/arm/freescale/.
And there's another fsl,aips-bus also has no binding doc, i'm not sure whether we need add a binding doc it as well. It seems already exist on many imx dts files.
Shawn,
your suggestion?

Strictly speaking, every compatible should be documented. But in reality, some compatibles not used by kernel may be missing the documentation. You're welcomed to add them.

Shawn

Dong Aisheng

author

2017-05-17 15:50 UTC #7 lore raw

PATCH 3/4 dts: imx: add imx7ulp evk support

In reply to Dong Aisheng

It includes the following support:
1) CLK
2) GPIO PTC, PTD, PTE, PTF
3) uSDHC 1/2
4) LPUART 4/5/6/7
5) LPI2C 6/7

Signed-off-by Anson Huang <[email protected]>

Signed-off-by Bai Ping <[email protected]>

Signed-off-by Fugang Duan <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 arch/arm/boot/dts/Makefile        |   2 +
 arch/arm/boot/dts/imx7ulp-evk.dts |  98 ++++++++++++
 arch/arm/boot/dts/imx7ulp.dtsi    | 310 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 410 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi

arch/arm/boot/dts/Makefile +2 -0

index 0bff8e7..d4bf4fa 100644
@@ -470,6 +470,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-sdb-sht11.dtb \
 	imx7s-colibri-eval-v3.dtb \
 	imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+	imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-qds.dtb \
 	ls1021a-twr.dtb

arch/arm/boot/dts/imx7ulp-evk.dts new file +98 -0

98 lines not on this page · raw message

arch/arm/boot/dts/imx7ulp.dtsi new file +310 -0

310 lines not on this page · raw message

Signature · 1 line

2.7.4

Stefan Wahren

2017-05-17 17:46 UTC #8 lore raw

PATCH 3/4 dts: imx: add imx7ulp evk support

Hi Dong,

Quoted 148 lines

Dong Aisheng <[email protected]> hat am 17. Mai 2017 um 17:50 geschrieben:

It includes the following support:
1) CLK
2) GPIO PTC, PTD, PTE, PTF
3) uSDHC 1/2
4) LPUART 4/5/6/7
5) LPI2C 6/7

Signed-off-by Anson Huang <[email protected]>

Signed-off-by Bai Ping <[email protected]>

Signed-off-by Fugang Duan <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 arch/arm/boot/dts/Makefile        |   2 +
 arch/arm/boot/dts/imx7ulp-evk.dts |  98 ++++++++++++
 arch/arm/boot/dts/imx7ulp.dtsi    | 310 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 410 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi

arch/arm/boot/dts/Makefile +2 -0

index 0bff8e7..d4bf4fa 100644
@@ -470,6 +470,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-sdb-sht11.dtb \
 	imx7s-colibri-eval-v3.dtb \
 	imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+	imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-qds.dtb \
 	ls1021a-twr.dtb

arch/arm/boot/dts/imx7ulp-evk.dts new file +98 -0

new file mode 100644
index 0000000..ec8790d
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP EVK";
+	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		stdout-path = &lpuart4;
+	};
+
+	memory {
+		reg = <0x60000000 0x40000000>;
+	};
+
+	reg_vsd_3v3: regulator-vsd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc0_rst>;
+		gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&lpuart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>,
+		    <&pinctrl_usdhc0_cd>;
+	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_vsd_3v3>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_lpuart4: lpuart4grp {
+		pins = <
+			ULP1_PAD_PTC3__LPUART4_RX
+			ULP1_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_cmd_data: usdhc0_cmd_data_0_3_grp {
+		pins = <
+			ULP1_PAD_PTD1__SDHC0_CMD
+			ULP1_PAD_PTD2__SDHC0_CLK
+			ULP1_PAD_PTD7__SDHC0_D3
+			ULP1_PAD_PTD8__SDHC0_D2
+			ULP1_PAD_PTD9__SDHC0_D1
+			ULP1_PAD_PTD10__SDHC0_D0
+		>;
+		drive-strength = <1>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_clk: usdhc0_clk_grp {
+		pins = <
+			ULP1_PAD_PTD2__SDHC0_CLK
+		>;
+		drive-strength = <1>;
+		bias-pull-down;
+	};
+
+	pinctrl_usdhc0_cd: usdhc0_gpios_cd_grp {
+		pins = <
+			ULP1_PAD_PTC10__PTC10		/* USDHC0 CD */
+		>;
+		nxp,input-buffer-enable;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_rst: usdhc0_gpios_rst_grp {
+		pins = <
+			ULP1_PAD_PTD0__PTD0		/* USDHC0 RST */
+		>;
+		nxp,output-buffer-enable;
+		bias-pull-up;
+	};
+};

arch/arm/boot/dts/imx7ulp.dtsi new file +3 -0

new file mode 100644
index 0000000..514e063
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc
+ * Copyright 2017 NXP

arch/arm/boot/dts/imx7ulp.dtsi line 13

Quoted 10 lines

arch/arm/boot/dts/imx7ulp.dtsi new file +10 -0

+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"

AFAIK this dtsi shouldn't be included from new dts files.

Quoted 20 lines

arch/arm/boot/dts/imx7ulp.dtsi new file +20 -0

+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	aliases {
+		gpio0 = &gpio_ptc;
+		gpio1 = &gpio_ptd;
+		gpio2 = &gpio_pte;
+		gpio3 = &gpio_ptf;
+		i2c0 = &lpi2c6;
+		i2c1 = &lpi2c7;
+		mmc0 = &usdhc0;
+		mmc1 = &usdhc1;
+		serial0 = &lpuart4;
+		serial1 = &lpuart5;
+		serial2 = &lpuart6;
+		serial3 = &lpuart7;
+	};

arch/arm/boot/dts/imx7ulp.dtsi line 43

Quoted 10 lines

arch/arm/boot/dts/imx7ulp.dtsi new file +10 -0

+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};

I'm not sure, but describing the hardware requires to add the second core.

Stefan

Dong Aisheng

2017-05-18 05:35 UTC #9 lore raw

PATCH 3/4 dts: imx: add imx7ulp evk support

Quoted 154 lines · Stefan Wahren

Hi Dong,

Quoted 152 lines

Dong Aisheng <[email protected]> hat am 17. Mai 2017 um 17:50 geschrieben:

It includes the following support:
1) CLK
2) GPIO PTC, PTD, PTE, PTF
3) uSDHC 1/2
4) LPUART 4/5/6/7
5) LPI2C 6/7

Signed-off-by Anson Huang <[email protected]>

Signed-off-by Bai Ping <[email protected]>

Signed-off-by Fugang Duan <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 arch/arm/boot/dts/Makefile        |   2 +
 arch/arm/boot/dts/imx7ulp-evk.dts |  98 ++++++++++++
 arch/arm/boot/dts/imx7ulp.dtsi    | 310 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 410 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi

arch/arm/boot/dts/Makefile +2 -0

index 0bff8e7..d4bf4fa 100644
@@ -470,6 +470,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-sdb-sht11.dtb \
 	imx7s-colibri-eval-v3.dtb \
 	imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+	imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-qds.dtb \
 	ls1021a-twr.dtb

arch/arm/boot/dts/imx7ulp-evk.dts new file +98 -0

new file mode 100644
index 0000000..ec8790d
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP EVK";
+	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		stdout-path = &lpuart4;
+	};
+
+	memory {
+		reg = <0x60000000 0x40000000>;
+	};
+
+	reg_vsd_3v3: regulator-vsd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc0_rst>;
+		gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&lpuart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>,
+		    <&pinctrl_usdhc0_cd>;
+	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_vsd_3v3>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_lpuart4: lpuart4grp {
+		pins = <
+			ULP1_PAD_PTC3__LPUART4_RX
+			ULP1_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_cmd_data: usdhc0_cmd_data_0_3_grp {
+		pins = <
+			ULP1_PAD_PTD1__SDHC0_CMD
+			ULP1_PAD_PTD2__SDHC0_CLK
+			ULP1_PAD_PTD7__SDHC0_D3
+			ULP1_PAD_PTD8__SDHC0_D2
+			ULP1_PAD_PTD9__SDHC0_D1
+			ULP1_PAD_PTD10__SDHC0_D0
+		>;
+		drive-strength = <1>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_clk: usdhc0_clk_grp {
+		pins = <
+			ULP1_PAD_PTD2__SDHC0_CLK
+		>;
+		drive-strength = <1>;
+		bias-pull-down;
+	};
+
+	pinctrl_usdhc0_cd: usdhc0_gpios_cd_grp {
+		pins = <
+			ULP1_PAD_PTC10__PTC10		/* USDHC0 CD */
+		>;
+		nxp,input-buffer-enable;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_rst: usdhc0_gpios_rst_grp {
+		pins = <
+			ULP1_PAD_PTD0__PTD0		/* USDHC0 RST */
+		>;
+		nxp,output-buffer-enable;
+		bias-pull-up;
+	};
+};

arch/arm/boot/dts/imx7ulp.dtsi new file +7 -0

new file mode 100644
index 0000000..514e063
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.

Quoted 9 lines

arch/arm/boot/dts/imx7ulp.dtsi line 13
Quoted 6 lines
arch/arm/boot/dts/imx7ulp.dtsi new file +6 -0
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
AFAIK this dtsi shouldn't be included from new dts files.

Missed it, thanks for reminder.

Quoted 24 lines

arch/arm/boot/dts/imx7ulp.dtsi new file +24 -0

+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	aliases {
+		gpio0 = &gpio_ptc;
+		gpio1 = &gpio_ptd;
+		gpio2 = &gpio_pte;
+		gpio3 = &gpio_ptf;
+		i2c0 = &lpi2c6;
+		i2c1 = &lpi2c7;
+		mmc0 = &usdhc0;
+		mmc1 = &usdhc1;
+		serial0 = &lpuart4;
+		serial1 = &lpuart5;
+		serial2 = &lpuart6;
+		serial3 = &lpuart7;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;

Quoted 9 lines

arch/arm/boot/dts/imx7ulp.dtsi line 43
Quoted 6 lines
arch/arm/boot/dts/imx7ulp.dtsi new file +6 -0
+
+		cpu0: cpu at 0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
I'm not sure, but describing the hardware requires to add the second core.

Not quite understand, it looks already fully comply with the standard bindings:
Documentation/devicetree/bindings/arm/cpus.txt

Or your mean the following ones?

Regards
Dong Aisheng

Stefan Wahren

2017-05-18 05:42 UTC #10 lore raw

PATCH 3/4 dts: imx: add imx7ulp evk support

Quoted 205 lines

Dong Aisheng <[email protected]> hat am 18. Mai 2017 um 07:35 geschrieben:

Quoted 154 lines · Stefan Wahren

Hi Dong,

Quoted 152 lines

Dong Aisheng <[email protected]> hat am 17. Mai 2017 um 17:50 geschrieben:

It includes the following support:
1) CLK
2) GPIO PTC, PTD, PTE, PTF
3) uSDHC 1/2
4) LPUART 4/5/6/7
5) LPI2C 6/7

Signed-off-by Anson Huang <[email protected]>

Signed-off-by Bai Ping <[email protected]>

Signed-off-by Fugang Duan <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
 arch/arm/boot/dts/Makefile        |   2 +
 arch/arm/boot/dts/imx7ulp-evk.dts |  98 ++++++++++++
 arch/arm/boot/dts/imx7ulp.dtsi    | 310 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 410 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi

arch/arm/boot/dts/Makefile +2 -0

index 0bff8e7..d4bf4fa 100644
@@ -470,6 +470,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-sdb-sht11.dtb \
 	imx7s-colibri-eval-v3.dtb \
 	imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+	imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-qds.dtb \
 	ls1021a-twr.dtb

arch/arm/boot/dts/imx7ulp-evk.dts new file +98 -0

new file mode 100644
index 0000000..ec8790d
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP EVK";
+	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		stdout-path = &lpuart4;
+	};
+
+	memory {
+		reg = <0x60000000 0x40000000>;
+	};
+
+	reg_vsd_3v3: regulator-vsd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc0_rst>;
+		gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&lpuart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>,
+		    <&pinctrl_usdhc0_cd>;
+	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_vsd_3v3>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_lpuart4: lpuart4grp {
+		pins = <
+			ULP1_PAD_PTC3__LPUART4_RX
+			ULP1_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_cmd_data: usdhc0_cmd_data_0_3_grp {
+		pins = <
+			ULP1_PAD_PTD1__SDHC0_CMD
+			ULP1_PAD_PTD2__SDHC0_CLK
+			ULP1_PAD_PTD7__SDHC0_D3
+			ULP1_PAD_PTD8__SDHC0_D2
+			ULP1_PAD_PTD9__SDHC0_D1
+			ULP1_PAD_PTD10__SDHC0_D0
+		>;
+		drive-strength = <1>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_clk: usdhc0_clk_grp {
+		pins = <
+			ULP1_PAD_PTD2__SDHC0_CLK
+		>;
+		drive-strength = <1>;
+		bias-pull-down;
+	};
+
+	pinctrl_usdhc0_cd: usdhc0_gpios_cd_grp {
+		pins = <
+			ULP1_PAD_PTC10__PTC10		/* USDHC0 CD */
+		>;
+		nxp,input-buffer-enable;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_rst: usdhc0_gpios_rst_grp {
+		pins = <
+			ULP1_PAD_PTD0__PTD0		/* USDHC0 RST */
+		>;
+		nxp,output-buffer-enable;
+		bias-pull-up;
+	};
+};

arch/arm/boot/dts/imx7ulp.dtsi new file +7 -0

new file mode 100644
index 0000000..514e063
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.

Quoted 9 lines

arch/arm/boot/dts/imx7ulp.dtsi line 13
Quoted 6 lines
arch/arm/boot/dts/imx7ulp.dtsi new file +6 -0
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
AFAIK this dtsi shouldn't be included from new dts files.

Missed it, thanks for reminder.

Quoted 24 lines

arch/arm/boot/dts/imx7ulp.dtsi new file +24 -0

+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	aliases {
+		gpio0 = &gpio_ptc;
+		gpio1 = &gpio_ptd;
+		gpio2 = &gpio_pte;
+		gpio3 = &gpio_ptf;
+		i2c0 = &lpi2c6;
+		i2c1 = &lpi2c7;
+		mmc0 = &usdhc0;
+		mmc1 = &usdhc1;
+		serial0 = &lpuart4;
+		serial1 = &lpuart5;
+		serial2 = &lpuart6;
+		serial3 = &lpuart7;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;

Quoted 9 lines

arch/arm/boot/dts/imx7ulp.dtsi line 43
Quoted 6 lines
arch/arm/boot/dts/imx7ulp.dtsi new file +6 -0
+
+		cpu0: cpu at 0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
I'm not sure, but describing the hardware requires to add the second core.

Quoted 4 lines

Not quite understand, it looks already fully comply with the standard bindings:
Documentation/devicetree/bindings/arm/cpus.txt
Or your mean the following ones?

The dts should describe the hardware. So i think this is missing:

cpu1: cpu at 1 {
        compatible = "arm,cortex-m4";
        device_type = "cpu";
        reg = <1>;
};

Quoted 3 lines

Regards
Dong Aisheng

A.S. Dong

author

2017-05-18 05:48 UTC #11 lore raw

PATCH 3/4 dts: imx: add imx7ulp evk support

Quoted 230 lines

-----Original Message-----
From: Stefan Wahren [mailto:stefan.wahren at i2se.com]
Sent: Thursday, May 18, 2017 1:42 PM
To: Dong Aisheng
Cc: Andy Duan; kernel at pengutronix.de; shawnguo at kernel.org; A.S. Dong; linux-arm-kernel at lists.infradead.org; Jacky Bai; Anson Huang
Subject: Re: [PATCH 3/4] dts: imx: add imx7ulp evk support
Quoted 1 line
Dong Aisheng <[email protected]> hat am 18. Mai 2017 um 07:35
geschrieben:
Quoted 6 lines · Stefan Wahren
Quoted 3 lines
Hi Dong,
Quoted 1 line
Dong Aisheng <[email protected]> hat am 17. Mai 2017 um 17:50
geschrieben:
Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
It includes the following support:
1) CLK
2) GPIO PTC, PTD, PTE, PTF
3) uSDHC 1/2
4) LPUART 4/5/6/7
5) LPI2C 6/7
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Signed-off-by Anson Huang <[email protected]>
Signed-off-by Bai Ping <[email protected]>
Signed-off-by Fugang Duan <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
 arch/arm/boot/dts/Makefile        |   2 +
 arch/arm/boot/dts/imx7ulp-evk.dts |  98 ++++++++++++
 arch/arm/boot/dts/imx7ulp.dtsi    | 310
++++++++++++++++++++++++++++++++++++++
Quoted 34 lines
Quoted 34 lines
Quoted 34 lines
 3 files changed, 410 insertions(+)  create mode 100644
arch/arm/boot/dts/imx7ulp-evk.dts create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
(quoted diff) +0 -0
b/arch/arm/boot/dts/Makefile index 0bff8e7..d4bf4fa 100644
arch/arm/boot/dts/Makefile +2 -0
@@ -470,6 +470,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-sdb-sht11.dtb \
 	imx7s-colibri-eval-v3.dtb \
 	imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+	imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-qds.dtb \
 	ls1021a-twr.dtb
arch/arm/boot/dts/imx7ulp-evk.dts new file +10 -0
new file mode 100644
index 0000000..ec8790d
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+modify
+ * it under the terms of the GNU General Public License version 2
+as
+ * published by the Free Software Foundation.
+ */
Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/imx7ulp-evk.dts
Quoted 8 lines
arch/arm/boot/dts/imx7ulp-evk.dts new file +8 -0
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP EVK";
+	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT
based
Quoted 108 lines
Quoted 98 lines
Quoted 98 lines
arch/arm/boot/dts/imx7ulp-evk.dts new file +83 -0
+system";
+
+	chosen {
+		stdout-path = &lpuart4;
+	};
+
+	memory {
+		reg = <0x60000000 0x40000000>;
+	};
+
+	reg_vsd_3v3: regulator-vsd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc0_rst>;
+		gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&lpuart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>,
+		    <&pinctrl_usdhc0_cd>;
+	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_vsd_3v3>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_lpuart4: lpuart4grp {
+		pins = <
+			ULP1_PAD_PTC3__LPUART4_RX
+			ULP1_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_cmd_data: usdhc0_cmd_data_0_3_grp {
+		pins = <
+			ULP1_PAD_PTD1__SDHC0_CMD
+			ULP1_PAD_PTD2__SDHC0_CLK
+			ULP1_PAD_PTD7__SDHC0_D3
+			ULP1_PAD_PTD8__SDHC0_D2
+			ULP1_PAD_PTD9__SDHC0_D1
+			ULP1_PAD_PTD10__SDHC0_D0
+		>;
+		drive-strength = <1>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_clk: usdhc0_clk_grp {
+		pins = <
+			ULP1_PAD_PTD2__SDHC0_CLK
+		>;
+		drive-strength = <1>;
+		bias-pull-down;
+	};
+
+	pinctrl_usdhc0_cd: usdhc0_gpios_cd_grp {
+		pins = <
+			ULP1_PAD_PTC10__PTC10		/* USDHC0 CD */
+		>;
+		nxp,input-buffer-enable;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_rst: usdhc0_gpios_rst_grp {
+		pins = <
+			ULP1_PAD_PTD0__PTD0		/* USDHC0 RST */
+		>;
+		nxp,output-buffer-enable;
+		bias-pull-up;
+	};
+};
(quoted diff) +0 -0
b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index 0000000..514e063
arch/arm/boot/dts/imx7ulp.dtsi new file +9 -0
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+modify
+ * it under the terms of the GNU General Public License version 2
+as
+ * published by the Free Software Foundation.
Quoted 9 lines
arch/arm/boot/dts/imx7ulp.dtsi line 13
Quoted 6 lines
arch/arm/boot/dts/imx7ulp.dtsi new file +6 -0
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/gpio/gpio.h> #include
+<dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
AFAIK this dtsi shouldn't be included from new dts files.
Quoted 34 lines
Missed it, thanks for reminder.
Quoted 32 lines
Quoted 20 lines
arch/arm/boot/dts/imx7ulp.dtsi new file +20 -0
+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	aliases {
+		gpio0 = &gpio_ptc;
+		gpio1 = &gpio_ptd;
+		gpio2 = &gpio_pte;
+		gpio3 = &gpio_ptf;
+		i2c0 = &lpi2c6;
+		i2c1 = &lpi2c7;
+		mmc0 = &usdhc0;
+		mmc1 = &usdhc1;
+		serial0 = &lpuart4;
+		serial1 = &lpuart5;
+		serial2 = &lpuart6;
+		serial3 = &lpuart7;
+	};
arch/arm/boot/dts/imx7ulp.dtsi line 43
Quoted 10 lines
arch/arm/boot/dts/imx7ulp.dtsi new file +10 -0
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
I'm not sure, but describing the hardware requires to add the second
core.
Quoted 3 lines
Quoted 1 line
Not quite understand, it looks already fully comply with the standard
bindings:
Quoted 3 lines
Documentation/devicetree/bindings/arm/cpus.txt
Or your mean the following ones?

Quoted 8 lines

The dts should describe the hardware. So i think this is missing:
cpu1: cpu at 1 {
        compatible = "arm,cortex-m4";
        device_type = "cpu";
        reg = <1>;
};

Okay, understand,
Now the point is we only want to add A7 domain peripherals in device tree currently, still no plan to add M4 domain as M4 is run a separate RTOS and will handle M4 resources separately.

I guess we would still save them first.

Regards
Dong Aisheng

Dong Aisheng

author

2017-05-17 15:50 UTC #12 lore raw

PATCH 4/4 ARM: imx_v6_v7_defconfig: add imx7ulp support

In reply to Dong Aisheng

Select CONFIG_SOC_IMX7ULP by default.
Patch generated via make ARCH=arm savedefconfig

Cc Shawn Guo <[email protected]>

Signed-off-by Dong Aisheng <[email protected]>

---
The patch involves below config changes with savedefconfig. CONFIG_TOUCHSCREEN_MAX11801=y CONFIG_HID_MULTITOUCH=y

---
 arch/arm/configs/imx_v6_v7_defconfig | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

arch/arm/configs/imx_v6_v7_defconfig +3 -2

index bb6fa56..8f55e4f 100644
@@ -41,6 +41,7 @@ CONFIG_SOC_IMX6SL=y
 CONFIG_SOC_IMX6SX=y
 CONFIG_SOC_IMX6UL=y
 CONFIG_SOC_IMX7D=y
+CONFIG_SOC_IMX7ULP=y
 CONFIG_SOC_VF610=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y

@@ -163,9 +164,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
 CONFIG_TOUCHSCREEN_EGALAX=y
+CONFIG_TOUCHSCREEN_MAX11801=y
 CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
 CONFIG_TOUCHSCREEN_EDT_FT5X06=y
-CONFIG_TOUCHSCREEN_MAX11801=y
 CONFIG_TOUCHSCREEN_MC13783=y
 CONFIG_TOUCHSCREEN_TSC2004=y
 CONFIG_TOUCHSCREEN_TSC2007=y

@@ -174,7 +175,6 @@ CONFIG_TOUCHSCREEN_SX8654=y
 CONFIG_TOUCHSCREEN_COLIBRI_VF50=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MMA8450=y
-CONFIG_HID_MULTITOUCH=y
 CONFIG_SERIO_SERPORT=m
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_IMX=y

@@ -268,6 +268,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=y
 CONFIG_SND_SOC_TLV320AIC3X=y
 CONFIG_SND_SOC_WM8960=y
 CONFIG_SND_SIMPLE_CARD=y
+CONFIG_HID_MULTITOUCH=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y

Signature · 1 line

2.7.4