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pinctrl: imx: add generic pin config and imx7ulp support

PATCH Superseded Dong Aisheng 4 participants 26 messages May 19, 2017 – May 25, 2017

Subsystems (5)
Device tree bindings Arm i.MX and Layerscape GPIO Pin control +1 more subsystems
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Dong Aisheng

author maintainer
#0 lore raw

v2 cover pinctrl: imx: add generic pin config and imx7ulp support

This patch series intends to add the generic pin config support for imx platforms.

The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform.

Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently.

In order to cope with some special case, a platform specific fixup() function is also available to use.

The series also added the imx7ulp pinctrl support which only supports generic pin config.

ChangeLog:
v1->v2:
Minor changes including:
* comments/commit messages improvement
* add more descriptions in binding doc
* move dt-bindings/pinctrl/imx7ulp-pinfunc.h to arch/arm/boot/dts See individual for details.
* Patch 5 moved to patch 1 in new series

Dong Aisheng (5):
pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case
pinctrl: imx: add generic pin config core support
pinctrl: imx: add soc specific mux_mode mask and shift property
dt-bindings: pinctrl: add imx7ulp pinctrl binding doc
pinctrl: imx: add imx7ulp driver

 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  63 +++
 arch/arm/boot/dts/imx7ulp-pinfunc.h                | 468 +++++++++++++++++++++
 drivers/pinctrl/freescale/Kconfig                  |   9 +-
 drivers/pinctrl/freescale/Makefile                 |   1 +
 drivers/pinctrl/freescale/pinctrl-imx.c            | 130 +++++-
 drivers/pinctrl/freescale/pinctrl-imx.h            |  29 ++
 drivers/pinctrl/freescale/pinctrl-imx7ulp.c        | 358 ++++++++++++++++
 drivers/pinctrl/freescale/pinctrl-vf610.c          |   2 +
 8 files changed, 1040 insertions(+), 20 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/imx7ulp-pinfunc.h
 create mode 100644 drivers/pinctrl/freescale/pinctrl-imx7ulp.c
Signature · 1 line
2.7.4
author maintainer
#1 lore raw

PATCH v2 1/5 pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case

The original implemented debug message does not work for SHARE_MUX_CONF_REG case. This patch fixes it.

Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Fixes bf5a530971af ("pinctrl: imx: add VF610 support to imx pinctrl framework")
Signed-off-by Dong Aisheng <[email protected]>

---
* no changes

---
 drivers/pinctrl/freescale/pinctrl-imx.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)
drivers/pinctrl/freescale/pinctrl-imx.c +8 -4
index a7ace9e..6882644 100644
@@ -199,11 +199,13 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 			reg &= ~(0x7 << 20);
 			reg |= (pin->mux_mode << 20);
 			writel(reg, ipctl->base + pin_reg->mux_reg);
+			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+				pin_reg->mux_reg, reg);
 		} else {
 			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
+			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+				pin_reg->mux_reg, pin->mux_mode);
 		}
-		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
-			pin_reg->mux_reg, pin->mux_mode);
 
 		/*
 		 * If the select input value begins with 0xff, it's a quirky

@@ -405,11 +407,13 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 			reg &= ~0xffff;
 			reg |= configs[i];
 			writel(reg, ipctl->base + pin_reg->conf_reg);
+			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+				pin_reg->conf_reg, reg);
 		} else {
 			writel(configs[i], ipctl->base + pin_reg->conf_reg);
+			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
+				pin_reg->conf_reg, configs[i]);
 		}
-		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
-			pin_reg->conf_reg, configs[i]);
 	} /* for each config */
 
 	return 0;
Signature · 1 line
2.7.4
#3 lore raw

PATCH v2 1/5 pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case

In reply to Dong Aisheng
Quoted 7 lines · Dong Aisheng

The original implemented debug message does not work for SHARE_MUX_CONF_REG case. This patch fixes it.

Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Fixes bf5a530971af ("pinctrl: imx: add VF610 support to imx pinctrl framework")
Signed-off-by Dong Aisheng <[email protected]>

Patch applied with Shawn's ACK.

Yours,
Linus Walleij

author maintainer
#4 lore raw

PATCH v2 2/5 pinctrl: imx: add generic pin config core support

In reply to Dong Aisheng

The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform.

Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently.

In order to cope with some special case, a platform specific fixup() function is also available to use.

Note that rather than fully utilizing the generic pinconf support provided by pinctrl core, IMX only adopts the device tree bindings of generic pinconf. The config used in .pin_config_get[set] are raw register data instead of generic one which makes us align the exist using. And that's also why we cannot set pinconf_ops.is_generic.

Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---
ChangeLog:
v1->v2:
Minor changes including:
* rename 'offset' field to 'shift' in structure imx_cfg_params_decode
* comments improvement
* add more clearer information about imx generic pin config in commmit message.

---
 drivers/pinctrl/freescale/Kconfig       |   2 +-
 drivers/pinctrl/freescale/pinctrl-imx.c | 108 +++++++++++++++++++++++++++++---
 drivers/pinctrl/freescale/pinctrl-imx.h |  25 ++++++++
 3 files changed, 124 insertions(+), 11 deletions(-)
drivers/pinctrl/freescale/Kconfig +1 -1
index cae05e7..0b266b2 100644
@@ -2,7 +2,7 @@ config PINCTRL_IMX
 	bool
 	select GENERIC_PINCTRL_GROUPS
 	select GENERIC_PINMUX_FUNCTIONS
-	select PINCONF
+	select GENERIC_PINCONF
 	select REGMAP
 
 config PINCTRL_IMX1_CORE
drivers/pinctrl/freescale/pinctrl-imx.c +98 -10

168 lines not on this page · raw message

drivers/pinctrl/freescale/pinctrl-imx.h +25 -0
index ff2d3e5..38aa53c 100644
@@ -15,6 +15,8 @@
 #ifndef __DRIVERS_PINCTRL_IMX_H
 #define __DRIVERS_PINCTRL_IMX_H
 
+#include <linux/pinctrl/pinconf-generic.h>
+
 struct platform_device;
 
 /**

@@ -44,6 +46,14 @@ struct imx_pin_reg {
 	s16 conf_reg;
 };
 
+/* decode a generic config into raw register value */
+struct imx_cfg_params_decode {
+	enum pin_config_param param;
+	u32 mask;
+	u8 shift;
+	bool invert;
+};
+
 struct imx_pinctrl_soc_info {
 	struct device *dev;
 	const struct pinctrl_pin_desc *pins;

@@ -53,8 +63,23 @@ struct imx_pinctrl_soc_info {
 	unsigned int flags;
 	const char *gpr_compatible;
 	struct mutex mutex;
+
+	/* generic pinconf */
+	bool generic_pinconf;
+	const struct pinconf_generic_params *custom_params;
+	unsigned int num_custom_params;
+	struct imx_cfg_params_decode *decodes;
+	unsigned int num_decodes;
+	void (*fixup)(unsigned long *configs, unsigned int num_configs,
+		      u32 *raw_config);
 };
 
+#define IMX_CFG_PARAMS_DECODE(p, m, o) \
+	{ .param = p, .mask = m, .shift = o, .invert = false, }
+
+#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
+	{ .param = p, .mask = m, .shift = o, .invert = true, }
+
 #define SHARE_MUX_CONF_REG	0x1
 #define ZERO_OFFSET_VALID	0x2
Signature · 1 line
2.7.4
#5 lore raw

PATCH v2 2/5 pinctrl: imx: add generic pin config core support

Quoted 17 lines · Dong Aisheng

The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform.

Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently.

In order to cope with some special case, a platform specific fixup() function is also available to use.

Note that rather than fully utilizing the generic pinconf support provided by pinctrl core, IMX only adopts the device tree bindings of generic pinconf. The config used in .pin_config_get[set] are raw register data instead of generic one which makes us align the exist using. And that's also why we cannot set pinconf_ops.is_generic.

Quoted 4 lines
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
Acked-by Shawn Guo <[email protected]>
#6 lore raw

PATCH v2 2/5 pinctrl: imx: add generic pin config core support

In reply to Dong Aisheng
Quoted 17 lines · Dong Aisheng

The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform.

Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently.

In order to cope with some special case, a platform specific fixup() function is also available to use.

Note that rather than fully utilizing the generic pinconf support provided by pinctrl core, IMX only adopts the device tree bindings of generic pinconf. The config used in .pin_config_get[set] are raw register data instead of generic one which makes us align the exist using. And that's also why we cannot set pinconf_ops.is_generic.

Quoted 4 lines
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

Patch applied with Shawn's ACK.

Yours,
Linus Walleij

author maintainer
#7 lore raw

PATCH v2 3/5 pinctrl: imx: add soc specific mux_mode mask and shift property

In reply to Dong Aisheng

MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support.

One trick in exist code that Vybrid hardcoded the config part as 0xffff because its mux_config register BIT[15-0] are all configs part. But it's not true in ULP, so use mux_mask instead to address the difference.

Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Fugang Duan <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---
ChangeLog:
v1->v2:
Minor changes:
* add more explanation about Vybrid trick in commit message.

---
 drivers/pinctrl/freescale/pinctrl-imx.c   | 10 +++++-----
 drivers/pinctrl/freescale/pinctrl-imx.h   |  4 ++++
 drivers/pinctrl/freescale/pinctrl-vf610.c |  2 ++
 3 files changed, 11 insertions(+), 5 deletions(-)
drivers/pinctrl/freescale/pinctrl-imx.c +5 -5
index 6d5a517..bb7c625 100644
@@ -197,8 +197,8 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->mux_reg);
-			reg &= ~(0x7 << 20);
-			reg |= (pin->mux_mode << 20);
+			reg &= ~info->mux_mask;
+			reg |= (pin->mux_mode << info->mux_shift);
 			writel(reg, ipctl->base + pin_reg->mux_reg);
 			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 				pin_reg->mux_reg, reg);

@@ -290,7 +290,7 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
 
 mux_pin:
 	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~(0x7 << 20);
+	reg &= ~info->mux_mask;
 	reg |= imx_pin->config;
 	writel(reg, ipctl->base + pin_reg->mux_reg);
 

@@ -434,7 +434,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 	*config = readl(ipctl->base + pin_reg->conf_reg);
 
 	if (info->flags & SHARE_MUX_CONF_REG)
-		*config &= 0xffff;
+		*config &= ~info->mux_mask;
 
 	return 0;
 }

@@ -461,7 +461,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
 			reg = readl(ipctl->base + pin_reg->conf_reg);
-			reg &= ~0xffff;
+			reg &= info->mux_mask;
 			reg |= configs[i];
 			writel(reg, ipctl->base + pin_reg->conf_reg);
 			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
drivers/pinctrl/freescale/pinctrl-imx.h +4 -0
index 38aa53c..880bba7 100644
@@ -64,6 +64,10 @@ struct imx_pinctrl_soc_info {
 	const char *gpr_compatible;
 	struct mutex mutex;
 
+	/* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
+	unsigned int mux_mask;
+	u8 mux_shift;
+
 	/* generic pinconf */
 	bool generic_pinconf;
 	const struct pinconf_generic_params *custom_params;
drivers/pinctrl/freescale/pinctrl-vf610.c +2 -0
index 2b1e198..3bd8556 100644
@@ -299,6 +299,8 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
 	.pins = vf610_pinctrl_pads,
 	.npins = ARRAY_SIZE(vf610_pinctrl_pads),
 	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+	.mux_mask = 0x700000,
+	.mux_shift = 20,
 };
 
 static const struct of_device_id vf610_pinctrl_of_match[] = {
Signature · 1 line
2.7.4
#8 lore raw

PATCH v2 3/5 pinctrl: imx: add soc specific mux_mode mask and shift property

Quoted 9 lines · Dong Aisheng

MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support.

One trick in exist code that Vybrid hardcoded the config part as 0xffff because its mux_config register BIT[15-0] are all configs part. But it's not true in ULP, so use mux_mask instead to address the difference.

Quoted 6 lines
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Fugang Duan <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
Acked-by Shawn Guo <[email protected]>
#9 lore raw

PATCH v2 3/5 pinctrl: imx: add soc specific mux_mode mask and shift property

In reply to Dong Aisheng
Quoted 16 lines · Dong Aisheng

MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support.

One trick in exist code that Vybrid hardcoded the config part as 0xffff because its mux_config register BIT[15-0] are all configs part. But it's not true in ULP, so use mux_mask instead to address the difference.

Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Fugang Duan <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
Quoted 5 lines

---
ChangeLog:
v1->v2:
Minor changes:
* add more explanation about Vybrid trick in commit message.

Patch applied with Shawn's ACK.

Yours,
Linus Walleij

author maintainer
#10 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

In reply to Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.

Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---
ChangeLog:
v1->v2:
* add more descriptions in binding doc
* add missed prefix for private properties.
* move dt-bindings/pinctrl/imx7ulp-pinfunc.h to arch/arm/boot/dts

---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  63 +++
 arch/arm/boot/dts/imx7ulp-pinfunc.h                | 468 +++++++++++++++++++++
 2 files changed, 531 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/imx7ulp-pinfunc.h
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +63 -0
new file mode 100644
index 0000000..7fbf367
@@ -0,0 +1,63 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
+ports and IOMUXC DDR for DDR interface.
+
+Note:
+This binding doc is only for the IOMUXC1 support in A7 Domain and it only
+supports generic pin config.
+
+Please also refer to fsl,imx-pinctrl.txt in this directory for IMX common
+binding part and pinctrl-bindings.txt for the generic config binding.
+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible:	"fsl,imx7ulp-iomuxc1"
+- reg:		Should contain the base physical address and size of the iomuxc
+		registers.
+
+=== Pin Configuration Node ===
+- pins: One integers array, represents a group of pins mux setting.
+	The format is fsl,pins = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
+	a specific function.
+
+	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
+	and config register as follows:
+	<mux_conf_reg input_reg mux_mode input_val>
+
+	Refer to imx7ulp-pinfunc.h in in device tree source folder for all
+	available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- nxp,output-buffer-enable:	Bool. Output buffer enabled
+- nxp,input-buffer-enable:	Bool. Input buffer enabled
+- drive-strength		Integer. Controls Drive Strength
+					0: Standard
+					1: Hi Driver
+- drive-push-pull		Bool. Enable Pin Push-pull
+- drive-open-drain		Bool. Enable Pin Open-drian
+- slew-rate:			Integer. Controls Slew Rate
+					0: Standard
+					1: Slow
+- bias-disable:			Bool. Pull disabled
+- bias-pull-down:		Bool. Pull down on pin
+- bias-pull-up:			Bool. Pull up on pin
+
+Examples:
+#include "imx7ulp-pinfunc.h"
+
+/* Pin Controller Node */
+iomuxc1: iomuxc at 40ac0000 {
+	compatible = "fsl,imx7ulp-iomuxc1";
+	reg = <0x40ac0000 0x1000>;
+
+	/* Pin Configuration Node */
+	pinctrl_lpuart4: lpuart4grp {
+		pins = <
+			ULP1_PAD_PTC3__LPUART4_RX
+			ULP1_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+};
arch/arm/boot/dts/imx7ulp-pinfunc.h new file +468 -0

468 lines not on this page · raw message

Signature · 1 line
2.7.4
#11 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 18 lines · Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.

Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---
ChangeLog:
v1->v2:
* add more descriptions in binding doc
* add missed prefix for private properties.
* move dt-bindings/pinctrl/imx7ulp-pinfunc.h to arch/arm/boot/dts

Quoted 3 lines
---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  63 +++
 arch/arm/boot/dts/imx7ulp-pinfunc.h                | 468 +++++++++++++++++++++

Rather than being part of bindings doc patch, this pinfunc header should be included in dts patches that add imx7ulp SoC support.

Shawn

Quoted 3 lines
 2 files changed, 531 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/imx7ulp-pinfunc.h
author maintainer
#12 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 33 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Sunday, May 21, 2017 5:31 PM
To: A.S. Dong
Cc: linux-gpio at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linus.walleij at linaro.org; stefan at agner.ch; Jacky Bai; Andy Duan; kernel at pengutronix.de; Rob Herring; Mark Rutland;
devicetree at vger.kernel.org
Subject: Re: [PATCH V2 4/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 18 lines · Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.

Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---
ChangeLog:
v1->v2:
* add more descriptions in binding doc
* add missed prefix for private properties.
* move dt-bindings/pinctrl/imx7ulp-pinfunc.h to arch/arm/boot/dts

Quoted 3 lines
---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  63 +++
 arch/arm/boot/dts/imx7ulp-pinfunc.h                | 468
Quoted 5 lines

+++++++++++++++++++++

Rather than being part of bindings doc patch, this pinfunc header should be included in dts patches that add imx7ulp SoC support.

Okay.
One question is that imx7ulp-pinfunc.h is mentioned in this binding doc, that means after this patch applied, users still can't see it if separate, Should we worry about this issue or not?

+ Refer to imx7ulp-pinfunc.h in in device tree source folder for all
+ available imx7ulp PIN_FUNC_ID.

Last, thx for other ACKs.

Regards
Dong Aisheng

Quoted 6 lines

Shawn

Quoted 4 lines
 2 files changed, 531 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/imx7ulp-pinfunc.h
#13 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 44 lines · A.S. Dong
Quoted 33 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Sunday, May 21, 2017 5:31 PM
To: A.S. Dong
Cc: linux-gpio at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linus.walleij at linaro.org; stefan at agner.ch; Jacky Bai; Andy Duan; kernel at pengutronix.de; Rob Herring; Mark Rutland;
devicetree at vger.kernel.org
Subject: Re: [PATCH V2 4/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 18 lines · Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.

Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---
ChangeLog:
v1->v2:
* add more descriptions in binding doc
* add missed prefix for private properties.
* move dt-bindings/pinctrl/imx7ulp-pinfunc.h to arch/arm/boot/dts

Quoted 3 lines
---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  63 +++
 arch/arm/boot/dts/imx7ulp-pinfunc.h                | 468
Quoted 5 lines

+++++++++++++++++++++

Rather than being part of bindings doc patch, this pinfunc header should be included in dts patches that add imx7ulp SoC support.

Okay.
One question is that imx7ulp-pinfunc.h is mentioned in this binding doc, that means after this patch applied, users still can't see it if separate, Should we worry about this issue or not?

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 30

Quoted 2 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +2 -0
+       Refer to imx7ulp-pinfunc.h in in device tree source folder for all
+       available imx7ulp PIN_FUNC_ID.

Ah, okay, there is a reason to have it in the bindings doc patch. If LinusW and Rob have no problem with it, I'm fine then.

Acked-by Shawn Guo <[email protected]>
#14 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

In reply to Dong Aisheng
Quoted 11 lines · Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.

Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

(...)

Quoted 8 lines
+=== Pin Configuration Node ===
+- pins: One integers array, represents a group of pins mux setting.
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +6 -0
+       The format is fsl,pins = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
+       a specific function.
+
+       NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
+       and config register as follows:
+       <mux_conf_reg input_reg mux_mode input_val>

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 37

Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +10 -0
+
+       Refer to imx7ulp-pinfunc.h in in device tree source folder for all
+       available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- nxp,output-buffer-enable:    Bool. Output buffer enabled
+- nxp,input-buffer-enable:     Bool. Input buffer enabled
+- drive-strength               Integer. Controls Drive Strength
+                                       0: Standard
+                                       1: Hi Driver

(...)

WELL LOOK AT THAT

Custom input/output buffer enable properties eh?

We had this really really long discussion with the Renesas people about whether they make this a custom property or a generic one or whether anyone else would ever have the same need.

This would be a vote for adding output-buffer-enable and input-buffer-enable as generic properies hm?

UNLESS the existing device tree properties already cover the usecases.

Andy has made some good points there.

Can you please read up on the discussion thread for subject "[PATCH v5 01/10] pinctrl: generic: Add bi-directional and output-enable" and contribute to this discussion?

Yours,
Linus Walleij

author maintainer
#15 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 51 lines

-----Original Message-----
From: Linus Walleij [mailto:linus.walleij at linaro.org]
Sent: Monday, May 22, 2017 5:27 PM
To: A.S. Dong; Jacopo Mondi; Geert Uytterhoeven; Chris Brandt; Andy Shevchenko
Cc: linux-gpio at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Shawn Guo; Stefan Agner; Jacky Bai; Andy Duan; Sascha Hauer; Rob Herring; Mark Rutland; devicetree at vger.kernel.org
Subject: Re: [PATCH V2 4/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 11 lines · Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.

Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

(...)

Quoted 3 lines
+=== Pin Configuration Node ===
+- pins: One integers array, represents a group of pins mux setting.
+       The format is fsl,pins = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin

working on

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt

Quoted 3 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +3 -0
+       a specific function.
+
+       NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares

one mux

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt

Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +4 -0
+       and config register as follows:
+       <mux_conf_reg input_reg mux_mode input_val>
+
+       Refer to imx7ulp-pinfunc.h in in device tree source folder for

all

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt line 37

Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +8 -0
+       available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- nxp,output-buffer-enable:    Bool. Output buffer enabled
+- nxp,input-buffer-enable:     Bool. Input buffer enabled
+- drive-strength               Integer. Controls Drive Strength
+                                       0: Standard
+                                       1: Hi Driver

(...)

WELL LOOK AT THAT

Quoted 9 lines

Custom input/output buffer enable properties eh?

We had this really really long discussion with the Renesas people about whether they make this a custom property or a generic one or whether anyone else would ever have the same need.

This would be a vote for adding output-buffer-enable and input-buffer- enable as generic properies hm?

Yes, that would be good if they're made generic properties.

Quoted 8 lines

UNLESS the existing device tree properties already cover the usecases.

Andy has made some good points there.

Can you please read up on the discussion thread for subject "[PATCH v5 01/10] pinctrl: generic: Add bi-directional and output-enable" and contribute to this discussion?

Sure, will find time to read it.

Thanks for the reminder.

Regards
Dong Aisheng

#16 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

In reply to Dong Aisheng
Quoted 123 lines · Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.

Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---
ChangeLog:
v1->v2:
* add more descriptions in binding doc
* add missed prefix for private properties.
* move dt-bindings/pinctrl/imx7ulp-pinfunc.h to arch/arm/boot/dts

---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  63 +++
 arch/arm/boot/dts/imx7ulp-pinfunc.h                | 468 +++++++++++++++++++++
 2 files changed, 531 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/imx7ulp-pinfunc.h

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file mode 100644
index 0000000..7fbf367

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +63 -0
@@ -0,0 +1,63 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
+ports and IOMUXC DDR for DDR interface.
+
+Note:
+This binding doc is only for the IOMUXC1 support in A7 Domain and it only
+supports generic pin config.
+
+Please also refer to fsl,imx-pinctrl.txt in this directory for IMX common
+binding part and pinctrl-bindings.txt for the generic config binding.
+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible:	"fsl,imx7ulp-iomuxc1"
+- reg:		Should contain the base physical address and size of the iomuxc
+		registers.
+
+=== Pin Configuration Node ===
+- pins: One integers array, represents a group of pins mux setting.
+	The format is fsl,pins = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
+	a specific function.
+
+	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
+	and config register as follows:
+	<mux_conf_reg input_reg mux_mode input_val>
+
+	Refer to imx7ulp-pinfunc.h in in device tree source folder for all
+	available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- nxp,output-buffer-enable:	Bool. Output buffer enabled
+- nxp,input-buffer-enable:	Bool. Input buffer enabled
+- drive-strength		Integer. Controls Drive Strength
+					0: Standard
+					1: Hi Driver
+- drive-push-pull		Bool. Enable Pin Push-pull
+- drive-open-drain		Bool. Enable Pin Open-drian
+- slew-rate:			Integer. Controls Slew Rate
+					0: Standard
+					1: Slow
+- bias-disable:			Bool. Pull disabled
+- bias-pull-down:		Bool. Pull down on pin
+- bias-pull-up:			Bool. Pull up on pin
+
+Examples:
+#include "imx7ulp-pinfunc.h"
+
+/* Pin Controller Node */
+iomuxc1: iomuxc at 40ac0000 {
+	compatible = "fsl,imx7ulp-iomuxc1";
+	reg = <0x40ac0000 0x1000>;
+
+	/* Pin Configuration Node */
+	pinctrl_lpuart4: lpuart4grp {
+		pins = <
+			ULP1_PAD_PTC3__LPUART4_RX
+			ULP1_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+};
arch/arm/boot/dts/imx7ulp-pinfunc.h new file +19 -0
new file mode 100644
index 0000000..cafd3ed
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX7ULP_PINFUNC_H
+#define __DTS_IMX7ULP_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_conf_reg input_reg mux_mode input_val>
+ */
+
+#define ULP1_PAD_PTC0__PTC0
Quoted 1 line

0x0000 0x0000 0x1 0x0

For consistency with other SoCs, can we add MX7 to the define? E.g. MX7ULP1?

--
Stefan

author maintainer
#17 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 138 lines

-----Original Message-----
From: Stefan Agner [mailto:stefan at agner.ch]
Sent: Tuesday, May 23, 2017 12:16 AM
To: A.S. Dong
Cc: linux-gpio at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linus.walleij at linaro.org; shawnguo at kernel.org; Jacky Bai; Andy Duan; kernel at pengutronix.de; Rob Herring; Mark Rutland;
devicetree at vger.kernel.org
Subject: Re: [PATCH V2 4/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 18 lines · Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.

Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---
ChangeLog:
v1->v2:
* add more descriptions in binding doc
* add missed prefix for private properties.
* move dt-bindings/pinctrl/imx7ulp-pinfunc.h to arch/arm/boot/dts

Quoted 3 lines
---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  63 +++
 arch/arm/boot/dts/imx7ulp-pinfunc.h                | 468

+++++++++++++++++++++

Quoted 15 lines
 2 files changed, 531 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/imx7ulp-pinfunc.h

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file mode 100644
index 0000000..7fbf367

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +2 -0
+++ t

@@ -0,0 +1,63 @@
+* Freescale i.MX7ULP IOMUX Controller

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 11

Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +10 -0
+
+i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1
+for A7 ports and IOMUXC DDR for DDR interface.
+
+Note:
+This binding doc is only for the IOMUXC1 support in A7 Domain and it
+only supports generic pin config.
+
+Please also refer to fsl,imx-pinctrl.txt in this directory for IMX
+common binding part and pinctrl-bindings.txt for the generic config

binding.

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 17

Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +6 -0
+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible:	"fsl,imx7ulp-iomuxc1"
+- reg:		Should contain the base physical address and size of the

iomuxc

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 22

Quoted 5 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +5 -0
+		registers.
+
+=== Pin Configuration Node ===
+- pins: One integers array, represents a group of pins mux setting.
+	The format is fsl,pins = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working

on

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx line 25

Quoted 3 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +3 -0
+	a specific function.
+
+	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one

mux

Quoted 61 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.tx new file +38 -0
+	and config register as follows:
+	<mux_conf_reg input_reg mux_mode input_val>
+
+	Refer to imx7ulp-pinfunc.h in in device tree source folder for all
+	available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- nxp,output-buffer-enable:	Bool. Output buffer enabled
+- nxp,input-buffer-enable:	Bool. Input buffer enabled
+- drive-strength		Integer. Controls Drive Strength
+					0: Standard
+					1: Hi Driver
+- drive-push-pull		Bool. Enable Pin Push-pull
+- drive-open-drain		Bool. Enable Pin Open-drian
+- slew-rate:			Integer. Controls Slew Rate
+					0: Standard
+					1: Slow
+- bias-disable:			Bool. Pull disabled
+- bias-pull-down:		Bool. Pull down on pin
+- bias-pull-up:			Bool. Pull up on pin
+
+Examples:
+#include "imx7ulp-pinfunc.h"
+
+/* Pin Controller Node */
+iomuxc1: iomuxc at 40ac0000 {
+	compatible = "fsl,imx7ulp-iomuxc1";
+	reg = <0x40ac0000 0x1000>;
+
+	/* Pin Configuration Node */
+	pinctrl_lpuart4: lpuart4grp {
+		pins = <
+			ULP1_PAD_PTC3__LPUART4_RX
+			ULP1_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+};
arch/arm/boot/dts/imx7ulp-pinfunc.h new file +16 -0
new file mode 100644
index 0000000..cafd3ed
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX7ULP_PINFUNC_H
+#define __DTS_IMX7ULP_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
Quoted 9 lines
Quoted 4 lines
arch/arm/boot/dts/imx7ulp-pinfunc.h new file +3 -0
+ * <mux_conf_reg input_reg mux_mode input_val>  */
+
+#define ULP1_PAD_PTC0__PTC0

0x0000 0x0000 0x1 0x0

For consistency with other SoCs, can we add MX7 to the define? E.g. MX7ULP1?

ULP1 is another SoC name of IMX7ULP.
And there will be ULP0, ULPx in the future..

It looks like not big issue, so I did not change it.

Regards
Dong Aisheng

#18 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 15 lines · A.S. Dong
Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/imx7ulp-pinfunc.h new file +5 -0
+#ifndef __DTS_IMX7ULP_PINFUNC_H
+#define __DTS_IMX7ULP_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
Quoted 9 lines
Quoted 4 lines

+ * <mux_conf_reg input_reg mux_mode input_val> */

(quoted diff) +2 -0
+
+#define ULP1_PAD_PTC0__PTC0

0x0000 0x0000 0x1 0x0

For consistency with other SoCs, can we add MX7 to the define? E.g. MX7ULP1?

Quoted 2 lines

ULP1 is another SoC name of IMX7ULP.
And there will be ULP0, ULPx in the future..

What is the external/formal SoC name for ULP0 and ULPx?

Quoted 2 lines

It looks like not big issue, so I did not change it.

It's an easy change to make things more obvious, so +1 on Stefan's opinion.

Shawn

author maintainer
#19 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 26 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Thursday, May 25, 2017 11:16 AM
To: A.S. Dong
Cc: Stefan Agner; Mark Rutland; devicetree at vger.kernel.org; Andy Duan; Jacky Bai; linus.walleij at linaro.org; linux-gpio at vger.kernel.org; Rob Herring; kernel at pengutronix.de; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH V2 4/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 15 lines · A.S. Dong
Quoted 14 lines
Quoted 9 lines
arch/arm/boot/dts/imx7ulp-pinfunc.h new file +8 -0
+#ifndef __DTS_IMX7ULP_PINFUNC_H
+#define __DTS_IMX7ULP_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_conf_reg input_reg mux_mode input_val>  */
+
+#define ULP1_PAD_PTC0__PTC0

0x0000 0x0000 0x1 0x0

For consistency with other SoCs, can we add MX7 to the define? E.g. MX7ULP1?

Quoted 5 lines
Quoted 2 lines

ULP1 is another SoC name of IMX7ULP.
And there will be ULP0, ULPx in the future..

What is the external/formal SoC name for ULP0 and ULPx?

I don't know, it's still a plan.
Maybe IMX7ULP0, just can't sure.

Quoted 5 lines
Quoted 2 lines

It looks like not big issue, so I did not change it.

It's an easy change to make things more obvious, so +1 on Stefan's opinion.

If we really want to change, 'IMX7ULP1' may be a little strange as 'IMX7ULP' is the official external name and all other places are using it.
So IMX7ULP may be more suitable.

Then next generation may be:
IMX7ULP0_PAD_PTC0_PTC0.
Vs
IMX7ULP_PAD_PTC0_PTC0

Just not much better than:
ULP1_PAD_PTC0_PTC0.
vs
ULP0_PAD_PTC0_PTC0

That's why I did not do it initially.

However, if you do want the change, i'm okay to do it.

Regards
Dong Aisheng

#20 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 3 lines · A.S. Dong

If we really want to change, 'IMX7ULP1' may be a little strange as 'IMX7ULP' is the official external name and all other places are using it.
So IMX7ULP may be more suitable.

Yes, I actually meant IMX7ULP, which matches how we name the SoC elsewhere in the kernel.

Quoted 6 lines

Then next generation may be:
IMX7ULP0_PAD_PTC0_PTC0.
Vs
IMX7ULP_PAD_PTC0_PTC0

Quoted 8 lines

Just not much better than:
ULP1_PAD_PTC0_PTC0.
vs
ULP0_PAD_PTC0_PTC0

That's why I did not do it initially.

However, if you do want the change, i'm okay to do it.

For the next generation, we will have a name for it in the kernel anyway. The pinctrl macro simply follows that name.

Shawn

#21 lore raw

PATCH v2 4/5 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 8 lines · Shawn Guo
Quoted 3 lines · A.S. Dong

If we really want to change, 'IMX7ULP1' may be a little strange as 'IMX7ULP' is the official external name and all other places are using it.
So IMX7ULP may be more suitable.

Yes, I actually meant IMX7ULP, which matches how we name the SoC elsewhere in the kernel.

All the other arch/arm/boot/dts/imx*pinfunc.h use MX7ULP (without the I), but I am fine with either one.

--
Stefan

Quoted 19 lines
Quoted 6 lines

Then next generation may be:
IMX7ULP0_PAD_PTC0_PTC0.
Vs
IMX7ULP_PAD_PTC0_PTC0

Quoted 8 lines

Just not much better than:
ULP1_PAD_PTC0_PTC0.
vs
ULP0_PAD_PTC0_PTC0

That's why I did not do it initially.

However, if you do want the change, i'm okay to do it.

For the next generation, we will have a name for it in the kernel anyway. The pinctrl macro simply follows that name.

Shawn

author maintainer
#22 lore raw

PATCH v2 5/5 pinctrl: imx: add imx7ulp driver

In reply to Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.
It only supports generic pin config.

Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Bai Ping <[email protected]>
Cc Fugang Duan <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---
* no changes

---
 drivers/pinctrl/freescale/Kconfig           |   7 +
 drivers/pinctrl/freescale/Makefile          |   1 +
 drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 358 ++++++++++++++++++++++++++++
 3 files changed, 366 insertions(+)
 create mode 100644 drivers/pinctrl/freescale/pinctrl-imx7ulp.c
drivers/pinctrl/freescale/Kconfig +7 -0
index 0b266b2..4dbc576 100644
@@ -103,6 +103,13 @@ config PINCTRL_IMX7D
 	help
 	  Say Y here to enable the imx7d pinctrl driver
 
+config PINCTRL_IMX7ULP
+	bool "IMX7ULP pinctrl driver"
+	depends on SOC_IMX7ULP
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the imx7ulp pinctrl driver
+
 config PINCTRL_VF610
 	bool "Freescale Vybrid VF610 pinctrl driver"
 	depends on SOC_VF610
drivers/pinctrl/freescale/Makefile +1 -0
index d44c9e2..525a5ff 100644
@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_IMX6SL)	+= pinctrl-imx6sl.o
 obj-$(CONFIG_PINCTRL_IMX6SX)	+= pinctrl-imx6sx.o
 obj-$(CONFIG_PINCTRL_IMX6UL)	+= pinctrl-imx6ul.o
 obj-$(CONFIG_PINCTRL_IMX7D)	+= pinctrl-imx7d.o
+obj-$(CONFIG_PINCTRL_IMX7ULP)	+= pinctrl-imx7ulp.o
 obj-$(CONFIG_PINCTRL_VF610)	+= pinctrl-vf610.o
 obj-$(CONFIG_PINCTRL_MXS)	+= pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_IMX23)	+= pinctrl-imx23.o
drivers/pinctrl/freescale/pinctrl-imx7ulp.c new file +358 -0

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2.7.4
#23 lore raw

PATCH v2 5/5 pinctrl: imx: add imx7ulp driver

Quoted 11 lines · Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.
It only supports generic pin config.

Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Bai Ping <[email protected]>
Cc Fugang Duan <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
Acked-by Shawn Guo <[email protected]>
#24 lore raw

v2 cover pinctrl: imx: add generic pin config and imx7ulp support

In reply to Dong Aisheng
Quoted 2 lines · Dong Aisheng

This patch series intends to add the generic pin config support for imx platforms.

I applied patches 1,2,3 as you've seen, so please rebase on my "devel" branch in pin control and only resend the things we are still discussing.

I see there are some other patches flying for imx pin control and GPIO, if the patches are dependent on each other consider putting it all into one series. If they are not dependent, then don't.

Yours,
Linus Walleij

author maintainer
#25 lore raw

v2 cover pinctrl: imx: add generic pin config and imx7ulp support

Quoted 9 lines

-----Original Message-----
From: Linus Walleij [mailto:linus.walleij at linaro.org]
Sent: Tuesday, May 23, 2017 3:41 PM
To: A.S. Dong
Cc: linux-gpio at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Shawn Guo; Stefan Agner; Jacky Bai; Andy Duan; Sascha Hauer
Subject: Re: [PATCH V2 0/5] pinctrl: imx: add generic pin config and imx7ulp support

Quoted 8 lines
Quoted 2 lines · Dong Aisheng

This patch series intends to add the generic pin config support for imx platforms.

I applied patches 1,2,3 as you've seen, so please rebase on my "devel" branch in pin control and only resend the things we are still discussing.

Got it, thanks for the reminder.

Quoted 4 lines

I see there are some other patches flying for imx pin control and GPIO, if the patches are dependent on each other consider putting it all into one series. If they are not dependent, then don't.

I will consider it.

Regards
Dong Aisheng