ARM: NOMMU: MPU updates

Hi,

This is an update of the existent MPU code which consist set of clean-ups and enhancements. The most significant changes are in the way how MPU settings sync-up for secondaries (PATCH 3/7) and more flexible layout for memory (PATCH 7/7). Since there is no in-tree user of MPU, support for M-class has been added (PATCH 6/7).

Thanks!

Changelog:

	    RFC -> RFC v2
	       - fixed MPU enable for v7m (PATCH 6/7)

Vladimir Murzin (7):
ARM: NOMMU: Move out MPU setup in separate module
ARM: NOMMU: Update MPU accessors to use cp15 helpers
ARM: NOMMU: Rework MPU to be mostly done in C
ARM: NOMMU: Disallow MPU for XIP
ARM: Kconfig: Kill CONFIG_VECTORS_BASE
ARM: V7M: Add support for MPU to M-class
ARM: NOMMU: Use more MPU regions to cover memory

 arch/arm/Kconfig               |   9 -
 arch/arm/Kconfig-nommu         |   4 +-
 arch/arm/include/asm/cputype.h |  10 +
 arch/arm/include/asm/mpu.h     |  23 ++-
 arch/arm/include/asm/smp.h     |   2 +-
 arch/arm/include/asm/v7m.h     |  10 +
 arch/arm/kernel/asm-offsets.c  |  11 +
 arch/arm/kernel/head-nommu.S   | 128 +++++++++---
 arch/arm/kernel/smp.c          |   2 +-
 arch/arm/mm/Makefile           |   1 +
 arch/arm/mm/nommu.c            | 254 +----------------------
 arch/arm/mm/pmsa-v7.c          | 445 +++++++++++++++++++++++++++++++++++++++++
 12 files changed, 598 insertions(+), 301 deletions(-)
 create mode 100644 arch/arm/mm/pmsa-v7.c

2.0.0

Having MPU handling code in dedicated module makes it easier to enhance/maintain it.

---
 arch/arm/include/asm/mpu.h |  16 ++-
 arch/arm/mm/Makefile       |   1 +
 arch/arm/mm/nommu.c        | 254 +------------------------------------------
 arch/arm/mm/pmsa-v7.c      | 262 +++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 276 insertions(+), 257 deletions(-)
 create mode 100644 arch/arm/mm/pmsa-v7.c

index c3247cc..edec5cf 100644
@@ -1,8 +1,6 @@
 #ifndef __ARM_MPU_H
 #define __ARM_MPU_H
 
-#ifdef CONFIG_ARM_MPU
-
 /* MPUIR layout */
 #define MPUIR_nU		1
 #define MPUIR_DREGION		8

@@ -69,8 +67,18 @@ struct mpu_rgn_info {
 };
 extern struct mpu_rgn_info mpu_rgn_info;
 
-#endif /* __ASSEMBLY__ */
+#ifdef CONFIG_ARM_MPU
+
+extern void __init adjust_lowmem_bounds_mpu(void);
+extern void __init mpu_setup(void);
 
-#endif /* CONFIG_ARM_MPU */
+#else
+
+static inline void adjust_lowmem_bounds_mpu(void) {}
+static inline void mpu_setup(void) {}
+
+#endif /* !CONFIG_ARM_MPU */
+
+#endif /* __ASSEMBLY__ */
 
 #endif

index b3dea80..73f8f3c 100644
@@ -10,6 +10,7 @@ obj-$(CONFIG_MMU)		+= fault-armv.o flush.o idmap.o ioremap.o \
 
 ifneq ($(CONFIG_MMU),y)
 obj-y				+= nommu.o
+obj-$(CONFIG_ARM_MPU)		+= pmsa-v7.o
 endif
 
 obj-$(CONFIG_ARM_PTDUMP)	+= dump.o

2.0.0

Currently, inline assembly for accessing to MPU's cp15 lacks volatile keyword which opens possibility to compiler to optimise such accesses as soon as we start using them more intensively. Rather than fixing inline asm, lets move MPU accessors to use cp15 helpers which do the right thing.

---
 arch/arm/mm/pmsa-v7.c | 48 ++++++++++++++++++++++++++----------------------
 1 file changed, 26 insertions(+), 22 deletions(-)

index ee3cf51..5b55f8f 100644
@@ -12,63 +12,67 @@
 
 #include "mm.h"
 
+#define DRBAR	__ACCESS_CP15(c6, 0, c1, 0)
+#define IRBAR	__ACCESS_CP15(c6, 0, c1, 1)
+#define DRSR	__ACCESS_CP15(c6, 0, c1, 2)
+#define IRSR	__ACCESS_CP15(c6, 0, c1, 3)
+#define DRACR	__ACCESS_CP15(c6, 0, c1, 4)
+#define IRACR	__ACCESS_CP15(c6, 0, c1, 5)
+#define RNGNR	__ACCESS_CP15(c6, 0, c2, 0)
+
 /* Region number */
-static void rgnr_write(u32 v)
+static inline void rgnr_write(u32 v)
 {
-	asm("mcr        p15, 0, %0, c6, c2, 0" : : "r" (v));
+	write_sysreg(v, RNGNR);
 }
 
 /* Data-side / unified region attributes */
 
 /* Region access control register */
-static void dracr_write(u32 v)
+static inline void dracr_write(u32 v)
 {
-	asm("mcr        p15, 0, %0, c6, c1, 4" : : "r" (v));
+	write_sysreg(v, DRACR);
 }
 
 /* Region size register */
-static void drsr_write(u32 v)
+static inline void drsr_write(u32 v)
 {
-	asm("mcr        p15, 0, %0, c6, c1, 2" : : "r" (v));
+	write_sysreg(v, DRSR);
 }
 
 /* Region base address register */
-static void drbar_write(u32 v)
+static inline void drbar_write(u32 v)
 {
-	asm("mcr        p15, 0, %0, c6, c1, 0" : : "r" (v));
+	write_sysreg(v, DRBAR);
 }
 
-static u32 drbar_read(void)
+static inline u32 drbar_read(void)
 {
-	u32 v;
-	asm("mrc        p15, 0, %0, c6, c1, 0" : "=r" (v));
-	return v;
+	return read_sysreg(DRBAR);
 }
 /* Optional instruction-side region attributes */
 
 /* I-side Region access control register */
-static void iracr_write(u32 v)
+static inline void iracr_write(u32 v)
 {
-	asm("mcr        p15, 0, %0, c6, c1, 5" : : "r" (v));
+	write_sysreg(v, IRACR);
 }
 
 /* I-side Region size register */
-static void irsr_write(u32 v)
+static inline void irsr_write(u32 v)
 {
-	asm("mcr        p15, 0, %0, c6, c1, 3" : : "r" (v));
+	write_sysreg(v, IRSR);
 }
 
 /* I-side Region base address register */
-static void irbar_write(u32 v)
+static inline void irbar_write(u32 v)
 {
-	asm("mcr        p15, 0, %0, c6, c1, 1" : : "r" (v));
+	write_sysreg(v, IRBAR);
 }
 
-static unsigned long irbar_read(void)
+static inline u32 irbar_read(void)
 {
-	unsigned long v;
-	asm("mrc        p15, 0, %0, c6, c1, 1" : "=r" (v));
-	return v;
+	return read_sysreg(IRBAR);
 }
 
 /* MPU initialisation functions */

2.0.0

Currently, there are several issues with how MPU is setup:

1. We won't boot if MPU is missing
2. We won't boot if use XIP
3. Further extension of MPU setup requires asm skills

The 1st point can be relaxed, so we can continue with boot CPU even if MPU is missed and fail boot for secondaries only. To address the 2nd point we could create region covering CONFIG_XIP_PHYS_ADDR - _end and that might work for the first stage of MPU enable, but due to MPU's alignment requirement we could cover too much, IOW we need more flexibility in how we're partitioning memory regions... and it'd be hardly possible to archive because of the 3rd point.

This patch is trying to address 1st and 3rd issues and paves the path for 2nd and further improvements.

The most visible change introduced with this patch is that we start using mpu_rgn_info array (as it was supposed?), so change in MPU setup done by boot CPU is recorded there and feed to secondaries. It allows us to keep minimal region setup for boot CPU and do the rest in C. Since we start programming MPU regions in C evaluation of MPU constrains (number of regions supported and minimal region order) can be done once, which in turn open possibility to free-up "probe" region early.

---
 arch/arm/include/asm/mpu.h    |  2 +-
 arch/arm/include/asm/smp.h    |  2 +-
 arch/arm/kernel/asm-offsets.c | 11 ++++++
 arch/arm/kernel/head-nommu.S  | 80 +++++++++++++++++++++++++++++++++----------
 arch/arm/kernel/smp.c         |  2 +-
 arch/arm/mm/pmsa-v7.c         | 70 +++++++++++++++++++++++++++----------
 6 files changed, 127 insertions(+), 40 deletions(-)

index edec5cf..403462e 100644
@@ -62,7 +62,7 @@ struct mpu_rgn {
 };
 
 struct mpu_rgn_info {
-	u32 mpuir;
+	unsigned int used;
 	struct mpu_rgn rgns[MPU_MAX_REGIONS];
 };
 extern struct mpu_rgn_info mpu_rgn_info;

index 3d6dc8b..709a559 100644
@@ -60,7 +60,7 @@ asmlinkage void secondary_start_kernel(void);
  */
 struct secondary_data {
 	union {
-		unsigned long mpu_rgn_szr;
+		struct mpu_rgn_info *mpu_rgn_info;
 		u64 pgdir;
 	};
 	unsigned long swapper_pg_dir;

index 6080082..0098d3c4 100644
@@ -23,6 +23,7 @@
 #include <asm/mach/arch.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>
+#include <asm/mpu.h>
 #include <asm/procinfo.h>
 #include <asm/suspend.h>
 #include <asm/vdso_datapage.h>

@@ -183,5 +184,15 @@ int main(void)
 #ifdef CONFIG_VDSO
   DEFINE(VDSO_DATA_SIZE,	sizeof(union vdso_data_store));
 #endif
+  BLANK();
+#ifdef CONFIG_ARM_MPU
+  DEFINE(MPU_RNG_INFO_RNGS,	offsetof(struct mpu_rgn_info, rgns));
+  DEFINE(MPU_RNG_INFO_USED,	offsetof(struct mpu_rgn_info, used));
+
+  DEFINE(MPU_RNG_SIZE,		sizeof(struct mpu_rgn));
+  DEFINE(MPU_RGN_DRBAR,		offsetof(struct mpu_rgn, drbar));
+  DEFINE(MPU_RGN_DRSR,		offsetof(struct mpu_rgn, drsr));
+  DEFINE(MPU_RGN_DRACR,		offsetof(struct mpu_rgn, dracr));
+#endif
   return 0; 
 }

index 572a8df..5cb8cdf 100644
@@ -114,7 +114,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
 	 */
 	secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
 #ifdef CONFIG_ARM_MPU
-	secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr;
+	secondary_data.mpu_rgn_info = &mpu_rgn_info;
 #endif
 
 #ifdef CONFIG_MMU

2.0.0

It seems that MPU never worked with XIP, so we just disallow such combination.

---
 arch/arm/Kconfig-nommu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index b757634..6d18395 100644
@@ -52,7 +52,7 @@ config REMAP_VECTORS_TO_RAM
 
 config ARM_MPU
        bool 'Use the ARM v7 PMSA Compliant MPU'
-       depends on CPU_V7
+       depends on !XIP_KERNEL && CPU_V7
        default y
        help
          Some ARM systems without an MMU have instead a Memory Protection

2.0.0

The last user of CONFIG_VECTORS_BASE has gone, so kill it.

---
 arch/arm/Kconfig | 9 ---------
 1 file changed, 9 deletions(-)

index 9eb2529..332b6f2 100644
@@ -236,15 +236,6 @@ config NEED_RET_TO_USER
 config ARCH_MTD_XIP
 	bool
 
-config VECTORS_BASE
-	hex
-	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
-	default DRAM_BASE if REMAP_VECTORS_TO_RAM
-	default 0x00000000
-	help
-	  The base address of exception vectors.  This must be two pages
-	  in size.
-
 config ARM_PATCH_PHYS_VIRT
 	bool "Patch physical to virtual translations at runtime" if EMBEDDED
 	default y

2.0.0

Hi,

Ending up in this tag has left me scratching my head & amused :), whether you keep any tag or not for me, i do not have any issues.

Regards
afzal

Hi,

According to [1]:

"This series also does the preparation for CONFIG_VECTORS_BASE removal."

IIRC, that time only thing which stopped you from complete CONFIG_VECTORS_BASE removal was MPU code, so I don't see a reason not to give you a credit ;)

[1] https://lkml.org/lkml/2017/1/21/251

Cheers
Vladimir

This patch makes it possible to use MPU with v7M cores.

---
 arch/arm/Kconfig-nommu         |  4 +--
 arch/arm/include/asm/cputype.h | 10 ++++++++
 arch/arm/include/asm/v7m.h     | 10 ++++++++
 arch/arm/kernel/head-nommu.S   | 56 ++++++++++++++++++++++++++++++------------
 arch/arm/mm/pmsa-v7.c          | 53 +++++++++++++++++++++++++++++++++++++--
 5 files changed, 113 insertions(+), 20 deletions(-)

index 6d18395..930e000 100644
@@ -52,8 +52,8 @@ config REMAP_VECTORS_TO_RAM
 
 config ARM_MPU
        bool 'Use the ARM v7 PMSA Compliant MPU'
-       depends on !XIP_KERNEL && CPU_V7
-       default y
+       depends on !XIP_KERNEL && (CPU_V7 || CPU_V7M)
+       default y if CPU_V7
        help
          Some ARM systems without an MMU have instead a Memory Protection
          Unit (MPU) that defines the type and permissions for regions of

index b62eaeb..abaac5e 100644
@@ -173,6 +173,11 @@ static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 	return read_cpuid(CPUID_CACHETYPE);
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
+{
+	return read_cpuid(CPUID_MPUIR);
+}
+
 #elif defined(CONFIG_CPU_V7M)
 
 static inline unsigned int __attribute_const__ read_cpuid_id(void)

@@ -185,6 +190,11 @@ static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 	return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
+{
+	return readl(BASEADDR_V7M_SCB + MPU_TYPE);
+}
+
 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 
 static inline unsigned int __attribute_const__ read_cpuid_id(void)

index 1fd775c..5de776c 100644
@@ -57,6 +57,16 @@
 #define	V7M_SCB_CCSIDR		0x80	/* Cache size ID register */
 #define	V7M_SCB_CSSELR		0x84	/* Cache size selection register */
 
+/* Memory-mapped MPU registers for M-class */
+#define MPU_TYPE		0x90
+#define MPU_CTRL		0x94
+#define MPU_CTRL_ENABLE		1
+#define MPU_CTRL_PRIVDEFENA	(1 << 2)
+
+#define MPU_RNR			0x98
+#define MPU_RBAR		0x9c
+#define MPU_RASR		0xa0
+
 /* Cache opeartions */
 #define	V7M_SCB_ICIALLU		0x250	/* I-cache invalidate all to PoU */
 #define	V7M_SCB_ICIMVAU		0x258	/* I-cache invalidate by MVA to PoU */

2.0.0

PMSAv7 defines curious alignment requirements to the regions:
- size must be power of 2, and
- region start must be aligned to the region size

Because of that we currently adjust lowmem bounds plus we assign only one MPU region to cover memory all these lead to significant amount of memory could be wasted. As an example, consider 64Mb of memory at 0x70000000 - it fits alignment requirements nicely; now, imagine that 2Mb of memory is reserved for coherent DMA allocation, so now Linux is expected to see 62Mb of memory... and here annoying thing happens - memory gets truncated to 32Mb (we've lost 30Mb!), i.e. MPU layout looks like:

0: base 0x70000000, size 0x2000000

This patch tries to allocate as much as possible MPU slots to minimise amount of truncated memory. Moreover, with this patch MPU subregions starting to get used. MPU subregions allow us reduce the number of MPU slots used. For example given above, MPU layout looks like:

0: base 0x70000000, size 0x2000000
1: base 0x72000000, size 0x1000000
2: base 0x73000000, size 0x1000000, disable subreg 7 (0x73e00000 - 0x73ffffff)

Where without subregions we'd get:

0: base 0x70000000, size 0x2000000
1: base 0x72000000, size 0x1000000
2: base 0x73000000, size 0x800000
3: base 0x73800000, size 0x400000
4: base 0x73c00000, size 0x200000

To achieve better layout we fist try to cover specified memory as is (maybe with help of subregions) and if we failed, we truncate memory to fit alignment requirements (so it occupies one MPU slot) and perform one more attempt with the reminder, and so on till we either cover all memory or run out of MPU slots.

---
 arch/arm/include/asm/mpu.h |   5 ++
 arch/arm/mm/pmsa-v7.c      | 190 ++++++++++++++++++++++++++++++++++-----------
 2 files changed, 149 insertions(+), 46 deletions(-)

index 403462e..5db37a6 100644
@@ -15,6 +15,11 @@
 /* MPU D/I Size Register fields */
 #define MPU_RSR_SZ		1
 #define MPU_RSR_EN		0
+#define MPU_RSR_SD		8
+
+/* Number of subregions (SD) */
+#define MPU_NR_SUBREGS		8
+#define MPU_MIN_SUBREG_SIZE	256
 
 /* The D/I RSR value for an enabled region spanning the whole of memory */
 #define MPU_RSR_ALL_MEM		63

2.0.0

Hi,

I?ve tested these patches on my custom Atmel SAME70 armv7m board, along with the
"ARM: Fix dma_alloc_coherent() and friends for NOMMU" patches.

Both series works fine for me. These MPU patches introduce a nice feature that it simplifies the bootloader:
do not need to setup the MPU, for example for coherent DMA region, which is described in device-tree too.

So you can add my Tested-by.

Booting Linux on physical CPU 0x0
Linux version 4.12.0-rc1 (root at devel) (gcc version 4.9.2 ( 4.9.2-10) ) #1 Fri May 19 06:26:34 EDT 2017
CPU: ARMv7-M [410fc271] revision 1 (ARMv7M), cr=00000000
CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
OF: fdt: Machine model: SAME70-sampione board
bootconsole [earlycon0] enabled
Reserved memory: created DMA memory pool at 0x73e00000, size 2 MiB
OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
Using ARMv7 PMSA Compliant MPU. Region independence: No, Used 4 of 16 regions
?

Thanks for the patches!

Regards,
Andras

Hi,

Much appreciated!

I'm glad they work for you!

Cheers
Vladimir