arm64: marvell: add cryptographic engine support for 7k/8k

PATCH New Antoine Tenart 4 participants 16 messages May 24, 2017 – Jun 20, 2017

Subsystems (4)

Device tree bindings Crypto API Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support Inside secure crypto driver

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Antoine Tenart

author

2017-05-24 14:10 UTC #0 lore raw

v6 cover arm64: marvell: add cryptographic engine support for 7k/8k

Hi all,

This series adds support for the Inside Secure SafeXcel EIP197 cryptographic engine which can be found on Marvell Armada 7k and 8k boards. A new cryptographic engine driver is added, as well as the relevant device tree definition for the Armada 7040 DB and 8040 DB boards.

This driver needs two firmwares to work correctly. These firmware are usually used for more advanced operations than the ones supported (as of now), but we still need them to pass the data to the internal cryptographic engine.

This series was tested in various ways on both the Armada 7040 DB and the Armada 8040 DB: using the crypto framework self tests, using tcrypt and while performing various transfers with iperf on top of IPsec.

This series is based on top of v4.12-rc1, and is available at:
https://github.com/atenart/linux v4.12-rc1/7k8k-crypto
I can rebase if needed. Patches adding device tree nodes and modifying the arm64 defconfig have been applied to the mvebu tree already.

I'd like to thank Ofer Heifetz and Igal Liberman who helped me to do this driver by adding functionalities, optimizing functions and testing (a lot).

Thanks,
Antoine

Since v5:
- Fixed the interrupt property in both the documentation and device tree nodes.

Since v4:
- Added a dma-mask property and updated the default DMA mask to 64.
- Replaced all <asm/dma-mapping.h> to <linux/dma-mapping.h>.
- Rebased on top of 4.12-rc1.

Since v3:
- Updated to use the skcipher API instead of the ablkcipher one.
- Added explicit zeroing of the keys.
- Fixed the DMA mask.
- Removed a few remaining phys_addr_t.

Since v2:
- Used sha*_zero_message_hash definitions instead of custom ones.
- Used memzero_explicit() instead of memset() to avoid leaks.
- Misc cosmetic updates.

Since v1:
- Fixed two compilation issues reported by Kbuild.
- Removed all dma_to_phys() calls and used the dma addresses instead.
- Added a call to dma_set_mask_and_coherent() before calling any DMA API helper.
- Removed some DMA free functions to avoid double-freeing.
- Do not rely on sg_nents_for_len() to get the number of sg anymore.
- Added a dedicated kmalloc'ed cache to use for dma_map_single().

Antoine Tenart (5):
Documentation/bindings: Document the SafeXel cryptographic engine
driver
arm64: marvell: dts: fix interrupts in 7k/8k crypto nodes
arm64: marvell: dts: add dma-mask in crypto nodes for 7k/8k
crypto: inside-secure: add SafeXcel EIP197 crypto engine driver
MAINTAINERS: add a maintainer for the Inside Secure crypto driver

 .../bindings/crypto/inside-secure-safexcel.txt     |   29 +
 MAINTAINERS                                        |    6 +
 .../boot/dts/marvell/armada-cp110-master.dtsi      |    4 +-
 .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi |    4 +-
 drivers/crypto/Kconfig                             |   17 +
 drivers/crypto/Makefile                            |    1 +
 drivers/crypto/inside-secure/Makefile              |    2 +
 drivers/crypto/inside-secure/safexcel.c            |  930 +++++++++++++++++
 drivers/crypto/inside-secure/safexcel.h            |  572 +++++++++++
 drivers/crypto/inside-secure/safexcel_cipher.c     |  556 +++++++++++
 drivers/crypto/inside-secure/safexcel_hash.c       | 1045 ++++++++++++++++++++
 drivers/crypto/inside-secure/safexcel_ring.c       |  157 +++
 12 files changed, 3319 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt
 create mode 100644 drivers/crypto/inside-secure/Makefile
 create mode 100644 drivers/crypto/inside-secure/safexcel.c
 create mode 100644 drivers/crypto/inside-secure/safexcel.h
 create mode 100644 drivers/crypto/inside-secure/safexcel_cipher.c
 create mode 100644 drivers/crypto/inside-secure/safexcel_hash.c
 create mode 100644 drivers/crypto/inside-secure/safexcel_ring.c

Signature · 1 line

2.9.4

Antoine Tenart

author

2017-05-24 14:10 UTC #1 lore raw

PATCH v6 1/5 Documentation/bindings: Document the SafeXel cryptographic engine driver

The Inside Secure Safexcel cryptographic engine is found on some Marvell SoCs (7k/8k). Document the bindings used by its driver.

Signed-off-by Antoine Tenart <[email protected]>

---
 .../bindings/crypto/inside-secure-safexcel.txt     | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt

Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt new file +29 -0

new file mode 100644
index 000000000000..f69773f4252b
@@ -0,0 +1,29 @@
+Inside Secure SafeXcel cryptographic engine
+
+Required properties:
+- compatible: Should be "inside-secure,safexcel-eip197".
+- reg: Base physical address of the engine and length of memory mapped region.
+- interrupts: Interrupt numbers for the rings and engine.
+- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
+
+Optional properties:
+- clocks: Reference to the crypto engine clock.
+- dma-mask: The address mask limitation. Defaults to 64.
+
+Example:
+
+	crypto: crypto at 800000 {
+		compatible = "inside-secure,safexcel-eip197";
+		reg = <0x800000 0x200000>;
+		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
+				  "eip";
+		clocks = <&cpm_syscon0 1 26>;
+		dma-mask = <0xff 0xffffffff>;
+		status = "disabled";
+	};

Signature · 1 line

2.9.4

Antoine Tenart

author

2017-06-11 08:53 UTC #2 lore raw

PATCH v6 1/5 Documentation/bindings: Document the SafeXel cryptographic engine driver

Hi Herbert,

Quoted 4 lines · Antoine Tenart

The Inside Secure Safexcel cryptographic engine is found on some Marvell SoCs (7k/8k). Document the bindings used by its driver.
Signed-off-by Antoine Tenart <[email protected]>

Since you applied the Safexcel crypto driver patch, I think you should also apply this patch adding the corresponding bindings documentation.

Thanks!
Antoine

Quoted 43 lines

---
 .../bindings/crypto/inside-secure-safexcel.txt     | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt

Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt new file +29 -0

new file mode 100644
index 000000000000..f69773f4252b
@@ -0,0 +1,29 @@
+Inside Secure SafeXcel cryptographic engine
+
+Required properties:
+- compatible: Should be "inside-secure,safexcel-eip197".
+- reg: Base physical address of the engine and length of memory mapped region.
+- interrupts: Interrupt numbers for the rings and engine.
+- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
+
+Optional properties:
+- clocks: Reference to the crypto engine clock.
+- dma-mask: The address mask limitation. Defaults to 64.
+
+Example:
+
+	crypto: crypto at 800000 {
+		compatible = "inside-secure,safexcel-eip197";
+		reg = <0x800000 0x200000>;
+		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
+				  "eip";
+		clocks = <&cpm_syscon0 1 26>;
+		dma-mask = <0xff 0xffffffff>;
+		status = "disabled";
+	};

Signature · 1 line

2.9.4

Signature · 10 lines

Antoine T?nart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Herbert Xu

maintainer

2017-06-20 03:37 UTC #3 lore raw

PATCH v6 1/5 Documentation/bindings: Document the SafeXel cryptographic engine driver

Quoted 10 lines · Antoine Tenart

Hi Herbert,
Quoted 4 lines · Antoine Tenart
The Inside Secure Safexcel cryptographic engine is found on some Marvell SoCs (7k/8k). Document the bindings used by its driver.
Signed-off-by Antoine Tenart <[email protected]>
Since you applied the Safexcel crypto driver patch, I think you should also apply this patch adding the corresponding bindings documentation.

OK I've restored it in the patch queue.

Cheers,

Signature · 3 lines

Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Antoine Tenart

author

2017-06-20 06:21 UTC #4 lore raw

PATCH v6 1/5 Documentation/bindings: Document the SafeXel cryptographic engine driver

Quoted 11 lines · Herbert Xu

Quoted 8 lines · Antoine Tenart
Quoted 4 lines · Antoine Tenart
The Inside Secure Safexcel cryptographic engine is found on some Marvell SoCs (7k/8k). Document the bindings used by its driver.
Signed-off-by Antoine Tenart <[email protected]>
Since you applied the Safexcel crypto driver patch, I think you should also apply this patch adding the corresponding bindings documentation.
OK I've restored it in the patch queue.

Thanks!
Antoine

Signature · 10 lines

Antoine T?nart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Antoine Tenart

author

2017-05-24 14:10 UTC #5 lore raw

PATCH v6 2/5 arm64: marvell: dts: fix interrupts in 7k/8k crypto nodes

In reply to Antoine Tenart

The cryptographic engine nodes have an interrupt which is configured as both edge and level, which makes no sense at all. Fix this by configuring it the right way (level).

Signed-off-by Antoine Tenart <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 3 +--
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -2

index ac8df5201cd6..b4bc42ece754 100644
@@ -231,8 +231,7 @@
 			cpm_crypto: crypto at 800000 {
 				compatible = "inside-secure,safexcel-eip197";
 				reg = <0x800000 0x200000>;
-				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
-				| IRQ_TYPE_LEVEL_HIGH)>,
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +1 -2

index 7740a75a8230..6e2058847ddc 100644
@@ -221,8 +221,7 @@
 			cps_crypto: crypto at 800000 {
 				compatible = "inside-secure,safexcel-eip197";
 				reg = <0x800000 0x200000>;
-				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
-				| IRQ_TYPE_LEVEL_HIGH)>,
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,

Signature · 1 line

2.9.4

Gregory CLEMENT

2017-05-24 15:13 UTC #6 lore raw

PATCH v6 2/5 arm64: marvell: dts: fix interrupts in 7k/8k crypto nodes

Hi Antoine,

Quoted 5 lines · Antoine Tenart

The cryptographic engine nodes have an interrupt which is configured as both edge and level, which makes no sense at all. Fix this by configuring it the right way (level).
Signed-off-by Antoine Tenart <[email protected]>

Applied on mvebu/fixes

Thanks,

Gregory

Quoted 36 lines

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 3 +--
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -2

index ac8df5201cd6..b4bc42ece754 100644
@@ -231,8 +231,7 @@
 			cpm_crypto: crypto at 800000 {
 				compatible = "inside-secure,safexcel-eip197";
 				reg = <0x800000 0x200000>;
-				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
-				| IRQ_TYPE_LEVEL_HIGH)>,
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +1 -2

index 7740a75a8230..6e2058847ddc 100644
@@ -221,8 +221,7 @@
 			cps_crypto: crypto at 800000 {
 				compatible = "inside-secure,safexcel-eip197";
 				reg = <0x800000 0x200000>;
-				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
-				| IRQ_TYPE_LEVEL_HIGH)>,
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,

Signature · 1 line

2.9.4

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Antoine Tenart

author

2017-05-24 14:10 UTC #7 lore raw

PATCH v6 3/5 arm64: marvell: dts: add dma-mask in crypto nodes for 7k/8k

In reply to Antoine Tenart

The EIP197 cryptographic engine supports 64 bits address width but is limited to 40 bits on 7k/8k. Add a dma-mask property in the cryptographic engine nodes to reflect this.

Signed-off-by Antoine Tenart <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 +
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 1 +
 2 files changed, 2 insertions(+)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -0

index b4bc42ece754..434d8a806ffa 100644
@@ -240,6 +240,7 @@
 				interrupt-names = "mem", "ring0", "ring1",
 				"ring2", "ring3", "eip";
 				clocks = <&cpm_syscon0 1 26>;
+				dma-mask = <0xff 0xffffffff>;
 				status = "disabled";
 			};
 		};

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +1 -0

index 6e2058847ddc..17ca94a5d6b4 100644
@@ -230,6 +230,7 @@
 				interrupt-names = "mem", "ring0", "ring1",
 						  "ring2", "ring3", "eip";
 				clocks = <&cps_syscon0 1 26>;
+				dma-mask = <0xff 0xffffffff>;
 				status = "disabled";
 			};
 		};

Signature · 1 line

2.9.4

Gregory CLEMENT

2017-06-13 08:30 UTC #8 lore raw

PATCH v6 3/5 arm64: marvell: dts: add dma-mask in crypto nodes for 7k/8k

Hi Antoine,

Quoted 5 lines · Antoine Tenart

The EIP197 cryptographic engine supports 64 bits address width but is limited to 40 bits on 7k/8k. Add a dma-mask property in the cryptographic engine nodes to reflect this.
Signed-off-by Antoine Tenart <[email protected]>

Applied on mvebu/dt64

Thanks,

Gregory

Quoted 32 lines

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 +
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 1 +
 2 files changed, 2 insertions(+)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -0

index b4bc42ece754..434d8a806ffa 100644
@@ -240,6 +240,7 @@
 				interrupt-names = "mem", "ring0", "ring1",
 				"ring2", "ring3", "eip";
 				clocks = <&cpm_syscon0 1 26>;
+				dma-mask = <0xff 0xffffffff>;
 				status = "disabled";
 			};
 		};

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +1 -0

index 6e2058847ddc..17ca94a5d6b4 100644
@@ -230,6 +230,7 @@
 				interrupt-names = "mem", "ring0", "ring1",
 						  "ring2", "ring3", "eip";
 				clocks = <&cps_syscon0 1 26>;
+				dma-mask = <0xff 0xffffffff>;
 				status = "disabled";
 			};
 		};

Signature · 1 line

2.9.4

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Antoine Tenart

author

2017-05-24 14:10 UTC #9 lore raw

PATCH v6 4/5 crypto: inside-secure: add SafeXcel EIP197 crypto engine driver

In reply to Antoine Tenart

Add support for Inside Secure SafeXcel EIP197 cryptographic engine, which can be found on Marvell Armada 7k and 8k boards. This driver currently implements: ecb(aes), cbc(aes), sha1, sha224, sha256 and hmac(sah1) algorithms.

Two firmwares are needed for this engine to work. Their are mostly used for more advanced operations than the ones supported (as of now), but we still need them to pass the data to the internal cryptographic engine.

Signed-off-by Antoine Tenart <[email protected]>

---
 drivers/crypto/Kconfig                         |   17 +
 drivers/crypto/Makefile                        |    1 +
 drivers/crypto/inside-secure/Makefile          |    2 +
 drivers/crypto/inside-secure/safexcel.c        |  930 +++++++++++++++++++++
 drivers/crypto/inside-secure/safexcel.h        |  572 +++++++++++++
 drivers/crypto/inside-secure/safexcel_cipher.c |  556 +++++++++++++
 drivers/crypto/inside-secure/safexcel_hash.c   | 1045 ++++++++++++++++++++++++
 drivers/crypto/inside-secure/safexcel_ring.c   |  157 ++++
 8 files changed, 3280 insertions(+)
 create mode 100644 drivers/crypto/inside-secure/Makefile
 create mode 100644 drivers/crypto/inside-secure/safexcel.c
 create mode 100644 drivers/crypto/inside-secure/safexcel.h
 create mode 100644 drivers/crypto/inside-secure/safexcel_cipher.c
 create mode 100644 drivers/crypto/inside-secure/safexcel_hash.c
 create mode 100644 drivers/crypto/inside-secure/safexcel_ring.c

drivers/crypto/Kconfig +17 -0

index fb1e60f5002e..9cf41cc846bb 100644
@@ -643,4 +643,21 @@ config CRYPTO_DEV_BCM_SPU
 
 source "drivers/crypto/stm32/Kconfig"
 
+config CRYPTO_DEV_SAFEXCEL
+	tristate "Inside Secure's SafeXcel cryptographic engine driver"
+	depends on HAS_DMA && OF
+	depends on (ARM64 && ARCH_MVEBU) || (COMPILE_TEST && 64BIT)
+	select CRYPTO_AES
+	select CRYPTO_BLKCIPHER
+	select CRYPTO_HASH
+	select CRYPTO_HMAC
+	select CRYPTO_SHA1
+	select CRYPTO_SHA256
+	select CRYPTO_SHA512
+	help
+	  This driver interfaces with the SafeXcel EIP-197 cryptographic engine
+	  designed by Inside Secure. Select this if you want to use CBC/ECB
+	  chain mode, AES cipher mode and SHA1/SHA224/SHA256/SHA512 hash
+	  algorithms.
+
 endif # CRYPTO_HW

drivers/crypto/Makefile +1 -0

index 463f33592d93..67572e4afaae 100644
@@ -39,3 +39,4 @@ obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
 obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
 obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
+obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/

drivers/crypto/inside-secure/Makefile new file +2 -0

new file mode 100644
index 000000000000..302f07dde98c
@@ -0,0 +1,2 @@
+obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += crypto_safexcel.o
+crypto_safexcel-objs := safexcel.o safexcel_ring.o safexcel_cipher.o safexcel_hash.o

drivers/crypto/inside-secure/safexcel.c new file +930 -0

930 lines not on this page · raw message

drivers/crypto/inside-secure/safexcel.h new file +572 -0

572 lines not on this page · raw message

drivers/crypto/inside-secure/safexcel_cipher.c new file +556 -0

556 lines not on this page · raw message

drivers/crypto/inside-secure/safexcel_hash.c new file +1045 -0

915 lines not on this page · raw message

drivers/crypto/inside-secure/safexcel_ring.c new file +157 -0

157 lines not on this page · raw message

The rest of this diff is not shown. View the raw message.

Signature · 1 line

2.9.4

Part of the diff is not shown here. View the raw message.

PrasannaKumar Muralidharan

2017-05-28 05:39 UTC #10 lore raw

PATCH v6 4/5 crypto: inside-secure: add SafeXcel EIP197 crypto engine driver

Hi Antonie,

Quoted 10 lines · Antoine Tenart

Add support for Inside Secure SafeXcel EIP197 cryptographic engine, which can be found on Marvell Armada 7k and 8k boards. This driver currently implements: ecb(aes), cbc(aes), sha1, sha224, sha256 and hmac(sah1) algorithms.
Two firmwares are needed for this engine to work. Their are mostly used for more advanced operations than the ones supported (as of now), but we still need them to pass the data to the internal cryptographic engine.
Signed-off-by Antoine Tenart <[email protected]>

As you have got help from other people for testing, wouldn't it be nice to add tested-by tag?

Regards,
PrasannaKumar

Antoine Tenart

author

2017-05-29 09:21 UTC #11 lore raw

PATCH v6 4/5 crypto: inside-secure: add SafeXcel EIP197 crypto engine driver

Hello,

Quoted 7 lines · PrasannaKumar Muralidharan

Quoted 5 lines · Antoine Tenart
Add support for Inside Secure SafeXcel EIP197 cryptographic engine, which can be found on Marvell Armada 7k and 8k boards. This driver currently implements: ecb(aes), cbc(aes), sha1, sha224, sha256 and hmac(sah1) algorithms.

Quoted 8 lines

Quoted 5 lines
Two firmwares are needed for this engine to work. Their are mostly used for more advanced operations than the ones supported (as of now), but we still need them to pass the data to the internal cryptographic engine.
Signed-off-by Antoine Tenart <[email protected]>
As you have got help from other people for testing, wouldn't it be nice to add tested-by tag?

Well, they're listed as authors of the driver: not only they helped to test it but they developed parts of it. The tested-by tag doesn't apply here.

Thanks,
Antoine

Signature · 10 lines

Antoine T?nart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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PrasannaKumar Muralidharan

2017-05-29 09:42 UTC #12 lore raw

PATCH v6 4/5 crypto: inside-secure: add SafeXcel EIP197 crypto engine driver

Quoted 6 lines · Antoine Tenart

Quoted 2 lines
As you have got help from other people for testing, wouldn't it be nice to add tested-by tag?
Well, they're listed as authors of the driver: not only they helped to test it but they developed parts of it. The tested-by tag doesn't apply here.

Makes sense.

Regards,
PrasannaKumar

Herbert Xu

maintainer

2017-06-10 04:16 UTC #13 lore raw

PATCH v6 4/5 crypto: inside-secure: add SafeXcel EIP197 crypto engine driver

In reply to Antoine Tenart

Quoted 10 lines · Antoine Tenart

Add support for Inside Secure SafeXcel EIP197 cryptographic engine, which can be found on Marvell Armada 7k and 8k boards. This driver currently implements: ecb(aes), cbc(aes), sha1, sha224, sha256 and hmac(sah1) algorithms.
Two firmwares are needed for this engine to work. Their are mostly used for more advanced operations than the ones supported (as of now), but we still need them to pass the data to the internal cryptographic engine.
Signed-off-by Antoine Tenart <[email protected]>

Patch applied. Thanks.

Signature · 3 lines

Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Antoine Tenart

author

2017-05-24 14:10 UTC #14 lore raw

PATCH v6 5/5 MAINTAINERS: add a maintainer for the Inside Secure crypto driver

In reply to Antoine Tenart

A new cryptographic engine driver was added in drivers/crypto/inside-secure. Add myself as a maintainer for this driver.

Signed-off-by Antoine Tenart <[email protected]>

---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)

MAINTAINERS +6 -0

index f7d568b8f133..1f2017604f16 100644
@@ -6602,6 +6602,12 @@ F:	Documentation/input/multi-touch-protocol.rst
 F:	drivers/input/input-mt.c
 K:	\b(ABS|SYN)_MT_
 
+INSIDE SECURE CRYPTO DRIVER
+M:	Antoine Tenart <[email protected]>
+F:	drivers/crypto/inside-secure/
+S:	Maintained
+L:	linux-crypto at vger.kernel.org
+
 INTEL ASoC BDW/HSW DRIVERS
 M:	Jie Yang <[email protected]>
 L:	alsa-devel at alsa-project.org (moderated for non-subscribers)

Signature · 1 line

2.9.4

Herbert Xu

maintainer

2017-06-10 04:16 UTC #15 lore raw

PATCH v6 5/5 MAINTAINERS: add a maintainer for the Inside Secure crypto driver

Quoted 5 lines · Antoine Tenart

A new cryptographic engine driver was added in drivers/crypto/inside-secure. Add myself as a maintainer for this driver.
Signed-off-by Antoine Tenart <[email protected]>

Patch applied. Thanks.

Signature · 3 lines

Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt