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ARM: dts: add GSBI8 defines to the MSM8660 family

PATCH New Linus Walleij 4 participants 4 messages May 15, 2017 – Jun 6, 2017

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Linus Walleij

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#0 lore raw

PATCH 1/2 ARM: dts: add GSBI8 defines to the MSM8660 family

This defines the memory location and interrupt used by the GSBI8 I2C adapter on the MSM8660 SoCs. We add it as "disabled" by default so that boards using this I2C can enable it.

Signed-off-by Linus Walleij <[email protected]>
---
 arch/arm/boot/dts/qcom-msm8660.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
arch/arm/boot/dts/qcom-msm8660.dtsi +25 -0
index 747669a62aa8..a53c0f9970bd 100644
@@ -107,6 +107,31 @@
 			reg = <0x900000 0x4000>;
 		};
 
+
+		gsbi8: gsbi at 19800000 {
+			compatible = "qcom,gsbi-v1.0.0";
+			cell-index = <12>;
+			reg = <0x19800000 0x100>;
+			clocks = <&gcc GSBI8_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			syscon-tcsr = <&tcsr>;
+
+			gsbi8_i2c: i2c at 19880000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x19880000 0x1000>;
+				interrupts = <0 161 IRQ_TYPE_NONE>;
+				clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
+				clock-names = "core", "iface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
 		gsbi12: gsbi at 19c00000 {
 			compatible = "qcom,gsbi-v1.0.0";
 			cell-index = <12>;
Signature · 1 line
2.9.3
#1 lore raw

PATCH 1/2 ARM: dts: add GSBI8 defines to the MSM8660 family

Quoted 4 lines · Linus Walleij

This defines the memory location and interrupt used by the GSBI8 I2C adapter on the MSM8660 SoCs. We add it as "disabled" by default so that boards using this I2C can enable it.

Acked-by Bjorn Andersson <[email protected]>

Regards,
Bjorn

#2 lore raw

PATCH 1/2 ARM: dts: add GSBI8 defines to the MSM8660 family

In reply to Linus Walleij
Quoted 15 lines · Linus Walleij
arch/arm/boot/dts/qcom-msm8660.dtsi +7 -0
index 747669a62aa8..a53c0f9970bd 100644
@@ -107,6 +107,31 @@
 			reg = <0x900000 0x4000>;
 		};
 
+
+		gsbi8: gsbi at 19800000 {
+			compatible = "qcom,gsbi-v1.0.0";
+			cell-index = <12>;
+			reg = <0x19800000 0x100>;
+			clocks = <&gcc GSBI8_H_CLK>;
+			clock-names = "iface";

arch/arm/boot/dts/qcom-msm8660.dtsi line 126

Quoted 10 lines
arch/arm/boot/dts/qcom-msm8660.dtsi +10 -0
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			syscon-tcsr = <&tcsr>;
+
+			gsbi8_i2c: i2c at 19880000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x19880000 0x1000>;
+				interrupts = <0 161 IRQ_TYPE_NONE>;

interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>?

Quoted 1 line
arch/arm/boot/dts/qcom-msm8660.dtsi +1 -0
+				clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
Signature · 2 lines
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#3 lore raw

PATCH 1/2 ARM: dts: add GSBI8 defines to the MSM8660 family

Quoted 20 lines · Stephen Boyd
Quoted 19 lines · Linus Walleij
arch/arm/boot/dts/qcom-msm8660.dtsi +11 -0
index 747669a62aa8..a53c0f9970bd 100644
@@ -107,6 +107,31 @@
 			reg = <0x900000 0x4000>;
 		};
 
+
+		gsbi8: gsbi at 19800000 {
+			compatible = "qcom,gsbi-v1.0.0";
+			cell-index = <12>;
+			reg = <0x19800000 0x100>;
+			clocks = <&gcc GSBI8_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
Quoted 8 lines

arch/arm/boot/dts/qcom-msm8660.dtsi line 126

Quoted 6 lines
arch/arm/boot/dts/qcom-msm8660.dtsi +6 -0
+			syscon-tcsr = <&tcsr>;
+
+			gsbi8_i2c: i2c at 19880000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x19880000 0x1000>;
+				interrupts = <0 161 IRQ_TYPE_NONE>;

interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>?

I'll fix this up. No need for resend