Big work on sunxi DW DRAM controllers and some new DDR type support

PATCH New Icenowy Zheng 3 participants 17 messages Jun 3, 2017 – Jun 8, 2017

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm/Allwinner sunXi SoC support

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Icenowy Zheng

author

2017-06-03 09:10 UTC #0 lore raw

v2 cover Big work on sunxi DW DRAM controllers and some new DDR type support

This patchset contains several works on the sunxi DesignWare DRAM controllers.

The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers.

The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit).

The 4th patch adds bank detection code, in order to support some DDR2 chips.

The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3.

The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled.

The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip.

The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)

The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3.

Icenowy Zheng (12):
sunxi: makes an invisible option for H3-like DRAM controllers
sunxi: Rename bus-width related macros in H3 DRAM code
sunxi: add option for 16-bit DW DRAM controller
sunxi: add bank detection code to H3 DRAM initialization code
sunxi: Add selective DRAM type and timing
sunxi: enable dual rank detection in DesignWare-like DRAM code
sunxi: add support for the DDR2 in V3s SoC
sunxi: add support for V3s DRAM controller
sunxi: enable DRAM initialization and SPL for V3s SoC
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM
controller
sunxi: add LPDDR3 timing from stock boot0
sunxi: add a defconfig for SoPine w/ official baseboard

 arch/arm/include/asm/arch-sunxi/dram.h             |   6 +-
 .../{dram_sun8i_h3.h => dram_sunxi_dw.h}           |  36 +++-
 arch/arm/mach-sunxi/Kconfig                        |  75 ++++++++-
 arch/arm/mach-sunxi/Makefile                       |   5 +-
 .../{dram_sun8i_h3.c => dram_sunxi_dw.c}           | 187 +++++++--------------
 arch/arm/mach-sunxi/dram_timings/Makefile          |   3 +
 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c        |  84 +++++++++
 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c       |  87 ++++++++++
 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c    |  83 +++++++++
 configs/sopine_baseboard_defconfig                 |  22 +++
 10 files changed, 453 insertions(+), 135 deletions(-)
 rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (86%)
 rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (84%)
 create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c
 create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
 create mode 100644 configs/sopine_baseboard_defconfig

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #1 lore raw

PATCH v2 1/12 sunxi: makes an invisible option for H3-like DRAM controllers

From: Icenowy Zheng <[email protected]>

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c.

Add a invisible option for easier DRAM initialization code reuse.

Signed-off-by Icenowy Zheng <[email protected]>

Acked-by Maxime Ripard <[email protected]>

---
Changes in v2:
- Rebased on newest sunxi/next.

 arch/arm/include/asm/arch-sunxi/dram.h                         |  6 ++----
 .../asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h}        |  0
 arch/arm/mach-sunxi/Kconfig                                    | 10 ++++++++++
 arch/arm/mach-sunxi/Makefile                                   |  4 +---
 arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c}       |  0
 5 files changed, 13 insertions(+), 7 deletions(-)
 rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (100%)
 rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (100%)

arch/arm/include/asm/arch-sunxi/dram.h +2 -4

index f452f889f9..80abac95b8 100644
@@ -24,10 +24,8 @@
 #include <asm/arch/dram_sun8i_a33.h>
 #elif defined(CONFIG_MACH_SUN8I_A83T)
 #include <asm/arch/dram_sun8i_a83t.h>
-#elif defined(CONFIG_MACH_SUNXI_H3_H5) || \
-      defined(CONFIG_MACH_SUN8I_R40) || \
-      defined(CONFIG_MACH_SUN50I)
-#include <asm/arch/dram_sun8i_h3.h>
+#elif defined(CONFIG_SUNXI_DRAM_DW)
+#include <asm/arch/dram_sunxi_dw.h>
 #elif defined(CONFIG_MACH_SUN9I)
 #include <asm/arch/dram_sun9i.h>
 #else

arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h renamed from arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h +0 -0

similarity index 100%
rename from arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
rename to arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h

arch/arm/mach-sunxi/Kconfig +10 -0

index 7ced838d6a..11da1ab738 100644
@@ -29,11 +29,19 @@ config SUNXI_GEN_SUN6I
 	separate ahb reset control registers, custom pmic bus, new style
 	watchdog, etc.
 
+config SUNXI_DRAM_DW
+	bool
+	---help---
+	Select this for sunxi SoCs which uses a DRAM controller like the
+	DesignWare controller used in H3, mainly SoCs after H3, which do
+	not have official open-source DRAM initialization code, but can
+	use modified H3 DRAM initialization code.
 
 config MACH_SUNXI_H3_H5
 	bool
 	select DM_I2C
 	select SUNXI_DE2
+	select SUNXI_DRAM_DW
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL

@@ -118,6 +126,7 @@ config MACH_SUN8I_R40
 	select ARCH_SUPPORT_PSCI
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
+	select SUNXI_DRAM_DW
 
 config MACH_SUN8I_V3S
 	bool "sun8i (Allwinner V3s)"

@@ -143,6 +152,7 @@ config MACH_SUN50I
 	select SUNXI_GEN_SUN6I
 	select SUNXI_HIGH_SRAM
 	select SUPPORT_SPL
+	select SUNXI_DRAM_DW
 	select FIT
 	select SPL_LOAD_FIT

arch/arm/mach-sunxi/Makefile +1 -3

index 5510aa5435..41cee26765 100644
@@ -48,8 +48,6 @@ obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN8I_A23)	+= dram_sun8i_a23.o
 obj-$(CONFIG_MACH_SUN8I_A33)	+= dram_sun8i_a33.o
 obj-$(CONFIG_MACH_SUN8I_A83T)	+= dram_sun8i_a83t.o
-obj-$(CONFIG_MACH_SUNXI_H3_H5)	+= dram_sun8i_h3.o
-obj-$(CONFIG_MACH_SUN8I_R40)	+= dram_sun8i_h3.o
+obj-$(CONFIG_SUNXI_DRAM_DW)	+= dram_sunxi_dw.o
 obj-$(CONFIG_MACH_SUN9I)	+= dram_sun9i.o
-obj-$(CONFIG_MACH_SUN50I)	+= dram_sun8i_h3.o
 endif

arch/arm/mach-sunxi/dram_sunxi_dw.c renamed from arch/arm/mach-sunxi/dram_sun8i_h3.c +0 -0

similarity index 100%
rename from arch/arm/mach-sunxi/dram_sun8i_h3.c
rename to arch/arm/mach-sunxi/dram_sunxi_dw.c

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #2 lore raw

PATCH v2 2/12 sunxi: Rename bus-width related macros in H3 DRAM code

In reply to Icenowy Zheng

From: Icenowy Zheng <[email protected]>

The DesignWare DRAM controller used by H3 and newer SoCs use a bit to identify whether the DRAM is half-width.

As H3 itself come with 32-bit DRAM, the two modes of the bit used to be named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM they're really 8-bit and 16-bit.

Rename the bit's macro, and also rename the variable name in dram_sun8i_h3.c.

This commit do not add 16-bit DRAM controller support, but the support will be introduced in next commit.

Signed-off-by Icenowy Zheng <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h |  6 +++---
 arch/arm/mach-sunxi/dram_sunxi_dw.c             | 11 ++++++-----
 2 files changed, 9 insertions(+), 8 deletions(-)

arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +3 -3

index 2770986b61..d301ac95c3 100644
@@ -53,9 +53,9 @@ struct sunxi_mctl_com_reg {
 #define MCTL_CR_SEQUENTIAL	(0x1 << 15)
 #define MCTL_CR_INTERLEAVED	(0x0 << 15)
 
-#define MCTL_CR_32BIT		(0x1 << 12)
-#define MCTL_CR_16BIT		(0x0 << 12)
-#define MCTL_CR_BUS_WIDTH(x)	((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT)
+#define MCTL_CR_FULL_WIDTH	(0x1 << 12)
+#define MCTL_CR_HALF_WIDTH	(0x0 << 12)
+#define MCTL_CR_BUS_FULL_WIDTH(x)	((x) << 12)
 
 #define MCTL_CR_PAGE_SIZE(x)	((fls(x) - 4) << 8)
 #define MCTL_CR_ROW_BITS(x)	(((x) - 1) << 4)

arch/arm/mach-sunxi/dram_sunxi_dw.c +6 -5

index 2d12661a14..77fa6c2889 100644
@@ -28,7 +28,7 @@
 #define LINES_PER_BYTE_LANE	(BITS_PER_BYTE + 3)
 struct dram_para {
 	u16 page_size;
-	u8 bus_width;
+	u8 bus_full_width;
 	u8 dual_rank;
 	u8 row_bits;
 	const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];

@@ -440,7 +440,8 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 
 	writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
-	       MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
+	       MCTL_CR_EIGHT_BANKS |
+	       MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
 	       (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
 	       MCTL_CR_PAGE_SIZE(para->page_size) |
 	       MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);

@@ -578,7 +579,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 	}
 
 	/* set half DQ */
-	if (para->bus_width != 32) {
+	if (!para->bus_full_width) {
 		writel(0x0, &mctl_ctl->dx[2].gcr);
 		writel(0x0, &mctl_ctl->dx[3].gcr);
 	}

@@ -622,7 +623,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 		    ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) {
 			writel(0x0, &mctl_ctl->dx[2].gcr);
 			writel(0x0, &mctl_ctl->dx[3].gcr);
-			para->bus_width = 16;
+			para->bus_full_width = 0;
 		}
 
 		mctl_set_cr(socid, para);

@@ -758,7 +759,7 @@ unsigned long sunxi_dram_init(void)
 
 	struct dram_para para = {
 		.dual_rank = 0,
-		.bus_width = 32,
+		.bus_full_width = 1,
 		.row_bits = 15,
 		.page_size = 4096,

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #3 lore raw

PATCH v2 3/12 sunxi: add option for 16-bit DW DRAM controller

In reply to Icenowy Zheng

From: Icenowy Zheng <[email protected]>

Some Allwinner SoCs features a DesignWare-like controller with only 16 bit bus width.

Add support for them.

Signed-off-by Icenowy Zheng <[email protected]>

---
Changes in v2:
- Rebased on newest sunxi/next.

 arch/arm/mach-sunxi/Kconfig         | 17 +++++++++++++++++
 arch/arm/mach-sunxi/dram_sunxi_dw.c | 33 +++++++++++++++++++++++++++++----
 2 files changed, 46 insertions(+), 4 deletions(-)

arch/arm/mach-sunxi/Kconfig +17 -0

index 11da1ab738..8b8fc20a51 100644
@@ -37,11 +37,26 @@ config SUNXI_DRAM_DW
 	not have official open-source DRAM initialization code, but can
 	use modified H3 DRAM initialization code.
 
+if SUNXI_DRAM_DW
+config SUNXI_DRAM_DW_16BIT
+	bool
+	---help---
+	Select this for sunxi SoCs with DesignWare DRAM controller and
+	have only 16-bit memory buswidth.
+
+config SUNXI_DRAM_DW_32BIT
+	bool
+	---help---
+	Select this for sunxi SoCs with DesignWare DRAM controller with
+	32-bit memory buswidth.
+endif
+
 config MACH_SUNXI_H3_H5
 	bool
 	select DM_I2C
 	select SUNXI_DE2
 	select SUNXI_DRAM_DW
+	select SUNXI_DRAM_DW_32BIT
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL

@@ -127,6 +142,7 @@ config MACH_SUN8I_R40
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select SUNXI_DRAM_DW
+	select SUNXI_DRAM_DW_32BIT
 
 config MACH_SUN8I_V3S
 	bool "sun8i (Allwinner V3s)"

@@ -153,6 +169,7 @@ config MACH_SUN50I
 	select SUNXI_HIGH_SRAM
 	select SUPPORT_SPL
 	select SUNXI_DRAM_DW
+	select SUNXI_DRAM_DW_32BIT
 	select FIT
 	select SPL_LOAD_FIT

arch/arm/mach-sunxi/dram_sunxi_dw.c +29 -4

index 77fa6c2889..de683a1b63 100644
@@ -380,6 +380,13 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
 {
 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
 			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+	int zq_count;
+
+#if defined CONFIG_SUNXI_DRAM_DW_16BIT
+	zq_count = 4;
+#else
+	zq_count = 6;
+#endif
 
 	if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
 	    (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {

@@ -408,7 +415,7 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
 
 		writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
 
-		for (i = 0; i < 6; i++) {
+		for (i = 0; i < zq_count; i++) {
 			u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
 
 			writel((zq << 20) | (zq << 16) | (zq << 12) |

@@ -430,7 +437,9 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
 
 		writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
 		writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
-		writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
+		if (zq_count > 4)
+			writel((zq_val[5] << 16) | zq_val[4],
+			       &mctl_ctl->zqdr[2]);
 	}
 }

@@ -580,8 +589,14 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 
 	/* set half DQ */
 	if (!para->bus_full_width) {
+#if defined CONFIG_SUNXI_DRAM_DW_32BIT
 		writel(0x0, &mctl_ctl->dx[2].gcr);
 		writel(0x0, &mctl_ctl->dx[3].gcr);
+#elif defined CONFIG_SUNXI_DRAM_DW_16BIT
+		writel(0x0, &mctl_ctl->dx[1].gcr);
+#else
+#error Unsupported DRAM bus width!
+#endif
 	}
 
 	/* data training configuration */

@@ -612,19 +627,29 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 	/* detect ranks and bus width */
 	if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
 		/* only one rank */
-		if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) ||
-		    ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2)) {
+		if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2)
+#if defined CONFIG_SUNXI_DRAM_DW_32BIT
+		    || ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2)
+#endif
+		    ) {
 			clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
 			para->dual_rank = 0;
 		}
 
 		/* only half DQ width */
+#if defined CONFIG_SUNXI_DRAM_DW_32BIT
 		if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) ||
 		    ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) {
 			writel(0x0, &mctl_ctl->dx[2].gcr);
 			writel(0x0, &mctl_ctl->dx[3].gcr);
 			para->bus_full_width = 0;
 		}
+#elif defined CONFIG_SUNXI_DRAM_DW_16BIT
+		if ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x1) {
+			writel(0x0, &mctl_ctl->dx[1].gcr);
+			para->bus_full_width = 0;
+		}
+#endif
 
 		mctl_set_cr(socid, para);
 		udelay(20);

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #4 lore raw

PATCH v2 4/12 sunxi: add bank detection code to H3 DRAM initialization code

In reply to Icenowy Zheng

From: Icenowy Zheng <[email protected]>

Some DDR2 DRAM have only four banks, not eight.

Add code to detect this situation.

Signed-off-by Icenowy Zheng <[email protected]>

---
 arch/arm/mach-sunxi/dram_sunxi_dw.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

arch/arm/mach-sunxi/dram_sunxi_dw.c +15 -4

index de683a1b63..3f54c8ee09 100644
@@ -31,6 +31,7 @@ struct dram_para {
 	u8 bus_full_width;
 	u8 dual_rank;
 	u8 row_bits;
+	u8 bank_bits;
 	const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
 	const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
 	const u8 ac_delays[31];

@@ -449,7 +450,7 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 
 	writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
-	       MCTL_CR_EIGHT_BANKS |
+	       (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
 	       MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
 	       (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
 	       MCTL_CR_PAGE_SIZE(para->page_size) |

@@ -689,10 +690,19 @@ static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
 	/* detect row address bits */
 	para->page_size = 512;
 	para->row_bits = 16;
+	para->bank_bits = 2;
 	mctl_set_cr(socid, para);
 
 	for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
-		if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
+		if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size))
+			break;
+
+	/* detect bank address bits */
+	para->bank_bits = 3;
+	mctl_set_cr(socid, para);
+
+	for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++)
+		if (mctl_mem_matches((1 << para->bank_bits) * para->page_size))
 			break;
 
 	/* detect page size */

@@ -786,6 +796,7 @@ unsigned long sunxi_dram_init(void)
 		.dual_rank = 0,
 		.bus_full_width = 1,
 		.row_bits = 15,
+		.bank_bits = 3,
 		.page_size = 4096,
 
 #if defined(CONFIG_MACH_SUN8I_H3)

@@ -850,6 +861,6 @@ unsigned long sunxi_dram_init(void)
 	mctl_auto_detect_dram_size(socid, &para);
 	mctl_set_cr(socid, &para);
 
-	return (1UL << (para.row_bits + 3)) * para.page_size *
-						(para.dual_rank ? 2 : 1);
+	return (1UL << (para.row_bits + para.bank_bits)) * para.page_size *
+	       (para.dual_rank ? 2 : 1);
 }

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #5 lore raw

PATCH v2 5/12 sunxi: Add selective DRAM type and timing

In reply to Icenowy Zheng

From: Icenowy Zheng <[email protected]>

DRAM chip varies, and one code cannot satisfy all DRAMs.

Add options to select a timing set.

Currently only DDR3-1333 (the original set) is added into it.

Signed-off-by Icenowy Zheng <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h |  30 ++++++
 arch/arm/mach-sunxi/Kconfig                     |  18 ++++
 arch/arm/mach-sunxi/Makefile                    |   1 +
 arch/arm/mach-sunxi/dram_sunxi_dw.c             | 119 ++----------------------
 arch/arm/mach-sunxi/dram_timings/Makefile       |   1 +
 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c    |  87 +++++++++++++++++
 6 files changed, 143 insertions(+), 113 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c

arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +30 -0

index d301ac95c3..03fd46b724 100644
@@ -205,4 +205,34 @@ struct sunxi_mctl_ctl_reg {
 #define DXBDLR_WRITE_DELAY(x)	((x) << 8)
 #define DXBDLR_READ_DELAY(x)	((x) << 0)
 
+/*
+ * The delay parameters below allow to allegedly specify delay times of some
+ * unknown unit for each individual bit trace in each of the four data bytes
+ * the 32-bit wide access consists of. Also three control signals can be
+ * adjusted individually.
+ */
+#define BITS_PER_BYTE		8
+#define NR_OF_BYTE_LANES	(32 / BITS_PER_BYTE)
+/* The eight data lines (DQn) plus DM, DQS and DQSN */
+#define LINES_PER_BYTE_LANE	(BITS_PER_BYTE + 3)
+struct dram_para {
+	u16 page_size;
+	u8 bus_full_width;
+	u8 dual_rank;
+	u8 row_bits;
+	u8 bank_bits;
+	const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+	const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+	const u8 ac_delays[31];
+};
+
+static inline int ns_to_t(int nanoseconds)
+{
+	const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+	return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para);
+
 #endif /* _SUNXI_DRAM_SUN8I_H3_H */

arch/arm/mach-sunxi/Kconfig +18 -0

index 8b8fc20a51..3e529470e7 100644
@@ -216,6 +216,24 @@ config ARM_BOOT_HOOK_RMR
 	This allows both the SPL and the U-Boot proper to be entered in
 	either mode and switch to AArch64 if needed.
 
+if SUNXI_DRAM_DW
+config SUNXI_DRAM_DDR3
+	bool
+
+choice
+	prompt "DRAM Type and Timing"
+	default SUNXI_DRAM_DDR3_1333
+
+config SUNXI_DRAM_DDR3_1333
+	bool "DDR3 1333"
+	select SUNXI_DRAM_DDR3
+	---help---
+	This option is the original only supported memory type, which suits
+	many H3/H5/A64 boards available now.
+
+endchoice
+endif
+
 config DRAM_TYPE
 	int "sunxi dram type"
 	depends on MACH_SUN8I_A83T

arch/arm/mach-sunxi/Makefile +1 -0

index 41cee26765..2a3c379b72 100644
@@ -49,5 +49,6 @@ obj-$(CONFIG_MACH_SUN8I_A23)	+= dram_sun8i_a23.o
 obj-$(CONFIG_MACH_SUN8I_A33)	+= dram_sun8i_a33.o
 obj-$(CONFIG_MACH_SUN8I_A83T)	+= dram_sun8i_a83t.o
 obj-$(CONFIG_SUNXI_DRAM_DW)	+= dram_sunxi_dw.o
+obj-$(CONFIG_SUNXI_DRAM_DW)	+= dram_timings/
 obj-$(CONFIG_MACH_SUN9I)	+= dram_sun9i.o
 endif

arch/arm/mach-sunxi/dram_sunxi_dw.c +6 ~~-113~~

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arch/arm/mach-sunxi/dram_timings/Makefile new file +1 -0

new file mode 100644
index 0000000000..7e71c76a5c
@@ -0,0 +1 @@
+obj-$(CONFIG_SUNXI_DRAM_DDR3_1333)	+= ddr3_1333.o

arch/arm/mach-sunxi/dram_timings/ddr3_1333.c new file +87 -0

87 lines not on this page · raw message

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #6 lore raw

PATCH v2 6/12 sunxi: enable dual rank detection in DesignWare-like DRAM code

In reply to Icenowy Zheng

From: Icenowy Zheng <[email protected]>

The DesignWare-like DRAM code used to set the controller defaultly to single rank mode, which makes it not able to detect the second rank.

Set the default value to dual rank, thus the rank detection code can work and finally the rank setting will be the correct value.

Currently we know little about the dual-rank on R40, and the usage of A15 address line seems to be breaking dual-rank support. The only R40 board currently available (Sinovoip Banana Pi M2 Ultra) uses A15 rather than dual-rank, thus we cannot do research for it. So dual rank detection is temporarily disabled on R40.

This change is tested on a Orange Pi One (H3, single rank), a Pine64+ 2GiB version (A64, single rank) , a Pinebook early prototype with DDR3 (A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins on one chip).

Signed-off-by Icenowy Zheng <[email protected]>

---
 arch/arm/mach-sunxi/dram_sunxi_dw.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

arch/arm/mach-sunxi/dram_sunxi_dw.c +3 -1

index a5706423cb..bd606ccc65 100644
@@ -686,7 +686,7 @@ unsigned long sunxi_dram_init(void)
 			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 
 	struct dram_para para = {
-		.dual_rank = 0,
+		.dual_rank = 1,
 		.bus_full_width = 1,
 		.row_bits = 15,
 		.bank_bits = 3,

@@ -719,6 +719,8 @@ unsigned long sunxi_dram_init(void)
 	uint16_t socid = SOCID_H3;
 #elif defined(CONFIG_MACH_SUN8I_R40)
 	uint16_t socid = SOCID_R40;
+	/* Currently we cannot support R40 with dual rank memory */
+	para.dual_rank = 0;
 #elif defined(CONFIG_MACH_SUN50I)
 	uint16_t socid = SOCID_A64;
 #elif defined(CONFIG_MACH_SUN50I_H5)

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #7 lore raw

PATCH v2 7/12 sunxi: add support for the DDR2 in V3s SoC

In reply to Icenowy Zheng

From: Icenowy Zheng <[email protected]>

Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its timing param.

Add support for it.

Signed-off-by Icenowy Zheng <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig                 | 10 ++++
 arch/arm/mach-sunxi/dram_sunxi_dw.c         |  2 +
 arch/arm/mach-sunxi/dram_timings/Makefile   |  1 +
 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c | 84 +++++++++++++++++++++++++++++
 4 files changed, 97 insertions(+)
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c

arch/arm/mach-sunxi/Kconfig +10 -0

index 3e529470e7..1df24cfb39 100644
@@ -220,6 +220,9 @@ if SUNXI_DRAM_DW
 config SUNXI_DRAM_DDR3
 	bool
 
+config SUNXI_DRAM_DDR2
+	bool
+
 choice
 	prompt "DRAM Type and Timing"
 	default SUNXI_DRAM_DDR3_1333

@@ -231,6 +234,13 @@ config SUNXI_DRAM_DDR3_1333
 	This option is the original only supported memory type, which suits
 	many H3/H5/A64 boards available now.
 
+config SUNXI_DRAM_DDR2_V3S
+	bool "DDR2 found in V3s chip"
+	select SUNXI_DRAM_DDR2
+	---help---
+	This option is only for the DDR2 memory chip which is co-packaged in
+	Allwinner V3s SoC.
+
 endchoice
 endif

arch/arm/mach-sunxi/dram_sunxi_dw.c +2 -0

index bd606ccc65..438b4740cd 100644
@@ -340,6 +340,8 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
 	writel(MCTL_CR_BL8 | MCTL_CR_INTERLEAVED |
 #if defined CONFIG_SUNXI_DRAM_DDR3
 	       MCTL_CR_DDR3 | MCTL_CR_2T |
+#elif defined CONFIG_SUNXI_DRAM_DDR2
+	       MCTL_CR_DDR2 | MCTL_CR_2T |
 #else
 #error Unsupported DRAM type!
 #endif

arch/arm/mach-sunxi/dram_timings/Makefile +1 -0

index 7e71c76a5c..a4c9dc556c 100644
@@ -1 +1,2 @@
 obj-$(CONFIG_SUNXI_DRAM_DDR3_1333)	+= ddr3_1333.o
+obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S)	+= ddr2_v3s.o

arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c new file +84 -0

84 lines not on this page · raw message

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #8 lore raw

PATCH v2 8/12 sunxi: add support for V3s DRAM controller

In reply to Icenowy Zheng

From: Icenowy Zheng <[email protected]>

Allwinner V3s features a DRAM controller like the on in H3, but with a DDR2 DRAM.

Add support for it.

Signed-off-by Icenowy Zheng <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig         | 5 ++++-
 arch/arm/mach-sunxi/dram_sunxi_dw.c | 3 +++
 2 files changed, 7 insertions(+), 1 deletion(-)

arch/arm/mach-sunxi/Kconfig +4 -1

index 1df24cfb39..af5cd6da9b 100644
@@ -225,11 +225,13 @@ config SUNXI_DRAM_DDR2
 
 choice
 	prompt "DRAM Type and Timing"
-	default SUNXI_DRAM_DDR3_1333
+	default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
+	default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
 
 config SUNXI_DRAM_DDR3_1333
 	bool "DDR3 1333"
 	select SUNXI_DRAM_DDR3
+	depends on !MACH_SUN8I_V3S
 	---help---
 	This option is the original only supported memory type, which suits
 	many H3/H5/A64 boards available now.

@@ -237,6 +239,7 @@ config SUNXI_DRAM_DDR3_1333
 config SUNXI_DRAM_DDR2_V3S
 	bool "DDR2 found in V3s chip"
 	select SUNXI_DRAM_DDR2
+	depends on MACH_SUN8I_V3S
 	---help---
 	This option is only for the DDR2 memory chip which is co-packaged in
 	Allwinner V3s SoC.

arch/arm/mach-sunxi/dram_sunxi_dw.c +3 -0

index 438b4740cd..20c3055b7a 100644
@@ -723,6 +723,9 @@ unsigned long sunxi_dram_init(void)
 	uint16_t socid = SOCID_R40;
 	/* Currently we cannot support R40 with dual rank memory */
 	para.dual_rank = 0;
+#elif defined(CONFIG_MACH_SUN8I_V3S)
+	/* TODO: set delays and mbus priority for V3s */
+	uint16_t socid = SOCID_H3;
 #elif defined(CONFIG_MACH_SUN50I)
 	uint16_t socid = SOCID_A64;
 #elif defined(CONFIG_MACH_SUN50I_H5)

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #9 lore raw

PATCH v2 9/12 sunxi: enable DRAM initialization and SPL for V3s SoC

In reply to Icenowy Zheng

As we have already support for the DesignWare DRAM controller and the integrated DDR2 chip of V3s, let's enable the SPL support for V3s.

This patch also contains the default DRAM configuration for V3s.

Signed-off-by Icenowy Zheng <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

arch/arm/mach-sunxi/Kconfig +6 -1

index af5cd6da9b..ca6417388a 100644
@@ -151,6 +151,9 @@ config MACH_SUN8I_V3S
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select SUNXI_GEN_SUN6I
+	select SUNXI_DRAM_DW
+	select SUNXI_DRAM_DW_16BIT
+	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN9I

@@ -259,7 +262,8 @@ config DRAM_CLK
 	default 792 if MACH_SUN9I
 	default 648 if MACH_SUN8I_R40
 	default 312 if MACH_SUN6I || MACH_SUN8I
-	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
+		       MACH_SUN8I_V3S
 	default 672 if MACH_SUN50I
 	---help---
 	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),

@@ -279,6 +283,7 @@ config DRAM_ZQ
 	int "sunxi dram zq value"
 	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
 	default 127 if MACH_SUN7I
+	default 14779 if MACH_SUN8I_V3S
 	default 3881979 if MACH_SUN8I_R40
 	default 4145117 if MACH_SUN9I
 	default 3881915 if MACH_SUN50I

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #10 lore raw

PATCH v2 10/12 sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller

In reply to Icenowy Zheng

From: Icenowy Zheng <[email protected]>

Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM chips.

Add support for LPDDR3 DRAM in the DesignWare-like DRAM controller code.

Real LPDDR3 chips' support is not added yet in this commit.

Signed-off-by Icenowy Zheng <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig         | 3 +++
 arch/arm/mach-sunxi/dram_sunxi_dw.c | 2 ++
 2 files changed, 5 insertions(+)

arch/arm/mach-sunxi/Kconfig +3 -0

index ca6417388a..2761915638 100644
@@ -226,6 +226,9 @@ config SUNXI_DRAM_DDR3
 config SUNXI_DRAM_DDR2
 	bool
 
+config SUNXI_DRAM_LPDDR3
+	bool
+
 choice
 	prompt "DRAM Type and Timing"
 	default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S

arch/arm/mach-sunxi/dram_sunxi_dw.c +2 -0

index 20c3055b7a..78b4ffb9c3 100644
@@ -342,6 +342,8 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
 	       MCTL_CR_DDR3 | MCTL_CR_2T |
 #elif defined CONFIG_SUNXI_DRAM_DDR2
 	       MCTL_CR_DDR2 | MCTL_CR_2T |
+#elif defined CONFIG_SUNXI_DRAM_LPDDR3
+	       MCTL_CR_LPDDR3 | MCTL_CR_1T |
 #else
 #error Unsupported DRAM type!
 #endif

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #11 lore raw

PATCH v2 11/12 sunxi: add LPDDR3 timing from stock boot0

In reply to Icenowy Zheng

From: Icenowy Zheng <[email protected]>

As we added LPDDR3 support in the former patch, we need a set of timing info to really enable it.

Add the timing info used by stock boot0.

Signed-off-by Icenowy Zheng <[email protected]>

---
Changes in v2:
- Added some comments suggested by Andre Przywara.

 arch/arm/mach-sunxi/Kconfig                     |  7 +++
 arch/arm/mach-sunxi/dram_timings/Makefile       |  1 +
 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c | 83 +++++++++++++++++++++++++
 3 files changed, 91 insertions(+)
 create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c

arch/arm/mach-sunxi/Kconfig +7 -0

index 2761915638..bd3e7d3b3f 100644
@@ -242,6 +242,13 @@ config SUNXI_DRAM_DDR3_1333
 	This option is the original only supported memory type, which suits
 	many H3/H5/A64 boards available now.
 
+config SUNXI_DRAM_LPDDR3_STOCK
+	bool "LPDDR3 with Allwinner stock configuration"
+	select SUNXI_DRAM_LPDDR3
+	---help---
+	This option is the LPDDR3 timing used by the stock boot0 by
+	Allwinner.
+
 config SUNXI_DRAM_DDR2_V3S
 	bool "DDR2 found in V3s chip"
 	select SUNXI_DRAM_DDR2

arch/arm/mach-sunxi/dram_timings/Makefile +1 -0

index a4c9dc556c..278a8a14cc 100644
@@ -1,2 +1,3 @@
 obj-$(CONFIG_SUNXI_DRAM_DDR3_1333)	+= ddr3_1333.o
+obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK)	+= lpddr3_stock.o
 obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S)	+= ddr2_v3s.o

arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c new file +83 -0

83 lines not on this page · raw message

Signature · 1 line

2.12.2

Icenowy Zheng

author

2017-06-03 09:10 UTC #12 lore raw

PATCH v2 12/12 sunxi: add a defconfig for SoPine w/ official baseboard

In reply to Icenowy Zheng

The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card detect pin of the MicroSD slot is broken, however, it doesn't matter as the design of SoPine didn't allow hot-swapping the MicroSD card (The MicroSD slot is at the back of the SoM, and when the SoM is installed on the baseboard, it's nearly impossible to remove the MicroSD).

The official baseboard of it is a board with nearly the same connectors with the original Pine64+, with the MicroUSB power jack replaced, and at the position of MicroSD slot a eMMC module slot is added.

Add support for SoPine with the official baseboard by adding its defconfig file. It still uses the device tree of Pine64, however, it will change after a proper device tree of SoPine with baseboard is accepted by Linux mainline.

Signed-off-by Icenowy Zheng <[email protected]>

---
 configs/sopine_baseboard_defconfig | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 configs/sopine_baseboard_defconfig

configs/sopine_baseboard_defconfig new file +22 -0

new file mode 100644
index 0000000000..02ffb43d54
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN=""
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y

Signature · 1 line

2.12.2

Jagan Teki

2017-06-08 12:41 UTC #13 lore raw

v2 cover Big work on sunxi DW DRAM controllers and some new DDR type support

In reply to Icenowy Zheng

Quoted 28 lines · Icenowy Zheng

This patchset contains several works on the sunxi DesignWare DRAM controllers.
The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers.
The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit).
The 4th patch adds bank detection code, in order to support some DDR2 chips.
The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3.
The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled.
The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip.
The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3.

Quoted 14 lines

Icenowy Zheng (12):
sunxi: makes an invisible option for H3-like DRAM controllers
sunxi: Rename bus-width related macros in H3 DRAM code
sunxi: add option for 16-bit DW DRAM controller
sunxi: add bank detection code to H3 DRAM initialization code
sunxi: Add selective DRAM type and timing
sunxi: enable dual rank detection in DesignWare-like DRAM code
sunxi: add support for the DDR2 in V3s SoC
sunxi: add support for V3s DRAM controller
sunxi: enable DRAM initialization and SPL for V3s SoC
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM
controller
sunxi: add LPDDR3 timing from stock boot0
sunxi: add a defconfig for SoPine w/ official baseboard

I think you forgot to add MAINTAINERS update which I commented previous, anyway if you're OK I will add and apply the series?

thanks!

Signature · 4 lines

Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

Icenowy Zheng

author

2017-06-08 15:58 UTC #14 lore raw

于 2017年6月8日 GMT+08:00 下午8:41:41, Jagan Teki <[email protected]> 写到:

Quoted 52 lines · Icenowy Zheng

Quoted 5 lines
This patchset contains several works on the sunxi DesignWare DRAM controllers.
The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike
controllers.
Quoted 2 lines
The 2nd and 3rd patches are for supporting 16-bit DW DRAM
controllers,
Quoted 6 lines
in order to add V3s DRAM support (The controller on V3s is 16-bit).
The 4th patch adds bank detection code, in order to support some DDR2 chips.
The 5th patch adds a framework for select DRAM type and timing --
it's
Quoted 4 lines
needed for boards that use DRAM chips rather than DDR3.
The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so
it's
Quoted 3 lines
temporarily disabled.
The 7th~9th patches enables support for DRAM initialization and SPL
for
Quoted 3 lines
the V3s SoC, which integrates a DDR2 chip.
The 10th and 11th patches adds support for LPDDR3, with the stock
boot0
Quoted 1 line
timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram
source)
Quoted 2 lines
The 12th patches adds a defconfig for SoPine w/ official baseboard,
which
Quoted 16 lines
utilizes LPDDR3.
Icenowy Zheng (12):
sunxi: makes an invisible option for H3-like DRAM controllers
sunxi: Rename bus-width related macros in H3 DRAM code
sunxi: add option for 16-bit DW DRAM controller
sunxi: add bank detection code to H3 DRAM initialization code
sunxi: Add selective DRAM type and timing
sunxi: enable dual rank detection in DesignWare-like DRAM code
sunxi: add support for the DDR2 in V3s SoC
sunxi: add support for V3s DRAM controller
sunxi: enable DRAM initialization and SPL for V3s SoC
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM
controller
sunxi: add LPDDR3 timing from stock boot0
sunxi: add a defconfig for SoPine w/ official baseboard

Quoted 2 lines

I think you forgot to add MAINTAINERS update which I commented previous, anyway if you're OK I will add and apply the series?

Of course.

Thanks!

Quoted 2 lines

thanks!

Jagan Teki

2017-06-08 17:10 UTC #15 lore raw

v2 cover Big work on sunxi DW DRAM controllers and some new DDR type support

In reply to Icenowy Zheng

Quoted 28 lines · Icenowy Zheng

This patchset contains several works on the sunxi DesignWare DRAM controllers.
The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers.
The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit).
The 4th patch adds bank detection code, in order to support some DDR2 chips.
The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3.
The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled.
The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip.
The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3.

Quoted 7 lines

Icenowy Zheng (12):
sunxi: makes an invisible option for H3-like DRAM controllers
sunxi: Rename bus-width related macros in H3 DRAM code
sunxi: add option for 16-bit DW DRAM controller
sunxi: add bank detection code to H3 DRAM initialization code
sunxi: Add selective DRAM type and timing
sunxi: enable dual rank detection in DesignWare-like DRAM code

Reviewed-by Jagan Teki <[email protected]>

Quoted 1 line

sunxi: add support for the DDR2 in V3s SoC

Acked-by Jagan Teki <[email protected]>

Quoted 4 lines

sunxi: add support for V3s DRAM controller
sunxi: enable DRAM initialization and SPL for V3s SoC
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM
controller

Reviewed-by Jagan Teki <[email protected]>

Quoted 1 line

sunxi: add LPDDR3 timing from stock boot0

Acked-by Jagan Teki <[email protected]>

Quoted 1 line

sunxi: add a defconfig for SoPine w/ official baseboard

Reviewed-by Jagan Teki <[email protected]>

Tested MMC boot in SoPine.

Tested-by Jagan Teki <[email protected]>

Applied to u-boot-sunxi/master

thanks!

Signature · 4 lines

Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

Siarhei Siamashka

2017-06-08 19:03 UTC #16 lore raw

v2 cover Big work on sunxi DW DRAM controllers and some new DDR type support

In reply to Icenowy Zheng

Quoted 53 lines · On Sat, 3 Jun 2017 17:10:13 +0800 Icenowy Zheng <[email protected]> wrote:

This patchset contains several works on the sunxi DesignWare DRAM controllers.
The 1st patch made an option for H3-like DRAM controllers (DesignWare ones), which can ease further import of alike controllers.
The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers, in order to add V3s DRAM support (The controller on V3s is 16-bit).
The 4th patch adds bank detection code, in order to support some DDR2 chips.
The 5th patch adds a framework for select DRAM type and timing -- it's needed for boards that use DRAM chips rather than DDR3.
The 6th patch enables dual rank detection in the DW DRAM code on SoCs except R40. For R40 the dual rank facility is still not so clear, so it's temporarily disabled.
The 7th~9th patches enables support for DRAM initialization and SPL for the V3s SoC, which integrates a DDR2 chip.
The 10th and 11th patches adds support for LPDDR3, with the stock boot0 timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
The 12th patches adds a defconfig for SoPine w/ official baseboard, which utilizes LPDDR3.
Icenowy Zheng (12):
sunxi: makes an invisible option for H3-like DRAM controllers
sunxi: Rename bus-width related macros in H3 DRAM code
sunxi: add option for 16-bit DW DRAM controller
sunxi: add bank detection code to H3 DRAM initialization code
sunxi: Add selective DRAM type and timing
sunxi: enable dual rank detection in DesignWare-like DRAM code
sunxi: add support for the DDR2 in V3s SoC
sunxi: add support for V3s DRAM controller
sunxi: enable DRAM initialization and SPL for V3s SoC
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM
controller
sunxi: add LPDDR3 timing from stock boot0
sunxi: add a defconfig for SoPine w/ official baseboard
 arch/arm/include/asm/arch-sunxi/dram.h             |   6 +-
 .../{dram_sun8i_h3.h => dram_sunxi_dw.h}           |  36 +++-
 arch/arm/mach-sunxi/Kconfig                        |  75 ++++++++-
 arch/arm/mach-sunxi/Makefile                       |   5 +-
 .../{dram_sun8i_h3.c => dram_sunxi_dw.c}           | 187 +++++++--------------
 arch/arm/mach-sunxi/dram_timings/Makefile          |   3 +
 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c        |  84 +++++++++
 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c       |  87 ++++++++++
 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c    |  83 +++++++++
 configs/sopine_baseboard_defconfig                 |  22 +++

Quoted 9 lines

 10 files changed, 453 insertions(+), 135 deletions(-)
 rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (86%)
 rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (84%)
 create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c
 create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
 create mode 100644 configs/sopine_baseboard_defconfig

I'll have time to review your patchset on the coming weekend. Thanks!

Signature · 2 lines

Best regards,
Siarhei Siamashka