RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
Subsystems (2)
PATCH 1/2 RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
No i.mx6q board uses a 100k pull-down on clock, why should i.mx7d ?
--- arch/arm/boot/dts/imx7d-sdb.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
arch/arm/boot/dts/imx7d-sdb.dts +7 -7
@@ -591,7 +591,7 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_CLK__SD1_CLK 0x09 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
@@ -605,7 +605,7 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_CLK__SD2_CLK 0x09 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
@@ -616,7 +616,7 @@ pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_CLK__SD2_CLK 0x0a MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
@@ -627,7 +627,7 @@ pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_CLK__SD2_CLK 0x0b MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
@@ -639,7 +639,7 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_CLK__SD3_CLK 0x09 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
@@ -655,7 +655,7 @@ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_CLK__SD3_CLK 0x0a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
@@ -671,7 +671,7 @@ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_CLK__SD3_CLK 0x0b MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
Signature · 1 line
2.7.4
PATCH 2/2 RFC: ARM: dts: imx7d-sdb: swap pad settings for USDHCx 50Mhz and 100Mhz
It does not make sense that 100 Mhz pad settings would use a x2 setting and 50 Mhz would use a x4 setting, so swap.
--- arch/arm/boot/dts/imx7d-sdb.dts | 72 ++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 36 deletions(-)
arch/arm/boot/dts/imx7d-sdb.dts +36 -36
@@ -590,31 +590,20 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x09 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x0a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x5a /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x5a /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x5a /* vmmc */ >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x09 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { - fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5a MX7D_PAD_SD2_CLK__SD2_CLK 0x0a MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
@@ -624,6 +613,17 @@ >; }; + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x09 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
@@ -638,22 +638,6 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x09 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5a MX7D_PAD_SD3_CLK__SD3_CLK 0x0a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
@@ -668,6 +652,22 @@ >; }; + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x09 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
Signature · 1 line
2.7.4
PATCH 2/2 RFC: ARM: dts: imx7d-sdb: swap pad settings for USDHCx 50Mhz and 100Mhz
Quoted 4 lines · Troy Kisky
It does not make sense that 100 Mhz pad settings would use a x2 setting and 50 Mhz would use a x4 setting, so swap.
Signed-off-by Troy Kisky <[email protected]>
Add Dong and Frank for this one as well.
Shawn
Quoted 121 lines
--- arch/arm/boot/dts/imx7d-sdb.dts | 72 ++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 36 deletions(-)arch/arm/boot/dts/imx7d-sdb.dts +36
-36@@ -590,31 +590,20 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x09 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x0a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x5a /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x5a /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x5a /* vmmc */ >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x09 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { - fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5a MX7D_PAD_SD2_CLK__SD2_CLK 0x0a MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a@@ -624,6 +613,17 @@ >; }; + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x09 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5b@@ -638,22 +638,6 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x09 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5a MX7D_PAD_SD3_CLK__SD3_CLK 0x0a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a@@ -668,6 +652,22 @@ >; }; + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x09 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5bSignature · 7 lines
2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel at lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 2/2 RFC: ARM: dts: imx7d-sdb: swap pad settings for USDHCx 50Mhz and 100Mhz
Quoted 9 lines
-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Thursday, June 15, 2017 11:40 AM
To: Troy Kisky; A.s. Dong; Frank Li
Cc: shawn.guo at linaro.org; Fabio Estevam; gary.bisson at boundarydevices.com; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 2/2] RFC: ARM: dts: imx7d-sdb: swap pad settings for USDHCx 50Mhz and 100Mhz
Quoted 8 lines
Quoted 4 lines · Troy Kisky
It does not make sense that 100 Mhz pad settings would use a x2 setting and 50 Mhz would use a x4 setting, so swap.
Signed-off-by Troy Kisky <[email protected]>Add Dong and Frank for this one as well.
I'm ok with this one.
But you need double check PATCH 1/2 as CLK part in this one depends on it.
Regards
Dong Aisheng
Quoted 126 lines
Shawn
Quoted 12 lines
--- arch/arm/boot/dts/imx7d-sdb.dts | 72 ++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 36 deletions(-)(quoted diff) +0
-0
b/arch/arm/boot/dts/imx7d-sdb.dtsindex cab9208..70dcbf4 100644arch/arm/boot/dts/imx7d-sdb.dts +0
-0@@ -590,31 +590,20 @@ pinctrl_usdhc1: usdhc1grp {arch/arm/boot/dts/imx7d-sdb.dts line 601
Quoted 10 lines
arch/arm/boot/dts/imx7d-sdb.dts +0
-9fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x09 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /*vmmc */
arch/arm/boot/dts/imx7d-sdb.dts
Quoted 9 lines
arch/arm/boot/dts/imx7d-sdb.dts +9
-0+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x0a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x5a /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x5a /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x5a /*vmmc */
Quoted 91 lines
arch/arm/boot/dts/imx7d-sdb.dts +27
-28>; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x09 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { - fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5a MX7D_PAD_SD2_CLK__SD2_CLK 0x0a MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a@@ -624,6 +613,17 @@ >; }; + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x09 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5b@@ -638,22 +638,6 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x09 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5a MX7D_PAD_SD3_CLK__SD3_CLK 0x0a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a@@ -668,6 +652,22 @@ >; }; + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x09 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5b --2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 1/2 RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
In reply to Troy KiskyQuoted 3 lines · Troy Kisky
No i.mx6q board uses a 100k pull-down on clock, why should i.mx7d ?
Signed-off-by Troy Kisky <[email protected]>
Add Dong and Frank who may help to confirm.
Shawn
Quoted 79 lines
--- arch/arm/boot/dts/imx7d-sdb.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)arch/arm/boot/dts/imx7d-sdb.dts +7
-7@@ -591,7 +591,7 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_CLK__SD1_CLK 0x09 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59@@ -605,7 +605,7 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_CLK__SD2_CLK 0x09 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59@@ -616,7 +616,7 @@ pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_CLK__SD2_CLK 0x0a MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a@@ -627,7 +627,7 @@ pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_CLK__SD2_CLK 0x0b MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b@@ -639,7 +639,7 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_CLK__SD3_CLK 0x09 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59@@ -655,7 +655,7 @@ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_CLK__SD3_CLK 0x0a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a@@ -671,7 +671,7 @@ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_CLK__SD3_CLK 0x0b MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5bSignature · 7 lines
2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel at lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 1/2 RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
Hi Troy,
Quoted 9 lines
-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Thursday, June 15, 2017 11:39 AM
To: Troy Kisky; A.s. Dong; Frank Li
Cc: shawn.guo at linaro.org; Fabio Estevam; gary.bisson at boundarydevices.com; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 1/2] RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
Quoted 3 lines
Quoted 2 lines · Troy Kisky
No i.mx6q board uses a 100k pull-down on clock, why should i.mx7d ?
I saw the mx7d evk clk resistor pull-down is DNP,
then why we disable internal pad pull-down?
Regards
Dong Aisheng
Quoted 85 lines
Quoted 1 line
Signed-off-by Troy Kisky <[email protected]>Add Dong and Frank who may help to confirm.
Shawn
Quoted 79 lines
--- arch/arm/boot/dts/imx7d-sdb.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)(quoted diff) +0
-0
b/arch/arm/boot/dts/imx7d-sdb.dtsindex 54c4540..cab9208 100644arch/arm/boot/dts/imx7d-sdb.dts +7
-8@@ -591,7 +591,7 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_CLK__SD1_CLK 0x09 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59@@ -605,7 +605,7 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_CLK__SD2_CLK 0x09 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59@@ -616,7 +616,7 @@ pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_CLK__SD2_CLK 0x0a MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a@@ -627,7 +627,7 @@ pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_CLK__SD2_CLK 0x0b MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b@@ -639,7 +639,7 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_CLK__SD3_CLK 0x09 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59@@ -655,7 +655,7 @@ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_CLK__SD3_CLK 0x0a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a@@ -671,7 +671,7 @@ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_CLK__SD3_CLK 0x0b MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b --2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 1/2 RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
Quoted 11 lines · A.s. Dong
Hi Troy,
Quoted 9 lines
-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Thursday, June 15, 2017 11:39 AM
To: Troy Kisky; A.s. Dong; Frank Li
Cc: shawn.guo at linaro.org; Fabio Estevam; gary.bisson at boundarydevices.com; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 1/2] RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
Quoted 6 lines
Quoted 3 lines · Troy Kisky
Quoted 2 lines
No i.mx6q board uses a 100k pull-down on clock, why should i.mx7d ?
I saw the mx7d evk clk resistor pull-down is DNP,
then why we disable internal pad pull-down?
That sounds like a very good reason to disable to me. Why rely on a DNP? Also, consistency with imx6 is nice.
Quoted 90 lines
Regards
Dong AishengQuoted 85 lines
Quoted 1 line
Signed-off-by Troy Kisky <[email protected]>Add Dong and Frank who may help to confirm.
Shawn
Quoted 79 lines
--- arch/arm/boot/dts/imx7d-sdb.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)(quoted diff) +0
-0
b/arch/arm/boot/dts/imx7d-sdb.dtsindex 54c4540..cab9208 100644arch/arm/boot/dts/imx7d-sdb.dts +7
-8@@ -591,7 +591,7 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_CLK__SD1_CLK 0x09 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59@@ -605,7 +605,7 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_CLK__SD2_CLK 0x09 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59@@ -616,7 +616,7 @@ pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_CLK__SD2_CLK 0x0a MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a@@ -627,7 +627,7 @@ pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_CLK__SD2_CLK 0x0b MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b@@ -639,7 +639,7 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_CLK__SD3_CLK 0x09 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59@@ -655,7 +655,7 @@ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_CLK__SD3_CLK 0x0a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a@@ -671,7 +671,7 @@ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_CLK__SD3_CLK 0x0b MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b --2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 1/2 RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
Hi Troy,
Quoted 25 lines
-----Original Message-----
From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
Sent: Friday, June 16, 2017 1:46 AM
To: A.s. Dong; Shawn Guo; Frank Li
Cc: shawn.guo at linaro.org; Fabio Estevam; gary.bisson at boundarydevices.com; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 1/2] RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clockQuoted 15 lines · A.s. Dong
Hi Troy,
Quoted 12 lines
-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Thursday, June 15, 2017 11:39 AM
To: Troy Kisky; A.s. Dong; Frank Li
Cc: shawn.guo at linaro.org; Fabio Estevam;
gary.bisson at boundarydevices.com; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 1/2] RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clockQuoted 2 lines · Troy Kisky
No i.mx6q board uses a 100k pull-down on clock, why should i.mx7d ?
Quoted 7 lines
Quoted 2 lines
I saw the mx7d evk clk resistor pull-down is DNP, then why we disable internal pad pull-down?
That sounds like a very good reason to disable to me. Why rely on a DNP? Also, consistency with imx6 is nice.
Sorry missed your reply.
Not quite understand your point.
We would like to pull down the clk signal in default state, But due to the board pull-down resistor is DNP (not exist), That's why we use internal pull down function instead.
Regards
Dong Aisheng
Quoted 91 lines
Quoted 91 lines
Regards
Dong AishengQuoted 85 lines
Quoted 1 line
Signed-off-by Troy Kisky <[email protected]>Add Dong and Frank who may help to confirm.
Shawn
Quoted 79 lines
--- arch/arm/boot/dts/imx7d-sdb.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)(quoted diff) +0
-0
b/arch/arm/boot/dts/imx7d-sdb.dtsindex 54c4540..cab9208 100644arch/arm/boot/dts/imx7d-sdb.dts +7
-8@@ -591,7 +591,7 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_CLK__SD1_CLK 0x09 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59@@ -605,7 +605,7 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_CLK__SD2_CLK 0x09 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59@@ -616,7 +616,7 @@ pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_CLK__SD2_CLK 0x0a MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a@@ -627,7 +627,7 @@ pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_CLK__SD2_CLK 0x0b MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b@@ -639,7 +639,7 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_CLK__SD3_CLK 0x09 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59@@ -655,7 +655,7 @@ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_CLK__SD3_CLK 0x0a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a@@ -671,7 +671,7 @@ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_CLK__SD3_CLK 0x0b MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b --2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 1/2 RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
Quoted 37 lines · A.s. Dong
Hi Troy,
Quoted 25 lines
-----Original Message-----
From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
Sent: Friday, June 16, 2017 1:46 AM
To: A.s. Dong; Shawn Guo; Frank Li
Cc: shawn.guo at linaro.org; Fabio Estevam; gary.bisson at boundarydevices.com; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 1/2] RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clockQuoted 15 lines · A.s. Dong
Hi Troy,
Quoted 12 lines
-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Thursday, June 15, 2017 11:39 AM
To: Troy Kisky; A.s. Dong; Frank Li
Cc: shawn.guo at linaro.org; Fabio Estevam;
gary.bisson at boundarydevices.com; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 1/2] RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clockQuoted 2 lines · Troy Kisky
No i.mx6q board uses a 100k pull-down on clock, why should i.mx7d ?
Quoted 7 lines
Quoted 2 lines
I saw the mx7d evk clk resistor pull-down is DNP, then why we disable internal pad pull-down?
That sounds like a very good reason to disable to me. Why rely on a DNP? Also, consistency with imx6 is nice.
Sorry missed your reply.
Quoted 8 lines
Not quite understand your point.
We would like to pull down the clk signal in default state, But due to the board pull-down resistor is DNP (not exist), That's why we use internal pull down function instead.Regards
Dong Aisheng
I totally misinterpreted what you said about the DNP. Sorry. I understand you now, thanks.
But can you say why you want to pull down the clk signal in default state ? And why mx6q does not want to do the same ?
Thanks
Troy
Fabio Estevam
reviewerPATCH 1/2 RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
Hi Troy,
Quoted 1 line · Troy Kisky
And why mx6q does not want to do the same ?
On imx6qdl-sabresd.dtsi we have:
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
PUS field is at 00, which means 100k pull down.
PATCH 1/2 RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
Quoted 5 lines · Fabio Estevam
Hi Troy,
On Tue, Jun 27, 2017 at 5:22 PM, Troy Kisky
<[email protected]> wrote:
Quoted 8 lines
Quoted 1 line
And why mx6q does not want to do the same ?
On
imx6qdl-sabresd.dtsiwe have:
MX6QDL_PAD_SD2_CLK__SD2_CLK0x10059PUS field is at 00, which means 100k pull down.
Hi Fabio !
Yes, but the enable bits(12,13) are clear.MX6QDL_PAD_SD2_CLK__SD2_CLK 0x13059
Would turn on 100K pull down.
Troy
Fabio Estevam
reviewerPATCH 1/2 RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
Quoted 6 lines · Troy Kisky
Hi Fabio !
Yes, but the enable
bits(12,13)are clear.MX6QDL_PAD_SD2_CLK__SD2_CLK0x13059Would turn on 100K pull down.
Yes, you are right. That's the value that some boards use for pulling down the DATA3 line.
So your patch makes sense in my opinion.
Fabio Estevam
reviewerPATCH 1/2 RFC: ARM: dts: imx7d-sdb: remove 100k pull-down on USDHCx clock
In reply to A.s. DongHi Dong,
Quoted 4 lines · A.s. Dong
Not quite understand your point.
We would like to pull down the clk signal in default state, But due to the board pull-down resistor is DNP (not exist), That's why we use internal pull down function instead.
Looking at the SD1_CLK line in the mx7d-sdb schematics rev d there is no pull-down DNP resistor.
The DNP element in this line is capacitor C197.