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reset: add DT bindings header for Gemini reset controller

PATCH New Linus Walleij 3 participants 7 messages Jun 18, 2017 – Jun 20, 2017

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Device tree bindings Common clk Reset controller framework
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Linus Walleij

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#0 lore raw

PATCH v6 1/3 reset: add DT bindings header for Gemini reset controller

This adds the DT binding macros used by the reset controller.

Acked-by Rob Herring <[email protected]>
Signed-off-by Linus Walleij <[email protected]>

---
Please merge this into the clk tree with the rest of the patches when ready. The same patch might come in from the reset tree but that is harmless and a necessary evil in this case.

ChangeLog v4->v6:
- No changes just including with the clock driver series. ChangeLog v1->v4:
- New file to merge the macros in isolation from the DT bindings and implementation.

The bindings themselves will be merged as part of the DTS updates through the ARM SoC tree.

---
 include/dt-bindings/reset/cortina,gemini-reset.h | 36 ++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 include/dt-bindings/reset/cortina,gemini-reset.h
include/dt-bindings/reset/cortina,gemini-reset.h new file +36 -0
new file mode 100644
index 000000000000..0b886aee65e3
@@ -0,0 +1,36 @@
+#ifndef _DT_BINDINGS_RESET_CORTINA_GEMINI_H
+#define _DT_BINDINGS_RESET_CORTINA_GEMINI_H
+
+#define GEMINI_RESET_DRAM	0
+#define GEMINI_RESET_FLASH	1
+#define GEMINI_RESET_IDE	2
+#define GEMINI_RESET_RAID	3
+#define GEMINI_RESET_SECURITY	4
+#define GEMINI_RESET_GMAC0	5
+#define GEMINI_RESET_GMAC1	6
+#define GEMINI_RESET_PCI	7
+#define GEMINI_RESET_USB0	8
+#define GEMINI_RESET_USB1	9
+#define GEMINI_RESET_DMAC	10
+#define GEMINI_RESET_APB	11
+#define GEMINI_RESET_LPC	12
+#define GEMINI_RESET_LCD	13
+#define GEMINI_RESET_INTCON0	14
+#define GEMINI_RESET_INTCON1	15
+#define GEMINI_RESET_RTC	16
+#define GEMINI_RESET_TIMER	17
+#define GEMINI_RESET_UART	18
+#define GEMINI_RESET_SSP	19
+#define GEMINI_RESET_GPIO0	20
+#define GEMINI_RESET_GPIO1	21
+#define GEMINI_RESET_GPIO2	22
+#define GEMINI_RESET_WDOG	23
+#define GEMINI_RESET_EXTERN	24
+#define GEMINI_RESET_CIR	25
+#define GEMINI_RESET_SATA0	26
+#define GEMINI_RESET_SATA1	27
+#define GEMINI_RESET_TVC	28
+#define GEMINI_RESET_CPU1	30
+#define GEMINI_RESET_GLOBAL	31
+
+#endif
Signature · 1 line
2.9.4
author
#1 lore raw

PATCH v6 2/3 clk: add DT bindings header for Gemini clock controller

This adds the DT binding macros used by the clock controller.

Acked-by Rob Herring <[email protected]>
Signed-off-by Linus Walleij <[email protected]>

---
Mike/Stephen: please merge this into the clock subsystem once you're happy with it.

ChangeLog v5->v6:
- No changes, resending to keep the series together. ChangeLog v4->v5:
- No changes, resending to keep the series together. ChangeLog v1->v4:
- New file to merge the macros in isolation from the DT bindings and implementation.

The bindings themselves are merged through the ARM SoC tree.

---
 include/dt-bindings/clock/cortina,gemini-clock.h | 29 ++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 include/dt-bindings/clock/cortina,gemini-clock.h
include/dt-bindings/clock/cortina,gemini-clock.h new file +29 -0
new file mode 100644
index 000000000000..acf5cd550b0c
@@ -0,0 +1,29 @@
+#ifndef DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
+#define DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
+
+/* RTC, AHB, APB, CPU, PCI, TVC, UART clocks and 13 gates */
+#define GEMINI_NUM_CLKS 20
+
+#define GEMINI_CLK_RTC 0
+#define GEMINI_CLK_AHB 1
+#define GEMINI_CLK_APB 2
+#define GEMINI_CLK_CPU 3
+#define GEMINI_CLK_PCI 4
+#define GEMINI_CLK_TVC 5
+#define GEMINI_CLK_UART 6
+#define GEMINI_CLK_GATES 7
+#define GEMINI_CLK_GATE_SECURITY 7
+#define GEMINI_CLK_GATE_GMAC0 8
+#define GEMINI_CLK_GATE_GMAC1 9
+#define GEMINI_CLK_GATE_SATA0 10
+#define GEMINI_CLK_GATE_SATA1 11
+#define GEMINI_CLK_GATE_USB0 12
+#define GEMINI_CLK_GATE_USB1 13
+#define GEMINI_CLK_GATE_IDE 14
+#define GEMINI_CLK_GATE_PCI 15
+#define GEMINI_CLK_GATE_DDR 16
+#define GEMINI_CLK_GATE_FLASH 17
+#define GEMINI_CLK_GATE_TVC 18
+#define GEMINI_CLK_GATE_BOOT 19
+
+#endif /* DT_BINDINGS_CORTINA_GEMINI_CLOCK_H */
Signature · 1 line
2.9.4
Applied
#2 lore raw

PATCH v6 2/3 clk: add DT bindings header for Gemini clock controller

Quoted 5 lines · Linus Walleij

This adds the DT binding macros used by the clock controller.

Acked-by Rob Herring <[email protected]>
Signed-off-by Linus Walleij <[email protected]>

---

Applied to clk-next

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#3 lore raw

PATCH v6 3/3 clk: Add Gemini SoC clock controller

In reply to Linus Walleij

The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock.

Signed-off-by Linus Walleij <[email protected]>

---
Mike/Stephen: please merge this into the clk subsystem along with the <dt-bindings> patch once you're happy with it.

ChangeLog v5->v6:
- Merge the Gemini reset controller code into the clock driver so as to resolve the conflict about what device should be probing from the system controller. The reset portions are copy/pasted from the driver previously merged by Philipp Zabel.
- Split the driver in two init paths: one that executes at CLK_OF_DECLARE_DRIVER() level to provide the basic cxo, AHB and APB clocks, so that the system timer can start, and another path executed for the platform device as it comes up. The clock table is filled with -EPROBE_DEFER pointers until the platform device probes.
ChangeLog v4->v5:
- Add a dependency on ARCH_GEMINI || COMPILE_TEST to Kconfig
- Fix the includes, remove <linux/clkdev.h>, add <linux/spinlock.h>
- Indent all defines properly.
- Remove the global clock arrays and use the pattern to allocate a struct clk_hw_onecell_data * and fill that with the hw clocks.
- Switch everything to use struct clk_hw * everywhere.
- Look up clocks using of_clk_hw_onecell_get, add the lookup using of_clk_add_hw_provider().
- Cut unnecessary status checks from regmap_* accessors, skip to just checking the return value of the first access and then assume the MMIO regmap is working fine.
- Reduce the CPU-to-AHB calculation switch() statement to a table lookup.
ChangeLog v3->v4:
- No changes, just resending with separate DT header file. ChangeLog v2->v3:
- Augment driver to probe directly from the system controller.
- Mike/Stephen: when you're happy with this please ACK it so I can merge it through ARM SoC. This is needed because of the mess of #include <dt-bindings/*> from the DT bindings that is then used all over the DTS files.
ChangeLog v1->v2:
- Move the clock controller to be part of the syscon node. No need for a separate child node for this.

---
 drivers/clk/Kconfig      |   9 +
 drivers/clk/Makefile     |   1 +
 drivers/clk/clk-gemini.c | 455 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 465 insertions(+)
 create mode 100644 drivers/clk/clk-gemini.c
drivers/clk/Kconfig +9 -0
index 36cfea38135f..8611b0de01a0 100644
@@ -126,6 +126,15 @@ config COMMON_CLK_CS2000_CP
 	help
 	  If you say yes here you get support for the CS2000 clock multiplier.
 
+config COMMON_CLK_GEMINI
+	bool "Clock driver for Cortina Systems Gemini SoC"
+	depends on ARCH_GEMINI || COMPILE_TEST
+	select MFD_SYSCON
+	select RESET_CONTROLLER
+	---help---
+	  This driver supports the SoC clocks on the Cortina Systems Gemini
+	  platform, also known as SL3516 or CS3516.
+
 config COMMON_CLK_S2MPS11
 	tristate "Clock driver for S2MPS1X/S5M8767 MFD"
 	depends on MFD_SEC_CORE || COMPILE_TEST
drivers/clk/Makefile +1 -0
index c19983afcb81..a625c002a810 100644
@@ -25,6 +25,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925)	+= clk-cdce925.o
 obj-$(CONFIG_ARCH_CLPS711X)		+= clk-clps711x.o
 obj-$(CONFIG_COMMON_CLK_CS2000_CP)	+= clk-cs2000-cp.o
 obj-$(CONFIG_ARCH_EFM32)		+= clk-efm32gg.o
+obj-$(CONFIG_COMMON_CLK_GEMINI)		+= clk-gemini.o
 obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o
 obj-$(CONFIG_COMMON_CLK_MAX77686)	+= clk-max77686.o
 obj-$(CONFIG_ARCH_MB86S7X)		+= clk-mb86s7x.o
drivers/clk/clk-gemini.c new file +455 -0

455 lines not on this page · raw message

Signature · 1 line
2.9.4
#4 lore raw

PATCH v6 3/3 clk: Add Gemini SoC clock controller

Quoted 11 lines · Linus Walleij

The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock.

Signed-off-by Linus Walleij <[email protected]>

---
Mike/Stephen: please merge this into the clk subsystem along with the <dt-bindings> patch once you're happy with it.

Looking good overall. Just the small things now.

Quoted 23 lines
drivers/clk/clk-gemini.c new file +17 -0
new file mode 100644
index 000000000000..810c35008d6a
@@ -0,0 +1,455 @@
+
+static int gemini_clk_probe(struct platform_device *pdev)
+{
+	/* Gives the fracions 1x, 1.5x, 1.85x and 2x */
+	unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 };
+	unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 };
+	void __iomem *base;
+	struct gemini_reset *gr;
+	struct regmap *map;
+	struct clk_hw *hw;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	unsigned int mult, div;
+	u32 val;
+	int ret;
+	int i;
+

drivers/clk/clk-gemini.c line 27

Quoted 10 lines
drivers/clk/clk-gemini.c new file +10 -0
+	gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL);
+	if (!gr)
+		return -ENOMEM;
+
+	/* Remap the system controller for the exclusive register */
+	base = of_iomap(np, 0);
+	if (!base) {
+		dev_err(dev, "no memory base\n");
+		return -ENODEV;
+	}

We can use normal platform device driver APIs now instead of of_iomap()?

Quoted 9 lines
drivers/clk/clk-gemini.c new file +9 -0
+
+	map = syscon_node_to_regmap(np);
+	if (IS_ERR(map)) {
+		dev_err(dev, "no syscon regmap\n");
+		return PTR_ERR(map);
+	}
+
+	gr->map = map;
+	gr->rcdev.owner = THIS_MODULE;

[..]

Quoted 6 lines
drivers/clk/clk-gemini.c new file +6 -0
+
+static void __init gemini_cc_init(struct device_node *np)
+{
+	struct regmap *map;
+	struct clk_hw *hw;
+	unsigned long freq;

drivers/clk/clk-gemini.c line 397

Quoted 10 lines
drivers/clk/clk-gemini.c new file +10 -0
+	unsigned int mult, div;
+	u32 val;
+	int ret;
+	int i;
+
+	gemini_clk_data = kzalloc(sizeof(*gemini_clk_data) +
+			sizeof(*gemini_clk_data->hws) * GEMINI_NUM_CLKS,
+			GFP_KERNEL);
+	if (!gemini_clk_data) {
+		pr_err("out of memory for clocks\n");

We don't need out of memory error messages.

Quoted 26 lines
drivers/clk/clk-gemini.c new file +26 -0
+		return;
+	}
+	/*
+	 * This way all clock fetched before the platform device probes,
+	 * except those we assign here for early use, will be deferred.
+	 */
+	for (i = 0; i < GEMINI_NUM_CLKS; i++)
+		gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+	map = syscon_node_to_regmap(np);
+	if (IS_ERR(map)) {
+		pr_err("no syscon regmap\n");
+		return;
+	}
+	/*
+	 * We check that the regmap works on this very first access,
+	 * but as this is an MMIO-backed regmap, subsequent regmap
+	 * access is not going to fail and we skip error checks from
+	 * this point.
+	 */
+	ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
+	if (ret) {
+		pr_err("failed to read global status register\n");
+		return;
+	}
+

drivers/clk/clk-gemini.c line 433

Quoted 10 lines
drivers/clk/clk-gemini.c new file +10 -0
+	/*
+	 * XTAL is the crystal oscillator, 60 or 30 MHz selected from
+	 * strap pin E6
+	 */
+	if (val & PLL_OSC_SEL)
+		freq = 30000000;
+	else
+		freq = 60000000;
+	hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq);
+	pr_info("main crystal @%lu MHz\n", (freq / 1000000));

Debug printk? Also drop the parenthesis around that division please.

Quoted 22 lines
drivers/clk/clk-gemini.c new file +22 -0
+
+	/* VCO clock derived from the crystal */
+	mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);
+	div = 2;
+	/* If we run on 30 MHz crystal we have to multiply with two */
+	if (val & PLL_OSC_SEL)
+		mult *= 2;
+	hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div);
+
+	/* The AHB clock is always 1/3 of the VCO */
+	hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3);
+	gemini_clk_data->hws[GEMINI_CLK_AHB] = hw;
+
+	/* The APB clock is always 1/6 of the AHB */
+	hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6);
+	gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
+
+	/* Register the clocks to be accessed by the device tree */
+	gemini_clk_data->num = GEMINI_NUM_CLKS;
+	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
+}
+CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
maintainer
#5 lore raw

PATCH v6 3/3 clk: Add Gemini SoC clock controller

In reply to Linus Walleij
Quoted 12 lines · Linus Walleij

The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock.

Signed-off-by Linus Walleij <[email protected]>

---
Mike/Stephen: please merge this into the clk subsystem along with the <dt-bindings> patch once you're happy with it.

Quoted 6 lines

ChangeLog v5->v6:
- Merge the Gemini reset controller code into the clock driver so as to resolve the conflict about what device should be probing from the system controller. The reset portions are copy/pasted from the driver previously merged by Philipp Zabel.

For the reset controller part,

Acked-by Philipp Zabel <[email protected]>

regards
Philipp