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clk: hi6220: add acpu clock

PATCH RESEND New Zhangfei Gao 2 participants 4 messages May 31, 2017 – Jun 20, 2017

Subsystems (3)
Device tree bindings Common clk Arm/HiSilicon SoC support
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Zhangfei Gao

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#0 lore raw

PATCH RESEND 1/2 clk: hi6220: add acpu clock

Add acpu clock, including sft clock controlling hi6220 coresight module

Signed-off-by Zhangfei Gao <[email protected]>
Signed-off-by Li Pengcheng <[email protected]>
Acked-by Rob Herring <[email protected]>

---
Verified on clk-next, v.12-rc1

.../devicetree/bindings/clock/hi6220-clock.txt | 1 +

 drivers/clk/hisilicon/clk-hi6220.c                 | 23 ++++++++++++++++++++++
 include/dt-bindings/clock/hi6220-clock.h           |  4 ++++
 3 files changed, 28 insertions(+)
Documentation/devicetree/bindings/clock/hi6220-clock.txt +1 -0
index e4d5fea..ef3deb7 100644
@@ -11,6 +11,7 @@ Required Properties:
 - compatible: the compatible should be one of the following strings to
 	indicate the clock controller functionality.
 
+	- "hisilicon,hi6220-acpu-sctrl"
 	- "hisilicon,hi6220-aoctrl"
 	- "hisilicon,hi6220-sysctrl"
 	- "hisilicon,hi6220-mediactrl"
drivers/clk/hisilicon/clk-hi6220.c +23 -0
index 2ae151c..fc8813f 100644
@@ -285,3 +285,26 @@ static void __init hi6220_clk_power_init(struct device_node *np)
 				ARRAY_SIZE(hi6220_div_clks_power), clk_data);
 }
 CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init);
+
+
+/* clocks in acpu */
+static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = {
+	{ HI6220_ACPU_SFT_AT_S, "sft_at_s", "cs_atb",
+	  CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, },
+};
+
+static void __init hi6220_clk_acpu_init(struct device_node *np)
+{
+	struct hisi_clock_data *clk_data;
+	int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks);
+
+	clk_data = hisi_clk_init(np, nr);
+	if (!clk_data)
+		return;
+
+	hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks,
+				   ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks),
+				   clk_data);
+}
+
+CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init);
include/dt-bindings/clock/hi6220-clock.h +4 -0
index b8ba665..409cc02 100644
@@ -174,4 +174,8 @@
 #define HI6220_DDRC_AXI1	7
 
 #define HI6220_POWER_NR_CLKS	8
+
+/* clk in Hi6220 acpu sctrl */
+#define HI6220_ACPU_SFT_AT_S		0
+
 #endif
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH RESEND 2/2 arm64: dts: hi6220: add acpu_sctrl

Add acpu_sctrl clock node

Signed-off-by Zhangfei Gao <[email protected]>
Signed-off-by Li Pengcheng <[email protected]>

---
Verified on clk-next, v.12-rc1

 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm64/boot/dts/hisilicon/hi6220.dtsi +6 -0
index 1e5129b..b3ecbcf 100644
@@ -262,6 +262,12 @@
 			#clock-cells = <1>;
 		};
 
+		acpu_sctrl: acpu_sctrl at f7032000 {
+			compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
+			reg = <0x0 0xf6504000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		medianoc_ade: medianoc_ade at f4520000 {
 			compatible = "syscon";
 			reg = <0x0 0xf4520000 0x0 0x4000>;
Signature · 1 line
2.7.4
Applied
#2 lore raw

PATCH RESEND 1/2 clk: hi6220: add acpu clock

In reply to Zhangfei Gao
Quoted 6 lines · Zhangfei Gao

Add acpu clock, including sft clock controlling hi6220 coresight module

Signed-off-by Zhangfei Gao <[email protected]>
Signed-off-by Li Pengcheng <[email protected]>
Acked-by Rob Herring <[email protected]>

---

Applied to clk-next

Signature · 2 lines
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