clk: Add Gemini SoC clock controller
PATCH v8 1/1 clk: Add Gemini SoC clock controller
The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock.
---
ChangeLog v7->v8:
- Add Philipp's Acked-by that I managed to forget. ChangeLog v6->v7:
- Use platform device oriented memory remapping with devm_ioremap_resource().
- Convert shouty boot message about clock frequency to a pr_debug().
- Drop patches 1, 2 from the series as they got merged. ChangeLog v5->v6:
- Merge the Gemini reset controller code into the clock driver so as to resolve the conflict about what device should be probing from the system controller. The reset portions are copy/pasted from the driver previously merged by Philipp Zabel.
- Split the driver in two init paths: one that executes at CLK_OF_DECLARE_DRIVER() level to provide the basic cxo, AHB and APB clocks, so that the system timer can start, and another path executed for the platform device as it comes up. The clock table is filled with -EPROBE_DEFER pointers until the platform device probes.
ChangeLog v4->v5:
- Add a dependency on ARCH_GEMINI || COMPILE_TEST to Kconfig
- Fix the includes, remove <linux/clkdev.h>, add <linux/spinlock.h>
- Indent all defines properly.
- Remove the global clock arrays and use the pattern to allocate a struct clk_hw_onecell_data * and fill that with the hw clocks.
- Switch everything to use struct clk_hw * everywhere.
- Look up clocks using of_clk_hw_onecell_get, add the lookup using of_clk_add_hw_provider().
- Cut unnecessary status checks from regmap_* accessors, skip to just checking the return value of the first access and then assume the MMIO regmap is working fine.
- Reduce the CPU-to-AHB calculation switch() statement to a table lookup.
ChangeLog v3->v4:
- No changes, just resending with separate DT header file. ChangeLog v2->v3:
- Augment driver to probe directly from the system controller.
- Mike/Stephen: when you're happy with this please ACK it so I can merge it through ARM SoC. This is needed because of the mess of #include <dt-bindings/*> from the DT bindings that is then used all over the DTS files.
ChangeLog v1->v2:
- Move the clock controller to be part of the syscon node. No need for a separate child node for this.
--- drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-gemini.c | 458 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 468 insertions(+) create mode 100644 drivers/clk/clk-gemini.c
drivers/clk/Kconfig +9 -0
@@ -126,6 +126,15 @@ config COMMON_CLK_CS2000_CP help If you say yes here you get support for the CS2000 clock multiplier. +config COMMON_CLK_GEMINI + bool "Clock driver for Cortina Systems Gemini SoC" + depends on ARCH_GEMINI || COMPILE_TEST + select MFD_SYSCON + select RESET_CONTROLLER + ---help--- + This driver supports the SoC clocks on the Cortina Systems Gemini + platform, also known as SL3516 or CS3516. + config COMMON_CLK_S2MPS11 tristate "Clock driver for S2MPS1X/S5M8767 MFD" depends on MFD_SEC_CORE || COMPILE_TEST
drivers/clk/Makefile +1 -0
@@ -25,6 +25,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o +obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o
drivers/clk/clk-gemini.c new file +458 -0
458 lines not on this page · raw message
Signature · 1 line
2.9.4
Stephen Boyd
AppliedPATCH v8 1/1 clk: Add Gemini SoC clock controller
Quoted 10 lines · Linus Walleij
The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock.
Acked-by Philipp Zabel <[email protected]>Signed-off-by Linus Walleij <[email protected]>---
Applied to clk-next + this fixup
---8<---
drivers/clk/clk-gemini.c +2 -6
@@ -279,13 +279,9 @@ static int gemini_clk_probe(struct platform_device *pdev)/* Remap the system controller for the exclusive register */ res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); -if (!res) -return -ENODEV ; base =devm_ioremap_resource (dev, res); -if (!base) { -dev_err (dev,"no memory base\n" ); -return -ENODEV ; - } +if (IS_ERR (base)) +return PTR_ERR (base); map =syscon_node_to_regmap (np);if (IS_ERR (map)) {
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v8 1/1 clk: Add Gemini SoC clock controller
Quoted 8 lines · Stephen Boyd
Quoted 7 lines · Linus Walleij
The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock.
Quoted 5 lines
Quoted 3 lines
Acked-by Philipp Zabel <[email protected]>Signed-off-by Linus Walleij <[email protected]>---
Applied to clk-next + this fixup
Thanks, and thanks a lot for fixing.
Hm, I copied that code from somewhere.
Now I need to try to remember where so I can go and fix the bad example.
Yours,
Linus Walleij