pinctrl: imx: add imx7ulp pinctrl support

---
ChangeLog:
* new patch

---
 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +5 -4

index f01d154..1b954b5 100644
@@ -205,10 +205,11 @@ maintain.
 
 For cases like this, the pin controller driver may use the pinmux helper
 property, where the pin identifier is packed with mux configuration settings
-in a single integer.
+in a single integer or integers array which depends on platform binding
+specific.
 
-The pinmux property accepts an array of integers, each of them describing
-a single pin multiplexing configuration.
+The pinmux property accepts an array of group of integers, each group
+describing a single pin multiplexing configuration.
 
 pincontroller {
 	state_0_node_a {

@@ -300,7 +301,7 @@ arguments are described below.
 - pinmux takes a list of pin IDs and mux settings as required argument. The
   specific bindings for the hardware defines:
   - How pin IDs and mux settings are defined and assembled together in a single
-    integer.
+    integer or integers array.
 
 - bias-pull-up, -down and -pin-default take as optional argument on hardware
   supporting it the pull strength in Ohm. bias-disable will disable the pull.

Signature · 1 line

2.7.4

jmondi

2017-06-21 21:50 UTC #2 lore raw

PATCH v4 1/7 dt-bindings: pinctrl: extend the pinmux property to support integers array

Hi Dong,
thanks for this

Quoted 24 lines · Dong Aisheng

Some platforms may need more than one integer to represent a complete pinmux binding, so let's extend the pinmux property to allow to accept integer array instead of only a single integer.
Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Jacopo Mondi <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
ChangeLog:
* new patch
---
 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +0 -0
index f01d154..1b954b5 100644

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt maintain. · line 210

Quoted 7 lines

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +2 -1

@@ -205,10 +205,11 @@ maintain.
 
 For cases like this, the pin controller driver may use the pinmux helper
 property, where the pin identifier is packed with mux configuration settings
-in a single integer.
+in a single integer or integers array which depends on platform binding
+specific.

s/or integers array/or a group of integers/
since you're using "group" below

s/ which depends on platform binding specific//

I'm not a native speaker, but this sounds weird to me. If I'm the only one, please ignore my comment otherwise please drop this

Actually, to avoid confusion between "array of integers" and "group of integers" I would provide a definition of what a "pinmux group" is before everything else.
This is how the paragraph would look like:

-----------------------------------------------------------------------------
For cases like this, the pin controller driver may use the pinmux helper property, where the pin identifier is provided with mux configuration settings in a pinmux group.

A pinumux group consists of the pin identifier and mux settings represented as a single integer or an array of integers.

The pinmux property accepts an array of pinmux groups, each of them describing a single pin multiplexing configuration.

 pincontroller {
	state_0_node_a {
		pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
	};

};

Each individual pin controller driver bindings documentation shall specify how pin IDs and pin multiplexing configuration are defined and assembled together in a pinmux group.
-----------------------------------------------------------------------------

Thanks
j

Quoted 19 lines

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +3 -4

-The pinmux property accepts an array of integers, each of them describing
-a single pin multiplexing configuration.
+The pinmux property accepts an array of group of integers, each group
+describing a single pin multiplexing configuration.
 
 pincontroller {
 	state_0_node_a {

@@ -300,7 +301,7 @@ arguments are described below.
 - pinmux takes a list of pin IDs and mux settings as required argument. The
   specific bindings for the hardware defines:
   - How pin IDs and mux settings are defined and assembled together in a single
-    integer.
+    integer or integers array.
 
 - bias-pull-up, -down and -pin-default take as optional argument on hardware
   supporting it the pull strength in Ohm. bias-disable will disable the pull.
--

2.7.4

A.s. Dong

author maintainer

2017-06-22 14:35 UTC #3 lore raw

PATCH v4 1/7 dt-bindings: pinctrl: extend the pinmux property to support integers array

Hi Jacopo,

Quoted 79 lines

-----Original Message-----
From: jmondi [mailto:jacopo at jmondi.org]
Sent: Thursday, June 22, 2017 5:51 AM
To: A.s. Dong
Cc: linux-gpio at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linus.walleij at linaro.org; shawnguo at kernel.org; stefan at agner.ch; Jacky Bai; Andy Duan; kernel at pengutronix.de; Rob Herring; Mark Rutland; devicetree at vger.kernel.org; Jacopo Mondi
Subject: Re: [PATCH V4 1/7] dt-bindings: pinctrl: extend the pinmux property to support integers array
Hi Dong,
thanks for this
Quoted 32 lines · Dong Aisheng
Some platforms may need more than one integer to represent a complete pinmux binding, so let's extend the pinmux property to allow to accept integer array instead of only a single integer.
Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Jacopo Mondi <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
ChangeLog:
* new patch
---
 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | 9
+++++----
 1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index f01d154..1b954b5 100644
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +0 -0
@@ -205,10 +205,11 @@ maintain.
 
 For cases like this, the pin controller driver may use the pinmux
helper property, where the pin identifier is packed with mux configuration settings -in a single integer.
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Quoted 2 lines
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +2 -0
+in a single integer or integers array which depends on platform
+binding specific.
s/or integers array/or a group of integers/ since you're using "group" below
s/ which depends on platform binding specific//
I'm not a native speaker, but this sounds weird to me. If I'm the only one, please ignore my comment otherwise please drop this
Actually, to avoid confusion between "array of integers" and "group of integers" I would provide a definition of what a "pinmux group" is before everything else.
This is how the paragraph would look like:
--------------------------------------------------------------------------
---
For cases like this, the pin controller driver may use the pinmux helper
property, where the pin identifier is provided with mux configuration settings in a pinmux group.
A pinumux group consists of the pin identifier and mux settings
represented as a single integer or an array of integers.
The pinmux property accepts an array of pinmux groups, each of them
describing a single pin multiplexing configuration.
 pincontroller {
	state_0_node_a {
		pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
	};

Quoted 7 lines

};
Each individual pin controller driver bindings documentation shall
specify how pin IDs and pin multiplexing configuration are defined and assembled together in a pinmux group.
--------------------------------------------------------------------------
---

This does look much better.
I will renew the patch with your sign-off as well since it mostly from you. Thanks for the great suggestion.

Regards
Dong Aisheng

Quoted 27 lines

Thanks
j
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt arguments are described below. · line 301
Quoted 9 lines
-The pinmux property accepts an array of integers, each of them describing -a single pin multiplexing configuration.
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +2 -0
+The pinmux property accepts an array of group of integers, each group
+describing a single pin multiplexing configuration.
 
 pincontroller {
 	state_0_node_a {
@@ -300,7 +301,7 @@ arguments are described below.
 - pinmux takes a list of pin IDs and mux settings as required argument.
The
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt arguments are described below. · line 303
Quoted 2 lines
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +0 -0
   specific bindings for the hardware defines:
   - How pin IDs and mux settings are defined and assembled together in
a single
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt arguments are described below.
Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +1 -1
-    integer.
+    integer or integers array.
 
 - bias-pull-up, -down and -pin-default take as optional argument on
hardware
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt arguments are described below. · line 307
Quoted 1 line
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +0 -0
   supporting it the pull strength in Ohm. bias-disable will disable the
pull.
Quoted 3 lines
--
2.7.4

Dong Aisheng

author maintainer

2017-06-22 14:49 UTC #4 lore raw

PATCH v5 1/1 dt-bindings: pinctrl: extend the pinmux property to support integers array

Some platforms may need more than one integer to represent a complete pinmux binding, so let's extend the pinmux property to allow to accept integer array instead of only a single integer.

Cc Rob Herring <[email protected]>

Cc Mark Rutland <[email protected]>

Cc devicetree at vger.kernel.org

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Signed-off-by Jacopo Mondi <[email protected]>

---
ChangeLog:
v4->v5:
* doc improvement
v4:
* new patch

---
 .../devicetree/bindings/pinctrl/pinctrl-bindings.txt      | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +8 -7

index f01d154..30f1d9e 100644
@@ -204,21 +204,22 @@ each single pin the number of required sub-nodes containing "pin" and
 maintain.
 
 For cases like this, the pin controller driver may use the pinmux helper
-property, where the pin identifier is packed with mux configuration settings
-in a single integer.
+property, where the pin identifier is provided with mux configuration settings
+in a pinmux group. A pinmux group consists of the pin identifier and mux
+settings represented as a single integer or an array of integers.
 
-The pinmux property accepts an array of integers, each of them describing
+The pinmux property accepts an array of pinmux groups, each of them describing
 a single pin multiplexing configuration.
 
 pincontroller {
 	state_0_node_a {
-		pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ...;
+		pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
 	};
 };
 
 Each individual pin controller driver bindings documentation shall specify
-how those values (pin IDs and pin multiplexing configuration) are defined and
-assembled together.
+how pin IDs and pin multiplexing configuration are defined and assembled
+together in a pinmux group.
 
 == Generic pin configuration node content ==

@@ -300,7 +301,7 @@ arguments are described below.
 - pinmux takes a list of pin IDs and mux settings as required argument. The
   specific bindings for the hardware defines:
   - How pin IDs and mux settings are defined and assembled together in a single
-    integer.
+    integer or an array of integers.
 
 - bias-pull-up, -down and -pin-default take as optional argument on hardware
   supporting it the pull strength in Ohm. bias-disable will disable the pull.

Signature · 1 line

2.7.4

Rob Herring

maintainer

2017-06-26 18:49 UTC #5 lore raw

PATCH v5 1/1 dt-bindings: pinctrl: extend the pinmux property to support integers array

Quoted 18 lines · Dong Aisheng

Some platforms may need more than one integer to represent a complete pinmux binding, so let's extend the pinmux property to allow to accept integer array instead of only a single integer.
Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Jacopo Mondi <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
ChangeLog:
v4->v5:
* doc improvement
v4:
* new patch

Quoted 3 lines

---
 .../devicetree/bindings/pinctrl/pinctrl-bindings.txt      | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

Acked-by Rob Herring <[email protected]>

Linus Walleij

2017-06-29 12:35 UTC #6 lore raw

PATCH v5 1/1 dt-bindings: pinctrl: extend the pinmux property to support integers array

Quoted 12 lines · Dong Aisheng

Some platforms may need more than one integer to represent a complete pinmux binding, so let's extend the pinmux property to allow to accept integer array instead of only a single integer.
Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Signed-off-by Jacopo Mondi <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

Quoted 4 lines

---
ChangeLog:
v4->v5:
* doc improvement

Patch applied with Rob's ACK.

Yours,
Linus Walleij

Dong Aisheng

author maintainer

2017-06-21 11:59 UTC #7 lore raw

PATCH v4 2/7 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.

Cc Rob Herring <[email protected]>

Cc Mark Rutland <[email protected]>

Cc devicetree at vger.kernel.org

Cc Linus Walleij <[email protected]>

---
ChangeLog:
v3->v4:
* change pad name to IMX7ULP_PAD_X style
* switch to generic pinmux property
* input/output property are removed.
v2->v3:
* switch to generic input/output-enable property
v1->v2:
* add more descriptions in binding doc
* add missed prefix for private properties.
* move dt-bindings/pinctrl/imx7ulp-pinfunc.h to arch/arm/boot/dts

---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  61 +++
 arch/arm/boot/dts/imx7ulp-pinfunc.h                | 468 +++++++++++++++++++++
 2 files changed, 529 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/imx7ulp-pinfunc.h

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file +61 -0

new file mode 100644
index 0000000..44ad670a
@@ -0,0 +1,61 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
+ports and IOMUXC DDR for DDR interface.
+
+Note:
+This binding doc is only for the IOMUXC1 support in A7 Domain and it only
+supports generic pin config.
+
+Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
+binding.
+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible:	"fsl,imx7ulp-iomuxc1"
+- reg:		Should contain the base physical address and size of the iomuxc
+		registers.
+
+=== Pin Configuration Node ===
+- pinmux: One integers array, represents a group of pins mux setting.
+	The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
+	a specific function.
+
+	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
+	and config register as follows:
+	<mux_conf_reg input_reg mux_mode input_val>
+
+	Refer to imx7ulp-pinfunc.h in in device tree source folder for all
+	available imx7ulp PIN_FUNC_ID.
+
+Optional Properties:
+- drive-strength		Integer. Controls Drive Strength
+					0: Standard
+					1: Hi Driver
+- drive-push-pull		Bool. Enable Pin Push-pull
+- drive-open-drain		Bool. Enable Pin Open-drian
+- slew-rate:			Integer. Controls Slew Rate
+					0: Standard
+					1: Slow
+- bias-disable:			Bool. Pull disabled
+- bias-pull-down:		Bool. Pull down on pin
+- bias-pull-up:			Bool. Pull up on pin
+
+Examples:
+#include "imx7ulp-pinfunc.h"
+
+/* Pin Controller Node */
+iomuxc1: iomuxc at 40ac0000 {
+	compatible = "fsl,imx7ulp-iomuxc1";
+	reg = <0x40ac0000 0x1000>;
+
+	/* Pin Configuration Node */
+	pinctrl_lpuart4: lpuart4grp {
+		pinmux = <
+			IMX7ULP_PAD_PTC3__LPUART4_RX
+			IMX7ULP_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+};

arch/arm/boot/dts/imx7ulp-pinfunc.h new file +468 -0

468 lines not on this page · raw message

Signature · 1 line

2.7.4

Rob Herring

maintainer

2017-06-26 18:02 UTC #8 lore raw

PATCH v4 2/7 dt-bindings: pinctrl: add imx7ulp pinctrl binding doc

Quoted 24 lines · Dong Aisheng

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.
This patch adds the IOMUXC1 support for A7.
Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>
Cc devicetree at vger.kernel.org
Cc Linus Walleij <[email protected]>
Acked-by Shawn Guo <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
ChangeLog:
v3->v4:
* change pad name to IMX7ULP_PAD_X style
* switch to generic pinmux property
* input/output property are removed.
v2->v3:
* switch to generic input/output-enable property
v1->v2:
* add more descriptions in binding doc
* add missed prefix for private properties.
* move dt-bindings/pinctrl/imx7ulp-pinfunc.h to arch/arm/boot/dts

Quoted 6 lines

---
 .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt       |  61 +++
 arch/arm/boot/dts/imx7ulp-pinfunc.h                | 468 +++++++++++++++++++++
 2 files changed, 529 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/imx7ulp-pinfunc.h

Acked-by Rob Herring <[email protected]>

Dong Aisheng

author maintainer

2017-06-21 11:59 UTC #9 lore raw

PATCH v4 3/7 pinctrl: imx: switch to use the generic pinmux property

The generic pinmux property seems to be more suitable for IMX. So we change to use 'pinmux' instead of 'pins'.

Cc Linus Walleij <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Bai Ping <[email protected]>

---
ChangeLog:
* new patch

---
 drivers/pinctrl/freescale/pinctrl-imx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +3 -3

index 72aca75..fc1ba3c 100644
@@ -563,14 +563,14 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
 	 * do sanity check and calculate pins number
 	 *
 	 * First try legacy 'fsl,pins' property, then fall back to the
-	 * generic 'pins'.
+	 * generic 'pinmux'.
 	 *
-	 * Note: for generic 'pins' case, there's no CONFIG part in
+	 * Note: for generic 'pinmux' case, there's no CONFIG part in
 	 * the binding format.
 	 */
 	list = of_get_property(np, "fsl,pins", &size);
 	if (!list) {
-		list = of_get_property(np, "pins", &size);
+		list = of_get_property(np, "pinmux", &size);
 		if (!list) {
 			dev_err(info->dev,
 				"no fsl,pins and pins property in node %s\n",

Signature · 1 line

2.7.4

A.s. Dong

author maintainer

2017-07-12 13:57 UTC #10 lore raw

PATCH v4 3/7 pinctrl: imx: switch to use the generic pinmux property

Hi Shawn,

Quoted 10 lines

-----Original Message-----
From: Dong Aisheng [mailto:aisheng.dong at nxp.com]
Sent: Wednesday, June 21, 2017 8:00 PM
To: linux-gpio at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org; linus.walleij at linaro.org; shawnguo at kernel.org; stefan at agner.ch; Jacky Bai; Andy Duan; kernel at pengutronix.de; A.s. Dong
Subject: [PATCH V4 3/7] pinctrl: imx: switch to use the generic pinmux property

Quoted 8 lines

The generic pinmux property seems to be more suitable for IMX. So we change to use 'pinmux' instead of 'pins'.
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

Would you help review this minor change?

I will collect your ACKs and resent based on 4.13 RC1.

Regards
Dong Aisheng

Quoted 33 lines

---
ChangeLog:
* new patch

---
 drivers/pinctrl/freescale/pinctrl-imx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +3 -3

index 72aca75..fc1ba3c 100644
@@ -563,14 +563,14 @@ static int imx_pinctrl_parse_groups(struct
 device_node *np,
 	 * do sanity check and calculate pins number
 	 *
 	 * First try legacy 'fsl,pins' property, then fall back to the
-	 * generic 'pins'.
+	 * generic 'pinmux'.
 	 *
-	 * Note: for generic 'pins' case, there's no CONFIG part in
+	 * Note: for generic 'pinmux' case, there's no CONFIG part in
 	 * the binding format.
 	 */
 	list = of_get_property(np, "fsl,pins", &size);
 	if (!list) {
-		list = of_get_property(np, "pins", &size);
+		list = of_get_property(np, "pinmux", &size);
 		if (!list) {
 			dev_err(info->dev,

"no fsl,pins and pins property in node %s\n",
--
2.7.4

Shawn Guo

2017-07-13 08:43 UTC #11 lore raw

PATCH v4 3/7 pinctrl: imx: switch to use the generic pinmux property

Quoted 7 lines · Dong Aisheng

The generic pinmux property seems to be more suitable for IMX. So we change to use 'pinmux' instead of 'pins'.
Cc Linus Walleij <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

Dong Aisheng

author maintainer

2017-06-21 11:59 UTC #12 lore raw

PATCH v4 4/7 pinctrl: imx: add imx7ulp driver

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.

This patch adds the IOMUXC1 support for A7.
It only supports generic pin config.

Cc Linus Walleij <[email protected]>

Cc Bai Ping <[email protected]>

Signed-off-by Fugang Duan <[email protected]>

---
ChangeLog:
v3->v4:
* Change pad name to IMX7ULP_PAD_X style
* remove input/output generic property decodes as the standard input/out property name are still under discussing. It will be added back once it's determined.
v2->v3:
* Removed custom nxp,[output|input]-buffer-enable properties, instead, use generic input-enable and output enable.
v1->v2:
* no changes

---
 drivers/pinctrl/freescale/Kconfig           |   7 +
 drivers/pinctrl/freescale/Makefile          |   1 +
 drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 338 ++++++++++++++++++++++++++++
 3 files changed, 346 insertions(+)
 create mode 100644 drivers/pinctrl/freescale/pinctrl-imx7ulp.c

drivers/pinctrl/freescale/Kconfig +7 -0

index 0b266b2..4dbc576 100644
@@ -103,6 +103,13 @@ config PINCTRL_IMX7D
 	help
 	  Say Y here to enable the imx7d pinctrl driver
 
+config PINCTRL_IMX7ULP
+	bool "IMX7ULP pinctrl driver"
+	depends on SOC_IMX7ULP
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the imx7ulp pinctrl driver
+
 config PINCTRL_VF610
 	bool "Freescale Vybrid VF610 pinctrl driver"
 	depends on SOC_VF610

drivers/pinctrl/freescale/Makefile +1 -0

index d44c9e2..525a5ff 100644
@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_IMX6SL)	+= pinctrl-imx6sl.o
 obj-$(CONFIG_PINCTRL_IMX6SX)	+= pinctrl-imx6sx.o
 obj-$(CONFIG_PINCTRL_IMX6UL)	+= pinctrl-imx6ul.o
 obj-$(CONFIG_PINCTRL_IMX7D)	+= pinctrl-imx7d.o
+obj-$(CONFIG_PINCTRL_IMX7ULP)	+= pinctrl-imx7ulp.o
 obj-$(CONFIG_PINCTRL_VF610)	+= pinctrl-vf610.o
 obj-$(CONFIG_PINCTRL_MXS)	+= pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_IMX23)	+= pinctrl-imx23.o

drivers/pinctrl/freescale/pinctrl-imx7ulp.c new file +338 -0

338 lines not on this page · raw message

Signature · 1 line

2.7.4

Dong Aisheng

author maintainer

2017-06-21 11:59 UTC #13 lore raw

PATCH v4 5/7 pinctrl: imx: remove gpio_request_enable and gpio_disable_free

gpio_request_enable/disable_free actually are not quite necessary as standard IMX pinctrl binding already sets GPIO mux from device tree, e.g. VF610_PAD_PTB20__GPIO_42 or MX7D_PAD_SD2_CD_B__GPIO5_IO9 No need to do it again in gpio_request_enable.

And according to Stefan:
"For all GPIO I checked in upstream device trees we assign a pinctrl to the same node, so in all cases gpio_request_enable/disable is really unnecessary."

So it should be safe to simply remove it.

Cc Stefan Agner <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Alexandre Courbot <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Fugang Duan <[email protected]>

Cc Bai Ping <[email protected]>

---
ChangeLog:
* New patch.
Instead of fixing gpio_request_enable/disable, we decided to remove it after dicussion with Stefan (see blow).
https://www.spinics.net/lists/arm-kernel/msg583154.html

---
 drivers/pinctrl/freescale/pinctrl-imx.c | 69 ---------------------------------
 1 file changed, 69 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +0 ~~-69~~

index fc1ba3c..505fe79 100644
@@ -255,73 +255,6 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 	return 0;
 }
 
-static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
-			struct pinctrl_gpio_range *range, unsigned offset)
-{
-	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-	struct imx_pinctrl_soc_info *info = ipctl->info;
-	const struct imx_pin_reg *pin_reg;
-	struct group_desc *grp;
-	struct imx_pin *imx_pin;
-	unsigned int pin, group;
-	u32 reg;
-
-	/* Currently implementation only for shared mux/conf register */
-	if (!(info->flags & SHARE_MUX_CONF_REG))
-		return 0;
-
-	pin_reg = &info->pin_regs[offset];
-	if (pin_reg->mux_reg == -1)
-		return -EINVAL;
-
-	/* Find the pinctrl config with GPIO mux mode for the requested pin */
-	for (group = 0; group < pctldev->num_groups; group++) {
-		grp = pinctrl_generic_get_group(pctldev, group);
-		if (!grp)
-			continue;
-		for (pin = 0; pin < grp->num_pins; pin++) {
-			imx_pin = &((struct imx_pin *)(grp->data))[pin];
-			if (imx_pin->pin == offset && !imx_pin->mux_mode)
-				goto mux_pin;
-		}
-	}
-
-	return -EINVAL;
-
-mux_pin:
-	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~info->mux_mask;
-	reg |= imx_pin->config;
-	writel(reg, ipctl->base + pin_reg->mux_reg);
-
-	return 0;
-}
-
-static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
-			struct pinctrl_gpio_range *range, unsigned offset)
-{
-	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-	struct imx_pinctrl_soc_info *info = ipctl->info;
-	const struct imx_pin_reg *pin_reg;
-	u32 reg;
-
-	/*
-	 * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
-	 * They are part of the shared mux/conf register.
-	 */
-	if (!(info->flags & SHARE_MUX_CONF_REG))
-		return;
-
-	pin_reg = &info->pin_regs[offset];
-	if (pin_reg->mux_reg == -1)
-		return;
-
-	/* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
-	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~0x7;
-	writel(reg, ipctl->base + pin_reg->mux_reg);
-}
-
 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 	   struct pinctrl_gpio_range *range, unsigned offset, bool input)
 {

@@ -357,8 +290,6 @@ static const struct pinmux_ops imx_pmx_ops = {
 	.get_function_name = pinmux_generic_get_function_name,
 	.get_function_groups = pinmux_generic_get_function_groups,
 	.set_mux = imx_pmx_set,
-	.gpio_request_enable = imx_pmx_gpio_request_enable,
-	.gpio_disable_free = imx_pmx_gpio_disable_free,
 	.gpio_set_direction = imx_pmx_gpio_set_direction,
 };

Signature · 1 line

2.7.4

Stefan Agner

2017-06-27 03:47 UTC #14 lore raw

PATCH v4 5/7 pinctrl: imx: remove gpio_request_enable and gpio_disable_free

Quoted 11 lines · Dong Aisheng

gpio_request_enable/disable_free actually are not quite necessary as standard IMX pinctrl binding already sets GPIO mux from device tree, e.g. VF610_PAD_PTB20__GPIO_42 or MX7D_PAD_SD2_CD_B__GPIO5_IO9 No need to do it again in gpio_request_enable.
And according to Stefan:
"For all GPIO I checked in upstream device trees we assign a pinctrl to the same node, so in all cases gpio_request_enable/disable is really unnecessary."
So it should be safe to simply remove it.

Thanks looks good.

I would add a comment that this changes semantics for Vybrid, e.g.

"The two functions have been introduced for Vybrid (through SHARE_MUX_CONF_REG) and mux pins as GPIOs automatically when a GPIO gets requested. The automatic mux is optional by the pinmux/gpio subsystem semantics, and other NXP devices do not use it, instead an explicit pinctrl node is added in the device tree to mux GPIOs where required. Hence this change aligns Vybrid to other NXP (i.MX) devices.

Note that all upstream device tree assign proper pinctrl properties where GPIOs are used so no change is necessary for device trees."

Otherwise:

Acked-by Stefan Agner <[email protected]>

--
Stefan

Quoted 107 lines

Cc Stefan Agner <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Alexandre Courbot <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Fugang Duan <[email protected]>

Cc Bai Ping <[email protected]>

---
ChangeLog:
* New patch.
Instead of fixing gpio_request_enable/disable, we decided to remove it after dicussion with Stefan (see blow).
https://www.spinics.net/lists/arm-kernel/msg583154.html

---
 drivers/pinctrl/freescale/pinctrl-imx.c | 69 ---------------------------------
 1 file changed, 69 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +0 ~~-67~~

index fc1ba3c..505fe79 100644
@@ -255,73 +255,6 @@ static int imx_pmx_set(struct pinctrl_dev
 *pctldev, unsigned selector,
 	return 0;
 }
 
-static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
-			struct pinctrl_gpio_range *range, unsigned offset)
-{
-	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-	struct imx_pinctrl_soc_info *info = ipctl->info;
-	const struct imx_pin_reg *pin_reg;
-	struct group_desc *grp;
-	struct imx_pin *imx_pin;
-	unsigned int pin, group;
-	u32 reg;
-
-	/* Currently implementation only for shared mux/conf register */
-	if (!(info->flags & SHARE_MUX_CONF_REG))
-		return 0;
-
-	pin_reg = &info->pin_regs[offset];
-	if (pin_reg->mux_reg == -1)
-		return -EINVAL;
-
-	/* Find the pinctrl config with GPIO mux mode for the requested pin */
-	for (group = 0; group < pctldev->num_groups; group++) {
-		grp = pinctrl_generic_get_group(pctldev, group);
-		if (!grp)
-			continue;
-		for (pin = 0; pin < grp->num_pins; pin++) {
-			imx_pin = &((struct imx_pin *)(grp->data))[pin];
-			if (imx_pin->pin == offset && !imx_pin->mux_mode)
-				goto mux_pin;
-		}
-	}
-
-	return -EINVAL;
-
-mux_pin:
-	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~info->mux_mask;
-	reg |= imx_pin->config;
-	writel(reg, ipctl->base + pin_reg->mux_reg);
-
-	return 0;
-}
-
-static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
-			struct pinctrl_gpio_range *range, unsigned offset)
-{
-	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-	struct imx_pinctrl_soc_info *info = ipctl->info;
-	const struct imx_pin_reg *pin_reg;
-	u32 reg;
-
-	/*
-	 * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
-	 * They are part of the shared mux/conf register.
-	 */
-	if (!(info->flags & SHARE_MUX_CONF_REG))
-		return;
-
-	pin_reg = &info->pin_regs[offset];
-	if (pin_reg->mux_reg == -1)
-		return;
-
-	/* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
-	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~0x7;
-	writel(reg, ipctl->base + pin_reg->mux_reg);
-}
-
 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 	   struct pinctrl_gpio_range *range, unsigned offset, bool input)

{

drivers/pinctrl/freescale/pinctrl-imx.c +0 -2

@@ -357,8 +290,6 @@ static const struct pinmux_ops imx_pmx_ops = {
 	.get_function_name = pinmux_generic_get_function_name,
 	.get_function_groups = pinmux_generic_get_function_groups,
 	.set_mux = imx_pmx_set,
-	.gpio_request_enable = imx_pmx_gpio_request_enable,
-	.gpio_disable_free = imx_pmx_gpio_disable_free,
 	.gpio_set_direction = imx_pmx_gpio_set_direction,
 };

A.s. Dong

author maintainer

2017-06-27 05:27 UTC #15 lore raw

PATCH v4 5/7 pinctrl: imx: remove gpio_request_enable and gpio_disable_free

Quoted 34 lines

-----Original Message-----
From: Stefan Agner [mailto:stefan at agner.ch]
Sent: Tuesday, June 27, 2017 11:48 AM
To: A.s. Dong
Cc: linux-gpio at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linus.walleij at linaro.org; shawnguo at kernel.org; Jacky Bai; Andy Duan; kernel at pengutronix.de; Alexandre Courbot
Subject: Re: [PATCH V4 5/7] pinctrl: imx: remove gpio_request_enable and gpio_disable_free
Quoted 11 lines · Dong Aisheng
gpio_request_enable/disable_free actually are not quite necessary as standard IMX pinctrl binding already sets GPIO mux from device tree, e.g. VF610_PAD_PTB20__GPIO_42 or MX7D_PAD_SD2_CD_B__GPIO5_IO9 No need to do it again in gpio_request_enable.
And according to Stefan:
"For all GPIO I checked in upstream device trees we assign a pinctrl to the same node, so in all cases gpio_request_enable/disable is really unnecessary."
So it should be safe to simply remove it.
Thanks looks good.
I would add a comment that this changes semantics for Vybrid, e.g.
"The two functions have been introduced for Vybrid (through SHARE_MUX_CONF_REG) and mux pins as GPIOs automatically when a GPIO gets requested. The automatic mux is optional by the pinmux/gpio subsystem semantics, and other NXP devices do not use it, instead an explicit pinctrl node is added in the device tree to mux GPIOs where required. Hence this change aligns Vybrid to other NXP (i.MX) devices.

Quoted 3 lines

Note that all upstream device tree assign proper pinctrl properties where GPIOs are used so no change is necessary for device trees."

The comments looks ok to me.

Linus,
Would you help append it when pick the patch?

Stefan,
Would you help review imx7ulp GPIO patches as well after this pinctrl change?

Regards
Dong Aisheng

Quoted 115 lines

Otherwise:

Acked-by Stefan Agner <[email protected]>

--
Stefan

Quoted 9 lines

Cc Stefan Agner <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Alexandre Courbot <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Fugang Duan <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

Quoted 4 lines

---
ChangeLog:
* New patch.
Instead of fixing gpio_request_enable/disable, we decided to remove

Quoted 27 lines

after dicussion with Stefan (see blow).
https://www.spinics.net/lists/arm-kernel/msg583154.html

---
 drivers/pinctrl/freescale/pinctrl-imx.c | 69
---------------------------------
 1 file changed, 69 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +0 ~~-10~~

index fc1ba3c..505fe79 100644
@@ -255,73 +255,6 @@ static int imx_pmx_set(struct pinctrl_dev
 *pctldev, unsigned selector,
 	return 0;
 }
 
-static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
-			struct pinctrl_gpio_range *range, unsigned offset)
-{
-	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-	struct imx_pinctrl_soc_info *info = ipctl->info;
-	const struct imx_pin_reg *pin_reg;
-	struct group_desc *grp;
-	struct imx_pin *imx_pin;
-	unsigned int pin, group;
-	u32 reg;

drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pmx_set(struct pinctrl_dev · line 278

Quoted 10 lines

drivers/pinctrl/freescale/pinctrl-imx.c +0 ~~-10~~

-
-	/* Currently implementation only for shared mux/conf register */
-	if (!(info->flags & SHARE_MUX_CONF_REG))
-		return 0;
-
-	pin_reg = &info->pin_regs[offset];
-	if (pin_reg->mux_reg == -1)
-		return -EINVAL;
-
-	/* Find the pinctrl config with GPIO mux mode for the requested pin

Quoted 39 lines

drivers/pinctrl/freescale/pinctrl-imx.c +0 ~~-39~~

-	for (group = 0; group < pctldev->num_groups; group++) {
-		grp = pinctrl_generic_get_group(pctldev, group);
-		if (!grp)
-			continue;
-		for (pin = 0; pin < grp->num_pins; pin++) {
-			imx_pin = &((struct imx_pin *)(grp->data))[pin];
-			if (imx_pin->pin == offset && !imx_pin->mux_mode)
-				goto mux_pin;
-		}
-	}
-
-	return -EINVAL;
-
-mux_pin:
-	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~info->mux_mask;
-	reg |= imx_pin->config;
-	writel(reg, ipctl->base + pin_reg->mux_reg);
-
-	return 0;
-}
-
-static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
-			struct pinctrl_gpio_range *range, unsigned offset)
-{
-	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-	struct imx_pinctrl_soc_info *info = ipctl->info;
-	const struct imx_pin_reg *pin_reg;
-	u32 reg;
-
-	/*
-	 * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
-	 * They are part of the shared mux/conf register.
-	 */
-	if (!(info->flags & SHARE_MUX_CONF_REG))
-		return;
-
-	pin_reg = &info->pin_regs[offset];
-	if (pin_reg->mux_reg == -1)

drivers/pinctrl/freescale/pinctrl-imx.c static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, · line 259

Quoted 10 lines

drivers/pinctrl/freescale/pinctrl-imx.c +0 -8

-		return;
-
-	/* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
-	reg = readl(ipctl->base + pin_reg->mux_reg);
-	reg &= ~0x7;
-	writel(reg, ipctl->base + pin_reg->mux_reg);
-}
-
 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 	   struct pinctrl_gpio_range *range, unsigned offset, bool input)

{

Quoted 7 lines

drivers/pinctrl/freescale/pinctrl-imx.c +0 -2

@@ -357,8 +290,6 @@ static const struct pinmux_ops imx_pmx_ops = {
 	.get_function_name = pinmux_generic_get_function_name,
 	.get_function_groups = pinmux_generic_get_function_groups,
 	.set_mux = imx_pmx_set,
-	.gpio_request_enable = imx_pmx_gpio_request_enable,
-	.gpio_disable_free = imx_pmx_gpio_disable_free,
 	.gpio_set_direction = imx_pmx_gpio_set_direction,  };

Dong Aisheng

author maintainer

2017-06-21 11:59 UTC #16 lore raw

PATCH v4 6/7 pinctrl: imx: make imx_pmx_ops.gpio_set_direction platform specific callbacks

Various IMX platforms may have different imx_pmx_ops.gpio_set_direction implementations, so let's make it platform specific callbacks instead of the fixed common one.

Currently only VF610 platform implements it. No function level changes.

Cc Stefan Agner <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Alexandre Courbot <[email protected]>

Cc Shawn Guo <[email protected]>

---
ChangeLog:
* new patch.

---
 drivers/pinctrl/freescale/pinctrl-imx.c   | 48 +++----------------------------
 drivers/pinctrl/freescale/pinctrl-imx.h   | 20 +++++++++++++
 drivers/pinctrl/freescale/pinctrl-vf610.c | 25 ++++++++++++++++
 3 files changed, 49 insertions(+), 44 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +4 ~~-44~~

index 505fe79..ad23e39 100644
@@ -35,18 +35,6 @@
 #define IMX_NO_PAD_CTL	0x80000000	/* no pin config need */
 #define IMX_PAD_SION 0x40000000		/* set SION */
 
-/**
- * @dev: a pointer back to containing device
- * @base: the offset to the controller in virtual memory
- */
-struct imx_pinctrl {
-	struct device *dev;
-	struct pinctrl_dev *pctl;
-	void __iomem *base;
-	void __iomem *input_sel_base;
-	struct imx_pinctrl_soc_info *info;
-};
-
 static inline const struct group_desc *imx_pinctrl_find_group_by_name(
 				struct pinctrl_dev *pctldev,
 				const char *name)

@@ -255,42 +243,11 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 	return 0;
 }
 
-static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
-	   struct pinctrl_gpio_range *range, unsigned offset, bool input)
-{
-	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-	struct imx_pinctrl_soc_info *info = ipctl->info;
-	const struct imx_pin_reg *pin_reg;
-	u32 reg;
-
-	/*
-	 * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
-	 * They are part of the shared mux/conf register.
-	 */
-	if (!(info->flags & SHARE_MUX_CONF_REG))
-		return 0;
-
-	pin_reg = &info->pin_regs[offset];
-	if (pin_reg->mux_reg == -1)
-		return -EINVAL;
-
-	/* IBE always enabled allows us to read the value "on the wire" */
-	reg = readl(ipctl->base + pin_reg->mux_reg);
-	if (input)
-		reg &= ~0x2;
-	else
-		reg |= 0x2;
-	writel(reg, ipctl->base + pin_reg->mux_reg);
-
-	return 0;
-}
-
-static const struct pinmux_ops imx_pmx_ops = {
+struct pinmux_ops imx_pmx_ops = {
 	.get_functions_count = pinmux_generic_get_function_count,
 	.get_function_name = pinmux_generic_get_function_name,
 	.get_function_groups = pinmux_generic_get_function_groups,
 	.set_mux = imx_pmx_set,
-	.gpio_set_direction = imx_pmx_gpio_set_direction,
 };
 
 /* decode generic config into raw register values */

@@ -793,6 +750,9 @@ int imx_pinctrl_probe(struct platform_device *pdev,
 	imx_pinctrl_desc->custom_params = info->custom_params;
 	imx_pinctrl_desc->num_custom_params = info->num_custom_params;
 
+	/* platform specific callback */
+	imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
+
 	mutex_init(&info->mutex);
 
 	ipctl->info = info;

drivers/pinctrl/freescale/pinctrl-imx.h +20 -0

index 880bba7..5aa22b5 100644
@@ -16,9 +16,12 @@
 #define __DRIVERS_PINCTRL_IMX_H
 
 #include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
 
 struct platform_device;
 
+extern struct pinmux_ops imx_pmx_ops;
+
 /**
  * struct imx_pin - describes a single i.MX pin
  * @pin: the pin_id of this pin

@@ -76,6 +79,23 @@ struct imx_pinctrl_soc_info {
 	unsigned int num_decodes;
 	void (*fixup)(unsigned long *configs, unsigned int num_configs,
 		      u32 *raw_config);
+
+	int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
+				  struct pinctrl_gpio_range *range,
+				  unsigned offset,
+				  bool input);
+};
+
+/**
+ * @dev: a pointer back to containing device
+ * @base: the offset to the controller in virtual memory
+ */
+struct imx_pinctrl {
+	struct device *dev;
+	struct pinctrl_dev *pctl;
+	void __iomem *base;
+	void __iomem *input_sel_base;
+	struct imx_pinctrl_soc_info *info;
 };
 
 #define IMX_CFG_PARAMS_DECODE(p, m, o) \

drivers/pinctrl/freescale/pinctrl-vf610.c +25 -0

index 3bd8556..ac18bb6 100644
@@ -295,10 +295,35 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
 	IMX_PINCTRL_PIN(VF610_PAD_PTA7),
 };
 
+static int vf610_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+					struct pinctrl_gpio_range *range,
+					unsigned offset, bool input)
+{
+	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	struct imx_pinctrl_soc_info *info = ipctl->info;
+	const struct imx_pin_reg *pin_reg;
+	u32 reg;
+
+	pin_reg = &info->pin_regs[offset];
+	if (pin_reg->mux_reg == -1)
+		return -EINVAL;
+
+	/* IBE always enabled allows us to read the value "on the wire" */
+	reg = readl(ipctl->base + pin_reg->mux_reg);
+	if (input)
+		reg &= ~0x2;
+	else
+		reg |= 0x2;
+	writel(reg, ipctl->base + pin_reg->mux_reg);
+
+	return 0;
+}
+
 static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
 	.pins = vf610_pinctrl_pads,
 	.npins = ARRAY_SIZE(vf610_pinctrl_pads),
 	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+	.gpio_set_direction = vf610_pmx_gpio_set_direction,
 	.mux_mask = 0x700000,
 	.mux_shift = 20,
 };

Signature · 1 line

2.7.4

Stefan Agner

2017-06-27 03:53 UTC #17 lore raw

PATCH v4 6/7 pinctrl: imx: make imx_pmx_ops.gpio_set_direction platform specific callbacks

Quoted 5 lines · Dong Aisheng

Various IMX platforms may have different imx_pmx_ops.gpio_set_direction implementations, so let's make it platform specific callbacks instead of the fixed common one.
Currently only VF610 platform implements it. No function level changes.

Adds an indirection, but I feel this is necessary since we have platform differences how GPIO directions are handled...

So:

Acked-by Stefan Agner <[email protected]>

--
Stefan

Quoted 179 lines

Cc Stefan Agner <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Alexandre Courbot <[email protected]>

Cc Shawn Guo <[email protected]>

---
ChangeLog:
* new patch.

---
 drivers/pinctrl/freescale/pinctrl-imx.c   | 48 +++----------------------------
 drivers/pinctrl/freescale/pinctrl-imx.h   | 20 +++++++++++++
 drivers/pinctrl/freescale/pinctrl-vf610.c | 25 ++++++++++++++++
 3 files changed, 49 insertions(+), 44 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +1 ~~-44~~

index 505fe79..ad23e39 100644
@@ -35,18 +35,6 @@
 #define IMX_NO_PAD_CTL	0x80000000	/* no pin config need */
 #define IMX_PAD_SION 0x40000000		/* set SION */
 
-/**
- * @dev: a pointer back to containing device
- * @base: the offset to the controller in virtual memory
- */
-struct imx_pinctrl {
-	struct device *dev;
-	struct pinctrl_dev *pctl;
-	void __iomem *base;
-	void __iomem *input_sel_base;
-	struct imx_pinctrl_soc_info *info;
-};
-
 static inline const struct group_desc *imx_pinctrl_find_group_by_name(
 				struct pinctrl_dev *pctldev,
 				const char *name)

@@ -255,42 +243,11 @@ static int imx_pmx_set(struct pinctrl_dev
 *pctldev, unsigned selector,
 	return 0;
 }
 
-static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
-	   struct pinctrl_gpio_range *range, unsigned offset, bool input)
-{
-	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-	struct imx_pinctrl_soc_info *info = ipctl->info;
-	const struct imx_pin_reg *pin_reg;
-	u32 reg;
-
-	/*
-	 * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
-	 * They are part of the shared mux/conf register.
-	 */
-	if (!(info->flags & SHARE_MUX_CONF_REG))
-		return 0;
-
-	pin_reg = &info->pin_regs[offset];
-	if (pin_reg->mux_reg == -1)
-		return -EINVAL;
-
-	/* IBE always enabled allows us to read the value "on the wire" */
-	reg = readl(ipctl->base + pin_reg->mux_reg);
-	if (input)
-		reg &= ~0x2;
-	else
-		reg |= 0x2;
-	writel(reg, ipctl->base + pin_reg->mux_reg);
-
-	return 0;
-}
-
-static const struct pinmux_ops imx_pmx_ops = {
+struct pinmux_ops imx_pmx_ops = {
 	.get_functions_count = pinmux_generic_get_function_count,
 	.get_function_name = pinmux_generic_get_function_name,
 	.get_function_groups = pinmux_generic_get_function_groups,
 	.set_mux = imx_pmx_set,
-	.gpio_set_direction = imx_pmx_gpio_set_direction,
 };

/* decode generic config into raw register values */

drivers/pinctrl/freescale/pinctrl-imx.c +3 -0

@@ -793,6 +750,9 @@ int imx_pinctrl_probe(struct platform_device *pdev,
 	imx_pinctrl_desc->custom_params = info->custom_params;
 	imx_pinctrl_desc->num_custom_params = info->num_custom_params;
 
+	/* platform specific callback */
+	imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
+
 	mutex_init(&info->mutex);
 
 	ipctl->info = info;

drivers/pinctrl/freescale/pinctrl-imx.h +20 -0

index 880bba7..5aa22b5 100644
@@ -16,9 +16,12 @@
 #define __DRIVERS_PINCTRL_IMX_H
 
 #include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
 
 struct platform_device;
 
+extern struct pinmux_ops imx_pmx_ops;
+
 /**
  * struct imx_pin - describes a single i.MX pin
  * @pin: the pin_id of this pin

@@ -76,6 +79,23 @@ struct imx_pinctrl_soc_info {
 	unsigned int num_decodes;
 	void (*fixup)(unsigned long *configs, unsigned int num_configs,
 		      u32 *raw_config);
+
+	int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
+				  struct pinctrl_gpio_range *range,
+				  unsigned offset,
+				  bool input);
+};
+
+/**
+ * @dev: a pointer back to containing device
+ * @base: the offset to the controller in virtual memory
+ */
+struct imx_pinctrl {
+	struct device *dev;
+	struct pinctrl_dev *pctl;
+	void __iomem *base;
+	void __iomem *input_sel_base;
+	struct imx_pinctrl_soc_info *info;
 };
 
 #define IMX_CFG_PARAMS_DECODE(p, m, o) \

drivers/pinctrl/freescale/pinctrl-vf610.c +25 -0

index 3bd8556..ac18bb6 100644
@@ -295,10 +295,35 @@ static const struct pinctrl_pin_desc
 vf610_pinctrl_pads[] = {
 	IMX_PINCTRL_PIN(VF610_PAD_PTA7),
 };
 
+static int vf610_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+					struct pinctrl_gpio_range *range,
+					unsigned offset, bool input)
+{
+	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	struct imx_pinctrl_soc_info *info = ipctl->info;
+	const struct imx_pin_reg *pin_reg;
+	u32 reg;
+
+	pin_reg = &info->pin_regs[offset];
+	if (pin_reg->mux_reg == -1)
+		return -EINVAL;
+
+	/* IBE always enabled allows us to read the value "on the wire" */
+	reg = readl(ipctl->base + pin_reg->mux_reg);
+	if (input)
+		reg &= ~0x2;
+	else
+		reg |= 0x2;
+	writel(reg, ipctl->base + pin_reg->mux_reg);
+
+	return 0;
+}
+
 static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
 	.pins = vf610_pinctrl_pads,
 	.npins = ARRAY_SIZE(vf610_pinctrl_pads),
 	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+	.gpio_set_direction = vf610_pmx_gpio_set_direction,
 	.mux_mask = 0x700000,
 	.mux_shift = 20,

};

Dong Aisheng

author maintainer

2017-06-21 11:59 UTC #18 lore raw

PATCH v4 7/7 pinctrl: pinctrl-imx7ulp: add gpio_set_direction support

Add gpio_set_direction support. This makes the driver support GPIO input/output dynamically change from userspace.

Cc Linus Walleij <[email protected]>

Cc Alexandre Courbot <[email protected]>

Cc Shawn Guo <[email protected]>

Cc Stefan Agner <[email protected]>

Cc Fugang Duan <[email protected]>

Cc Bai Ping <[email protected]>

---
ChangeLog:
* New patch. Derived from the original:
[PATCH 1/2] pinctrl: pinctrl-imx: add IBE and OBE SoC property

---
 drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

drivers/pinctrl/freescale/pinctrl-imx7ulp.c +26 -0

index 96127dc..b7bebb2 100644
@@ -259,6 +259,8 @@ static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
 };
 
+#define BM_OBE_ENABLED		BIT(17)
+#define BM_IBE_ENABLED		BIT(16)
 #define BM_LK_ENABLED		BIT(15)
 #define BM_MUX_MODE		0xf00
 #define BP_MUX_MODE		8

@@ -300,10 +302,34 @@ static void imx7ulp_cfg_params_fixup(unsigned long *configs,
 	}
 }
 
+static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+					  struct pinctrl_gpio_range *range,
+					  unsigned offset, bool input)
+{
+	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	struct imx_pinctrl_soc_info *info = ipctl->info;
+	const struct imx_pin_reg *pin_reg;
+	u32 reg;
+
+	pin_reg = &info->pin_regs[offset];
+	if (pin_reg->mux_reg == -1)
+		return -EINVAL;
+
+	reg = readl(ipctl->base + pin_reg->mux_reg);
+	if (input)
+		reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
+	else
+		reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
+	writel(reg, ipctl->base + pin_reg->mux_reg);
+
+	return 0;
+}
+
 static struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
 	.pins = imx7ulp_pinctrl_pads,
 	.npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
 	.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
+	.gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
 	.mux_mask = BM_MUX_MODE,
 	.mux_shift = BP_MUX_MODE,
 	.generic_pinconf = true,

Signature · 1 line

2.7.4

A.s. Dong

author maintainer

2017-07-12 13:59 UTC #19 lore raw

PATCH v4 7/7 pinctrl: pinctrl-imx7ulp: add gpio_set_direction support

Hi Shawn,

Quoted 21 lines

-----Original Message-----
From: Dong Aisheng [mailto:aisheng.dong at nxp.com]
Sent: Wednesday, June 21, 2017 8:00 PM
To: linux-gpio at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org; linus.walleij at linaro.org; shawnguo at kernel.org; stefan at agner.ch; Jacky Bai; Andy Duan; kernel at pengutronix.de; A.s. Dong; Alexandre Courbot
Subject: [PATCH V4 7/7] pinctrl: pinctrl-imx7ulp: add gpio_set_direction support
Add gpio_set_direction support. This makes the driver support GPIO input/output dynamically change from userspace.
Cc Linus Walleij <[email protected]>
Cc Alexandre Courbot <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Fugang Duan <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

Quoted 4 lines

---
ChangeLog:
* New patch. Derived from the original:
[PATCH 1/2] pinctrl: pinctrl-imx: add IBE and OBE SoC property

And this one.

Please help review.

Regards
Dong Aisheng

Quoted 58 lines

---
 drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 26
++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

drivers/pinctrl/freescale/pinctrl-imx7ulp.c +2 -0

index 96127dc..b7bebb2 100644
@@ -259,6 +259,8 @@ static const struct pinctrl_pin_desc
 imx7ulp_pinctrl_pads[] = {
 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
 };
 
+#define BM_OBE_ENABLED		BIT(17)
+#define BM_IBE_ENABLED		BIT(16)
 #define BM_LK_ENABLED		BIT(15)
 #define BM_MUX_MODE		0xf00

#define BP_MUX_MODE 8

drivers/pinctrl/freescale/pinctrl-imx7ulp.c +24 -0

@@ -300,10 +302,34 @@ static void imx7ulp_cfg_params_fixup(unsigned long
 *configs,
 	}
 }
 
+static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+					  struct pinctrl_gpio_range *range,
+					  unsigned offset, bool input)
+{
+	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+	struct imx_pinctrl_soc_info *info = ipctl->info;
+	const struct imx_pin_reg *pin_reg;
+	u32 reg;
+
+	pin_reg = &info->pin_regs[offset];
+	if (pin_reg->mux_reg == -1)
+		return -EINVAL;
+
+	reg = readl(ipctl->base + pin_reg->mux_reg);
+	if (input)
+		reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
+	else
+		reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
+	writel(reg, ipctl->base + pin_reg->mux_reg);
+
+	return 0;
+}
+
 static struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
 	.pins = imx7ulp_pinctrl_pads,
 	.npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
 	.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
+	.gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
 	.mux_mask = BM_MUX_MODE,
 	.mux_shift = BP_MUX_MODE,

.generic_pinconf = true,
--
2.7.4

Shawn Guo

2017-07-13 08:46 UTC #20 lore raw

PATCH v4 7/7 pinctrl: pinctrl-imx7ulp: add gpio_set_direction support

Quoted 10 lines · Dong Aisheng

Add gpio_set_direction support. This makes the driver support GPIO input/output dynamically change from userspace.
Cc Linus Walleij <[email protected]>
Cc Alexandre Courbot <[email protected]>
Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Fugang Duan <[email protected]>
Cc Bai Ping <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

A.s. Dong

author maintainer

2017-07-03 10:36 UTC #21 lore raw

v4 cover pinctrl: imx: add imx7ulp pinctrl support