hyper-v: avoid tsc calibration

PATCH New Vitaly Kuznetsov 2 participants 5 messages Jun 22, 2017

Subsystems (2)

x86 Hyper-V/Azure core and drivers

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Vitaly Kuznetsov

author

2017-06-22 10:07 UTC #0 lore raw

v2 cover hyper-v: avoid tsc calibration

Changes since v1:
- s/AVAILABELE/AVAILABLE/ fixing the typo [Thomas Gleixner]

Original description:

TSC calibration on virtual machines is always error prone. It was found that in nested environments Gen2 instances may get stuck on boot. As Hyper-V hosts provide us with all the required information we can easily avoid calibration. This is already done for other hypervisors (KVM, Vmware).

Vitaly Kuznetsov (2):
hyper-v: check frequency MSRs presence according to the specification
hyper-v: read TSC frequency from a synthetic MSR

 arch/x86/include/uapi/asm/hyperv.h | 15 ++++++---------
 arch/x86/kernel/cpu/mshyperv.c     | 18 +++++++++++++++++-
 2 files changed, 23 insertions(+), 10 deletions(-)

Signature · 1 line

2.9.4

Vitaly Kuznetsov

author

2017-06-22 10:08 UTC #1 lore raw

PATCH v2 1/2 hyper-v: check frequency MSRs presence according to the specification

Hyper-V TLFS specifies two bits which should be checked before accessing frequency MSRs:
- AccessFrequencyMsrs (BIT(11) in EAX) which indicates if we have access to frequency MSRs.
- FrequencyMsrsAvailable (BIT(8) in EDX) which indicates is these MSRs are present.
Rename and specify these bits accordingly.

Signed-off-by Vitaly Kuznetsov <[email protected]>

---
 arch/x86/include/uapi/asm/hyperv.h | 15 ++++++---------
 arch/x86/kernel/cpu/mshyperv.c     |  3 ++-
 2 files changed, 8 insertions(+), 10 deletions(-)

arch/x86/include/uapi/asm/hyperv.h +6 -9

index 432df4b..f4fef5a 100644
@@ -34,16 +34,10 @@
 #define HV_X64_MSR_REFERENCE_TSC		0x40000021
 
 /*
- * There is a single feature flag that signifies the presence of the MSR
- * that can be used to retrieve both the local APIC Timer frequency as
- * well as the TSC frequency.
+ * There is a single feature flag that signifies if the partition has access
+ * to MSRs with local APIC and TSC frequencies.
  */
-
-/* Local APIC timer frequency MSR (HV_X64_MSR_APIC_FREQUENCY) is available */
-#define HV_X64_MSR_APIC_FREQUENCY_AVAILABLE (1 << 11)
-
-/* TSC frequency MSR (HV_X64_MSR_TSC_FREQUENCY) is available */
-#define HV_X64_MSR_TSC_FREQUENCY_AVAILABLE (1 << 11)
+#define HV_X64_ACCESS_FREQUENCY_MSRS		(1 << 11)
 
 /*
  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM

@@ -73,6 +67,9 @@
   */
 #define HV_X64_MSR_STAT_PAGES_AVAILABLE		(1 << 8)
 
+/* Frequency MSRs available */
+#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE	(1 << 8)
+
 /* Crash MSR available */
 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)

arch/x86/kernel/cpu/mshyperv.c +2 -1

index 04cb8d3..3563c8e 100644
@@ -194,7 +194,8 @@ static void __init ms_hyperv_init_platform(void)
 	}
 
 #ifdef CONFIG_X86_LOCAL_APIC
-	if (ms_hyperv.features & HV_X64_MSR_APIC_FREQUENCY_AVAILABLE) {
+	if (ms_hyperv.features & HV_X64_ACCESS_FREQUENCY_MSRS &&
+	    ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
 		/*
 		 * Get the APIC frequency.
 		 */

Signature · 1 line

2.9.4

tip-bot for Vitaly Kuznetsov

merge bot

2017-06-22 13:41 UTC #2 lore raw

[tip:x86/hyperv] x86/hyperv: Check frequency MSRs presence according to the specification

x86/hyperv: Check frequency MSRs presence according to the specification

Commit-ID:  2cf0284223a40773bd0ec76a409a7cbf0607ca28
Gitweb:     http://git.kernel.org/tip/2cf0284223a40773bd0ec76a409a7cbf0607ca28
Author:     Vitaly Kuznetsov <[email protected]>
AuthorDate: Thu, 22 Jun 2017 18:07:29 +0800
Committer:  Thomas Gleixner <[email protected]>
CommitDate: Thu, 22 Jun 2017 15:35:11 +0200

x86/hyperv: Check frequency MSRs presence according to the specification

Hyper-V TLFS specifies two bits which should be checked before accessing frequency MSRs:

- AccessFrequencyMsrs (BIT(11) in EAX) which indicates if we have access to frequency MSRs.
- FrequencyMsrsAvailable (BIT(8) in EDX) which indicates is these MSRs are present.

Rename and specify these bits accordingly.

Signed-off-by Vitaly Kuznetsov <[email protected]>

Signed-off-by Thomas Gleixner <[email protected]>

Cc Stephen Hemminger <[email protected]>

Cc Haiyang Zhang <[email protected]>

Cc Ladi Prosek <[email protected]>

Cc Jork Loeser <[email protected]>

Cc [email protected]

Cc "K. Y. Srinivasan" <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

---
 arch/x86/include/uapi/asm/hyperv.h | 15 ++++++---------
 arch/x86/kernel/cpu/mshyperv.c     |  3 ++-
 2 files changed, 8 insertions(+), 10 deletions(-)

arch/x86/include/uapi/asm/hyperv.h +6 -9

index 432df4b..f4fef5a 100644
@@ -34,16 +34,10 @@
 #define HV_X64_MSR_REFERENCE_TSC		0x40000021
 
 /*
- * There is a single feature flag that signifies the presence of the MSR
- * that can be used to retrieve both the local APIC Timer frequency as
- * well as the TSC frequency.
+ * There is a single feature flag that signifies if the partition has access
+ * to MSRs with local APIC and TSC frequencies.
  */
-
-/* Local APIC timer frequency MSR (HV_X64_MSR_APIC_FREQUENCY) is available */
-#define HV_X64_MSR_APIC_FREQUENCY_AVAILABLE (1 << 11)
-
-/* TSC frequency MSR (HV_X64_MSR_TSC_FREQUENCY) is available */
-#define HV_X64_MSR_TSC_FREQUENCY_AVAILABLE (1 << 11)
+#define HV_X64_ACCESS_FREQUENCY_MSRS		(1 << 11)
 
 /*
  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM

@@ -73,6 +67,9 @@
   */
 #define HV_X64_MSR_STAT_PAGES_AVAILABLE		(1 << 8)
 
+/* Frequency MSRs available */
+#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE	(1 << 8)
+
 /* Crash MSR available */
 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)

arch/x86/kernel/cpu/mshyperv.c +2 -1

index 04cb8d3..3563c8e 100644
@@ -194,7 +194,8 @@ static void __init ms_hyperv_init_platform(void)
 	}
 
 #ifdef CONFIG_X86_LOCAL_APIC
-	if (ms_hyperv.features & HV_X64_MSR_APIC_FREQUENCY_AVAILABLE) {
+	if (ms_hyperv.features & HV_X64_ACCESS_FREQUENCY_MSRS &&
+	    ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
 		/*
 		 * Get the APIC frequency.
 		 */

Vitaly Kuznetsov

author

2017-06-22 10:07 UTC #3 lore raw

PATCH v2 2/2 hyper-v: read TSC frequency from a synthetic MSR

In reply to Vitaly Kuznetsov

It was found that SMI_TRESHOLD of 50000 is not enough for Hyper-V guests in nested environment and falling back to counting jiffies is not an option for Gen2 guests as they don't have PIT. As Hyper-V provides TSC frequency in a synthetic MSR we can just use this information instead of doing a error prone calibration.

Reported-by Ladi Prosek <[email protected]>

Tested-by Ladi Prosek <[email protected]>

Signed-off-by Vitaly Kuznetsov <[email protected]>

---
 arch/x86/kernel/cpu/mshyperv.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/x86/kernel/cpu/mshyperv.c +15 -0

index 3563c8e..200c521 100644
@@ -161,6 +161,15 @@ static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs)
 }
 #endif
 
+static unsigned long hv_get_tsc_khz(void)
+{
+	unsigned long freq;
+
+	rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq);
+
+	return freq/1000;
+}
+
 static void __init ms_hyperv_init_platform(void)
 {
 	int hv_host_info_eax;

@@ -193,6 +202,12 @@ static void __init ms_hyperv_init_platform(void)
 			hv_host_info_edx >> 24, hv_host_info_edx & 0xFFFFFF);
 	}
 
+	if (ms_hyperv.features & HV_X64_ACCESS_FREQUENCY_MSRS &&
+	    ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
+		x86_platform.calibrate_tsc = hv_get_tsc_khz;
+		x86_platform.calibrate_cpu = hv_get_tsc_khz;
+	}
+
 #ifdef CONFIG_X86_LOCAL_APIC
 	if (ms_hyperv.features & HV_X64_ACCESS_FREQUENCY_MSRS &&
 	    ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {

Signature · 1 line

2.9.4

tip-bot for Vitaly Kuznetsov

merge bot

2017-06-22 13:42 UTC #4 lore raw

[tip:x86/hyperv] x86/hyperv: Read TSC frequency from a synthetic MSR

x86/hyperv: Read TSC frequency from a synthetic MSR

Commit-ID:  71c2a2d0a81f096a2932fccb39a500116fece554
Gitweb:     http://git.kernel.org/tip/71c2a2d0a81f096a2932fccb39a500116fece554
Author:     Vitaly Kuznetsov <[email protected]>
AuthorDate: Thu, 22 Jun 2017 18:07:30 +0800
Committer:  Thomas Gleixner <[email protected]>
CommitDate: Thu, 22 Jun 2017 15:35:12 +0200

x86/hyperv: Read TSC frequency from a synthetic MSR

Reported-and-tested-by Ladi Prosek <[email protected]>

Signed-off-by Vitaly Kuznetsov <[email protected]>

Signed-off-by Thomas Gleixner <[email protected]>

Cc Stephen Hemminger <[email protected]>

Cc Haiyang Zhang <[email protected]>

Cc Jork Loeser <[email protected]>

Cc [email protected]

Cc "K. Y. Srinivasan" <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/cpu/mshyperv.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/x86/kernel/cpu/mshyperv.c +15 -0

index 3563c8e..70e717f 100644
@@ -161,6 +161,15 @@ static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs)
 }
 #endif
 
+static unsigned long hv_get_tsc_khz(void)
+{
+	unsigned long freq;
+
+	rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq);
+
+	return freq / 1000;
+}
+
 static void __init ms_hyperv_init_platform(void)
 {
 	int hv_host_info_eax;

@@ -193,6 +202,12 @@ static void __init ms_hyperv_init_platform(void)
 			hv_host_info_edx >> 24, hv_host_info_edx & 0xFFFFFF);
 	}
 
+	if (ms_hyperv.features & HV_X64_ACCESS_FREQUENCY_MSRS &&
+	    ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
+		x86_platform.calibrate_tsc = hv_get_tsc_khz;
+		x86_platform.calibrate_cpu = hv_get_tsc_khz;
+	}
+
 #ifdef CONFIG_X86_LOCAL_APIC
 	if (ms_hyperv.features & HV_X64_ACCESS_FREQUENCY_MSRS &&
 	    ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {