Documentation: atomic_ops.txt is core-api/atomic_ops.rst
Subsystems (2)
PATCH 1/1 Documentation: atomic_ops.txt is core-api/atomic_ops.rst
I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation.
Signed-off-by Palmer Dabbelt <[email protected]>
Acked-by Will Deacon <[email protected]>
--- Documentation/memory-barriers.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
Documentation/memory-barriers.txt +5 -5
@@ -498,11 +498,11 @@ And a couple of implicit varieties: This means that ACQUIRE acts as a minimal "acquire" operation and RELEASE acts as a minimal "release" operation. -A subset of the atomic operations described in atomic_ops.txt have ACQUIRE -and RELEASE variants in addition to fully-ordered and relaxed (no barrier -semantics) definitions. For compound atomics performing both a load and a -store, ACQUIRE semantics apply only to the load and RELEASE semantics apply -only to the store portion of the operation. +A subset of the atomic operations described in core-api/atomic_ops.rst have +ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no +barrier semantics) definitions. For compound atomics performing both a load +and a store, ACQUIRE semantics apply only to the load and RELEASE semantics +apply only to the store portion of the operation. Memory barriers are only required where there's a possibility of interaction between two CPUs or between a CPU and a device. If it can be guaranteed that
Signature · 1 line
2.13.0
Quoted 6 lines · Palmer Dabbelt
I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation.
Signed-off-by Palmer Dabbelt <[email protected]>Acked-by Will Deacon <[email protected]>
Good catch!
Acked-by Paul E. McKenney <[email protected]>
Quoted 28 lines
--- Documentation/memory-barriers.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)Documentation/memory-barriers.txt +5
-5@@ -498,11 +498,11 @@ And a couple of implicit varieties: This means that ACQUIRE acts as a minimal "acquire" operation and RELEASE acts as a minimal "release" operation. -A subset of the atomic operations described in atomic_ops.txt have ACQUIRE -and RELEASE variants in addition to fully-ordered and relaxed (no barrier -semantics) definitions. For compound atomics performing both a load and a -store, ACQUIRE semantics apply only to the load and RELEASE semantics apply -only to the store portion of the operation. +A subset of the atomic operations described in core-api/atomic_ops.rst have +ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no +barrier semantics) definitions. For compound atomics performing both a load +and a store, ACQUIRE semantics apply only to the load and RELEASE semantics +apply only to the store portion of the operation. Memory barriers are only required where there's a possibility of interaction between two CPUs or between a CPU and a device. If it can be guaranteed thatSignature · 1 line
2.13.0
Quoted 11 lines · On Fri, 23 Jun 2017 13:45:29 -0700 "Paul E. McKenney"…
Quoted 6 lines · Palmer Dabbelt
I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation.
Signed-off-by Palmer Dabbelt <[email protected]>Acked-by Will Deacon <[email protected]>Good catch!
Acked-by Paul E. McKenney <[email protected]>
Applied to the docs tree, thanks.
jon