drm/sun4i: hdmi: Implement I2C adapter for A10s DDC bus
PATCH v5 1/1 drm/sun4i: hdmi: Implement I2C adapter for A10s DDC bus
The documentation for drm_do_get_edid in drivers/gpu/drm/drm_edid.c states:
"As in the general case the DDC bus is accessible by the kernel at the I2C level, drivers must make all reasonable efforts to expose it as an I2C adapter and use drm_get_edid() instead of abusing this function."
Exposing the DDC bus as an I2C adapter is more beneficial as it can be used for purposes other than reading the EDID such as modifying the EDID or using the HDMI DDC pins as an I2C bus through the I2C dev interface from userspace (e.g. i2c-tools).
Implement this for A10s.
---
Changes for v5:
- Use devm_kzalloc instead of devm_kmemdup and remove const struct i2c_adapter
- Rework to use readl_poll_timeout for checking FIFO status
Changes for v4:
- Carry over copyright from initial I2C code into sun4i_hdmi_i2c.c
- Clean up indentation in sun4i_hdmi.h
- Rename SUN4I_HDMI_DDC_MAX_TRANSFER_SIZE to SUN4I_HDMI_DDC_BYTE_COUNT_MAX and group it under the SUN4I_HDMI_DDC_BYTE_COUNT_REG define, changing the value to use the GENMASK macro to make it clear that it is derived from the width of the field in the register
- Fix SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_UNDERFLOW typo which should be SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW
- Remove redundant rewriting of SUN4I_HDMI_DDC_INT_STATUS_REG register
- Change struct i2c_adapter to be const by using devm_kmemdup on creation
- Return -ETIMEDOUT instead of -EIO if there is timeout while transferring an I2C message
- Instead of waiting for 1-2 bytes to transfer, wait for the time it would take for remaining bytes to transfer (limited by FIFO size)
- Add additional comments
Changes for v3:
- Explain why drm_do_get_edid should be used and why it's better to expose it as an I2C adapter in commit message
- Reorder bit defines in descending order for consistency
- Keep old unused macros instead of removing them
- The v2 algorithm split large transfers into 16 byte transfers but this may cause a large single write to be treated as multiple writes causing data corruption. The algorithm has been reworked to not split larger transfers and make more use of the FIFO to avoid this.
- Moved the creation of the DDC clock from sun4i_hdmi_enc.c to sun4i_hdmi_i2c.c
- Reformatted code
- Instead of masking bits that we don't want to check for errors, explicitly check the error bits
- Clear error bits at start of transfer in case of error from previous transfer
- Poll for completion of FIFO clear after setting FIFO clear bit
Changes for v2:
- Rebased against Maxime's sunxi-drm/for-next branch
- Fix up error paths in sun4i_hdmi_bind so that the I2C adapter is deleted if any of the calls after the I2C adapter is created fails
- Remove unnecessary includes in sun4i_hdmi_i2c.c
drivers/gpu/drm/sun4i/Makefile | 1 + drivers/gpu/drm/sun4i/sun4i_hdmi.h | 23 ++++ drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 101 ++------------- drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c | 226 +++++++++++++++++++++++++++++++++ 4 files changed, 261 insertions(+), 90 deletions(-) create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c
drivers/gpu/drm/sun4i/Makefile +1 -0
@@ -2,6 +2,7 @@ sun4i-drm-y += sun4i_drv.o sun4i-drm-y += sun4i_framebuffer.o sun4i-drm-hdmi-y += sun4i_hdmi_enc.o +sun4i-drm-hdmi-y += sun4i_hdmi_i2c.o sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o
drivers/gpu/drm/sun4i/sun4i_hdmi.h +23 -0
@@ -96,6 +96,7 @@#define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31)#define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30)#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8) +#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE (1 << 8)#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8)#define SUN4I_HDMI_DDC_CTRL_RESET BIT(0)
@@ -105,14 +106,33 @@#define SUN4I_HDMI_DDC_ADDR_OFFSET (off) (((off) & 0xff) << 8)#define SUN4I_HDMI_DDC_ADDR_SLAVE (addr) ((addr) & 0xff) +#define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c +#define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION BIT(7) +#define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW BIT(6) +#define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW BIT(5) +#define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST BIT(4) +#define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR BIT(3) +#define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR BIT(2) +#define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR BIT(1) +#define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0) +#define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510#define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31) +#define SUN4I_HDMI_DDC_FIFO_STATUS_REG 0x514 +#define SUN4I_HDMI_DDC_FIFO_STATUS_FULL BIT(6) +#define SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY BIT(5) +#define SUN4I_HDMI_DDC_FIFO_STATUS_LEVEL_MASK GENMASK(4, 0) +#define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518 +#define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c +#define SUN4I_HDMI_DDC_BYTE_COUNT_MAX GENMASK(9, 0)#define SUN4I_HDMI_DDC_CMD_REG 0x520#define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6 +#define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ 5 +#define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3#define SUN4I_HDMI_DDC_CLK_REG 0x528#define SUN4I_HDMI_DDC_CLK_M (m) (((m) & 0x7) << 3)
@@ -146,6 +166,8 @@ struct sun4i_hdmi {struct clk *ddc_clk;struct clk *tmds_clk; +struct i2c_adapter *i2c; +struct sun4i_drv *drv;bool hdmi_monitor;
@@ -153,5 +175,6 @@ struct sun4i_hdmi {int sun4i_ddc_create (struct sun4i_hdmi *hdmi,struct clk *clk);int sun4i_tmds_create (struct sun4i_hdmi *hdmi); +int sun4i_hdmi_i2c_create (struct device *dev,struct sun4i_hdmi *hdmi);#endif /* _SUN4I_HDMI_H_ */
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +11 -90
154 lines not on this page · raw message
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +226 -0
226 lines not on this page · raw message
Signature · 1 line
2.13.1
Quoted 16 lines · Jonathan Liu
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +16
-0+#define SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK ( \ + SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION | \ + SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW | \ + SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW | \ + SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR | \ + SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR | \ + SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR \ +) + +static bool is_err_status (u32 int_status) +{ +return !!(int_status &SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK ); +} + +static bool is_fifo_flag_unset (struct sun4i_hdmi *hdmi,u32 *fifo_status, +u32 flag)
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 43
Quoted 10 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +10
-0+{ + *fifo_status =readl (hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG ); +return !(*fifo_status & flag); +} + +static int fifo_transfer (struct sun4i_hdmi *hdmi,u8 *buf,int len,bool read) +{ +/* 1 byte takes 9 clock cycles (8 bits + 1 ACK) */ +unsigned long byte_time =DIV_ROUND_UP (USEC_PER_SEC , +clk_get_rate (hdmi->ddc_clk)) *9 ;
There's no real need for it to be dynamic. The clock rate will not change, and the order of magnitude is roughly 100us, so let's just use that (and make a comment).
Quoted 9 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +9
-0+u32 int_status; +u32 fifo_status; +/* Read needs empty flag unset, write needs full flag unset */ +u32 flag = read ?SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY : +SUN4I_HDMI_DDC_FIFO_STATUS_FULL ; +int ret; + +/* Wait until error or FIFO ready */ + ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 62
Quoted 10 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +10
-0+ int_status, +is_err_status (int_status) || +is_fifo_flag_unset (hdmi, &fifo_status, flag), +min (len,SUN4I_HDMI_DDC_FIFO_SIZE ) * byte_time, + 100000); + +if (is_err_status (int_status)) +return -EIO ; +if (ret) +return -ETIMEDOUT ;
Why not just have
ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_FIFO_STATUS_REG, reg,
!(reg & flag), 100, 100000);
if (ret < 0)
if (is_err_status()) return -EIO; return ret;
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 65
Quoted 3 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +3
-0+ +/* Read FIFO level */ +int level = (int )(fifo_status &SUN4I_HDMI_DDC_FIFO_STATUS_LEVEL_MASK );
and explicitly read the fifo status here. That will make you remove that function that does two things while claiming that it does only one, and it will be more obvious.
You can also just use reg at this point, instead of reading it once again.
Maxime
Signature · 3 lines
Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
Hi Maxime,
Quoted 23 lines · Maxime Ripard
Quoted 22 lines · Jonathan Liu
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +22
-0+#define SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK ( \ + SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION | \ + SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW | \ + SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW | \ + SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR | \ + SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR | \ + SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR \ +) + +static bool is_err_status (u32 int_status) +{ +return !!(int_status &SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK ); +} + +static bool is_fifo_flag_unset (struct sun4i_hdmi *hdmi,u32 *fifo_status, +u32 flag) +{ + *fifo_status =readl (hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG ); +return !(*fifo_status & flag); +} + +static int fifo_transfer (struct sun4i_hdmi *hdmi,u8 *buf,int len,bool read)
Quoted 9 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 43
Quoted 4 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +4
-0+{ +/* 1 byte takes 9 clock cycles (8 bits + 1 ACK) */ +unsigned long byte_time =DIV_ROUND_UP (USEC_PER_SEC , +clk_get_rate (hdmi->ddc_clk)) *9 ;There's no real need for it to be dynamic. The clock rate will not change, and the order of magnitude is roughly 100us, so let's just use that (and make a comment).
Ok.
Quoted 22 lines
Quoted 9 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +9
-0+u32 int_status; +u32 fifo_status; +/* Read needs empty flag unset, write needs full flag unset */ +u32 flag = read ?SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY : +SUN4I_HDMI_DDC_FIFO_STATUS_FULL ; +int ret; + +/* Wait until error or FIFO ready */ + ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 62
Quoted 10 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +10
-0+ int_status, +is_err_status (int_status) || +is_fifo_flag_unset (hdmi, &fifo_status, flag), +min (len,SUN4I_HDMI_DDC_FIFO_SIZE ) * byte_time, + 100000); + +if (is_err_status (int_status)) +return -EIO ; +if (ret) +return -ETIMEDOUT ;Why not just have
ret = readl_poll_timeout(hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG, reg,
Quoted 8 lines
!(reg & flag), 100, 100000);if (ret < 0)
if (is_err_status()) return -EIO; return ret;
If I check error status after readl_poll_timeout and there is an error (e.g. the I2C address does not have a corresponding device connected or nothing connected to HDMI port) it will keep checking the fifo status even though error bit is set in the int status and then timeout after 100 ms. If it checks the int status register at the same time, it will error after 100 nanoseconds. I don't want to introduce unnecessary delays considering part of the reason for adding this driver to make it more usable for non-standard use cases.
Quoted 8 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 65
Quoted 3 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +3
-0+ +/* Read FIFO level */ +int level = (int )(fifo_status &SUN4I_HDMI_DDC_FIFO_STATUS_LEVEL_MASK );and explicitly read the fifo status here. That will make you remove that function that does two things while claiming that it does only one, and it will be more obvious.
I will fix the is_fifo_flag_unset function so it only does one thing.
Quoted 9 lines
You can also just use reg at this point, instead of reading it once again.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Regards,
Jonathan
Quoted 31 lines · Jonathan Liu
Quoted 22 lines
Quoted 9 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +9
-0+u32 int_status; +u32 fifo_status; +/* Read needs empty flag unset, write needs full flag unset */ +u32 flag = read ?SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY : +SUN4I_HDMI_DDC_FIFO_STATUS_FULL ; +int ret; + +/* Wait until error or FIFO ready */ + ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 62
Quoted 10 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +10
-0+ int_status, +is_err_status (int_status) || +is_fifo_flag_unset (hdmi, &fifo_status, flag), +min (len,SUN4I_HDMI_DDC_FIFO_SIZE ) * byte_time, + 100000); + +if (is_err_status (int_status)) +return -EIO ; +if (ret) +return -ETIMEDOUT ;Why not just have
ret = readl_poll_timeout(hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG, reg,Quoted 8 lines
!(reg & flag), 100, 100000);if (ret < 0)
if (is_err_status()) return -EIO; return ret;
Quoted 8 lines
If I check error status after
readl_poll_timeoutand there is an error (e.g. the I2C address does not have a corresponding device connected or nothing connected to HDMI port) it will keep checking the fifo status even though error bit is set in the int status and then timeout after 100 ms. If it checks the int status register at the same time, it will error after 100 nanoseconds. I don't want to introduce unnecessary delays considering part of the reason for adding this driver to make it more usable for non-standard use cases.
Well, polling for 100ms doesn't seem great either. What was the rationale behind that timeout?
And we can also reverse the check and look at the INT_STATUS register. The errors will be there, and we can program the threshold we want in both directions and use the DDC_FIFO_Request_Interrupt_Status bit.
Maxime
Signature · 3 lines
Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
Hi Maxime,
Quoted 41 lines · Maxime Ripard
Quoted 31 lines · Jonathan Liu
Quoted 22 lines
Quoted 9 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +9
-0+u32 int_status; +u32 fifo_status; +/* Read needs empty flag unset, write needs full flag unset */ +u32 flag = read ?SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY : +SUN4I_HDMI_DDC_FIFO_STATUS_FULL ; +int ret; + +/* Wait until error or FIFO ready */ + ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 62
Quoted 10 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +10
-0+ int_status, +is_err_status (int_status) || +is_fifo_flag_unset (hdmi, &fifo_status, flag), +min (len,SUN4I_HDMI_DDC_FIFO_SIZE ) * byte_time, + 100000); + +if (is_err_status (int_status)) +return -EIO ; +if (ret) +return -ETIMEDOUT ;Why not just have
ret = readl_poll_timeout(hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG, reg,Quoted 8 lines
!(reg & flag), 100, 100000);if (ret < 0)
if (is_err_status()) return -EIO; return ret;Quoted 8 lines
If I check error status after
readl_poll_timeoutand there is an error (e.g. the I2C address does not have a corresponding device connected or nothing connected to HDMI port) it will keep checking the fifo status even though error bit is set in the int status and then timeout after 100 ms. If it checks the int status register at the same time, it will error after 100 nanoseconds. I don't want to introduce unnecessary delays considering part of the reason for adding this driver to make it more usable for non-standard use cases.
Quoted 3 lines
Well, polling for 100ms doesn't seem great either. What was the rationale behind that timeout?
When an error occurs one of the error bits will be set in the INT_STATUS register so this is detected very quickly if I check the INT_STATUS and FIFO_STATUS at the same time. The 100 ms timeout is in case the I2C slave does clock stretching in which case the transfer may take longer than the predicted time.
Quoted 5 lines
And we can also reverse the check and look at the
INT_STATUSregister. The errors will be there, and we can program the threshold we want in both directions and use theDDC_FIFO_Request_Interrupt_Statusbit.
I did try that when I was doing the v3 patch but I couldn't get it to work as mentioned previously in the v3 patch discussion. I programmed the FIFO_RX_TRIGGER_THRES and FIFO_TX_TRIGGER_THRES in DDC_FIFO_Ctrl register at the same time as setting FIFO_Address_Clear but the request interrupt status bit did not get updated to the appropriate state that is consistent with the FIFO level and the thresholds. I did try this several times for subsequent patch versions without success.
Quoted 6 lines
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Regards,
Jonathan
Quoted 61 lines · Jonathan Liu
Hi Maxime,
Quoted 41 lines · Maxime Ripard
Quoted 31 lines · Jonathan Liu
Quoted 22 lines
Quoted 9 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +9
-0+u32 int_status; +u32 fifo_status; +/* Read needs empty flag unset, write needs full flag unset */ +u32 flag = read ?SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY : +SUN4I_HDMI_DDC_FIFO_STATUS_FULL ; +int ret; + +/* Wait until error or FIFO ready */ + ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 62
Quoted 10 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +10
-0+ int_status, +is_err_status (int_status) || +is_fifo_flag_unset (hdmi, &fifo_status, flag), +min (len,SUN4I_HDMI_DDC_FIFO_SIZE ) * byte_time, + 100000); + +if (is_err_status (int_status)) +return -EIO ; +if (ret) +return -ETIMEDOUT ;Why not just have
ret = readl_poll_timeout(hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG, reg,Quoted 8 lines
!(reg & flag), 100, 100000);if (ret < 0)
if (is_err_status()) return -EIO; return ret;Quoted 8 lines
If I check error status after
readl_poll_timeoutand there is an error (e.g. the I2C address does not have a corresponding device connected or nothing connected to HDMI port) it will keep checking the fifo status even though error bit is set in the int status and then timeout after 100 ms. If it checks the int status register at the same time, it will error after 100 nanoseconds. I don't want to introduce unnecessary delays considering part of the reason for adding this driver to make it more usable for non-standard use cases.Quoted 3 lines
Well, polling for 100ms doesn't seem great either. What was the rationale behind that timeout?
When an error occurs one of the error bits will be set in the
INT_STATUSregister so this is detected very quickly if I check theINT_STATUSandFIFO_STATUSat the same time. The 100 ms timeout is in case the I2C slave does clock stretching in which case the transfer may take longer than the predicted time.Quoted 5 lines
And we can also reverse the check and look at the
INT_STATUSregister. The errors will be there, and we can program the threshold we want in both directions and use theDDC_FIFO_Request_Interrupt_Statusbit.
Quoted 7 lines
I did try that when I was doing the v3 patch but I couldn't get it to work as mentioned previously in the v3 patch discussion. I programmed the
FIFO_RX_TRIGGER_THRESandFIFO_TX_TRIGGER_THRESinDDC_FIFO_Ctrlregister at the same time as settingFIFO_Address_Clearbut the request interrupt status bit did not get updated to the appropriate state that is consistent with the FIFO level and the thresholds. I did try this several times for subsequent patch versions without success.
The manual says "When FIFO level is above this value in read mode, DMA request and FIFO request interrupt are asserted if relative enable is on."
Perhaps try enabling the interrupts? But if that were the case, wouldn't using interrupts instead of polling be better?
ChenYu
Quoted 10 lines
Quoted 7 lines
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.comRegards,
Jonathan
Hi Chen-Yu and Maxime,
Quoted 70 lines · Chen-Yu Tsai
Quoted 61 lines · Jonathan Liu
Hi Maxime,
Quoted 41 lines · Maxime Ripard
Quoted 31 lines · Jonathan Liu
Quoted 22 lines
Quoted 9 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +9
-0+u32 int_status; +u32 fifo_status; +/* Read needs empty flag unset, write needs full flag unset */ +u32 flag = read ?SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY : +SUN4I_HDMI_DDC_FIFO_STATUS_FULL ; +int ret; + +/* Wait until error or FIFO ready */ + ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 62
Quoted 10 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +10
-0+ int_status, +is_err_status (int_status) || +is_fifo_flag_unset (hdmi, &fifo_status, flag), +min (len,SUN4I_HDMI_DDC_FIFO_SIZE ) * byte_time, + 100000); + +if (is_err_status (int_status)) +return -EIO ; +if (ret) +return -ETIMEDOUT ;Why not just have
ret = readl_poll_timeout(hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG, reg,Quoted 8 lines
!(reg & flag), 100, 100000);if (ret < 0)
if (is_err_status()) return -EIO; return ret;Quoted 8 lines
If I check error status after
readl_poll_timeoutand there is an error (e.g. the I2C address does not have a corresponding device connected or nothing connected to HDMI port) it will keep checking the fifo status even though error bit is set in the int status and then timeout after 100 ms. If it checks the int status register at the same time, it will error after 100 nanoseconds. I don't want to introduce unnecessary delays considering part of the reason for adding this driver to make it more usable for non-standard use cases.Quoted 3 lines
Well, polling for 100ms doesn't seem great either. What was the rationale behind that timeout?
When an error occurs one of the error bits will be set in the
INT_STATUSregister so this is detected very quickly if I check theINT_STATUSandFIFO_STATUSat the same time. The 100 ms timeout is in case the I2C slave does clock stretching in which case the transfer may take longer than the predicted time.Quoted 5 lines
And we can also reverse the check and look at the
INT_STATUSregister. The errors will be there, and we can program the threshold we want in both directions and use theDDC_FIFO_Request_Interrupt_Statusbit.Quoted 7 lines
I did try that when I was doing the v3 patch but I couldn't get it to work as mentioned previously in the v3 patch discussion. I programmed the
FIFO_RX_TRIGGER_THRESandFIFO_TX_TRIGGER_THRESinDDC_FIFO_Ctrlregister at the same time as settingFIFO_Address_Clearbut the request interrupt status bit did not get updated to the appropriate state that is consistent with the FIFO level and the thresholds. I did try this several times for subsequent patch versions without success.
Quoted 8 lines
The manual says "When FIFO level is above this value in read mode, DMA request and FIFO request interrupt are asserted if relative enable is on."
Perhaps try enabling the interrupts? But if that were the case, wouldn't using interrupts instead of polling be better?
ChenYu
I managed to get the thresholds working so switching to using interrupts instead of polling will be my next goal.
Quoted 10 lines
Quoted 10 lines
Quoted 7 lines
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.comRegards,
Jonathan
Regards,
Jonathan
Quoted 76 lines · Jonathan Liu
Hi Chen-Yu and Maxime,
Quoted 73 lines · Chen-Yu Tsai
Quoted 61 lines · Jonathan Liu
Hi Maxime,
Quoted 41 lines · Maxime Ripard
Quoted 31 lines · Jonathan Liu
Quoted 22 lines
Quoted 9 lines
(quoted diff) +9
-0+ u32 int_status; + u32 fifo_status; + /* Read needs empty flag unset, write needs full flag unset */ + u32 flag = read ? SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY : + SUN4I_HDMI_DDC_FIFO_STATUS_FULL; + int ret; + + /* Wait until error or FIFO ready */ + ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,Review
Quoted 10 lines
(quoted diff) +10
-0+ int_status, + is_err_status(int_status) || + is_fifo_flag_unset(hdmi, &fifo_status, flag), + min(len, SUN4I_HDMI_DDC_FIFO_SIZE) * byte_time, + 100000); + + if (is_err_status(int_status)) + return -EIO; + if (ret) + return -ETIMEDOUT;Why not just have
ret = readl_poll_timeout(hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG, reg,Quoted 8 lines
!(reg & flag), 100, 100000);if (ret < 0)
if (is_err_status()) return -EIO; return ret;Quoted 8 lines
If I check error status after
readl_poll_timeoutand there is an error (e.g. the I2C address does not have a corresponding device connected or nothing connected to HDMI port) it will keep checking the fifo status even though error bit is set in the int status and then timeout after 100 ms. If it checks the int status register at the same time, it will error after 100 nanoseconds. I don't want to introduce unnecessary delays considering part of the reason for adding this driver to make it more usable for non-standard use cases.Quoted 3 lines
Well, polling for 100ms doesn't seem great either. What was the rationale behind that timeout?
When an error occurs one of the error bits will be set in the
INT_STATUSregister so this is detected very quickly if I check theINT_STATUSandFIFO_STATUSat the same time. The 100 ms timeout is in case the I2C slave does clock stretching in which case the transfer may take longer than the predicted time.Quoted 5 lines
And we can also reverse the check and look at the
INT_STATUSregister. The errors will be there, and we can program the threshold we want in both directions and use theDDC_FIFO_Request_Interrupt_Statusbit.Quoted 7 lines
I did try that when I was doing the v3 patch but I couldn't get it to work as mentioned previously in the v3 patch discussion. I programmed the
FIFO_RX_TRIGGER_THRESandFIFO_TX_TRIGGER_THRESinDDC_FIFO_Ctrlregister at the same time as settingFIFO_Address_Clearbut the request interrupt status bit did not get updated to the appropriate state that is consistent with the FIFO level and the thresholds. I did try this several times for subsequent patch versions without success.The manual says "When FIFO level is above this value in read mode, DMA request and FIFO request interrupt are asserted if relative enable is on."
Quoted 8 lines
Quoted 5 lines
Perhaps try enabling the interrupts? But if that were the case, wouldn't using interrupts instead of polling be better?
ChenYu
I managed to get the thresholds working so switching to using interrupts instead of polling will be my next goal.
I'd say that we can do it using polling first, and then move to interrupts if needed. And that should definitely be part of a separate patch. This one is already pretty invasive.
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170630/4ea810e2/attachment-0001.sig>
Hi,
Quoted 49 lines · Jonathan Liu
Hi Maxime,
Quoted 41 lines · Maxime Ripard
Quoted 31 lines · Jonathan Liu
Quoted 22 lines
Quoted 9 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +9
-0+u32 int_status; +u32 fifo_status; +/* Read needs empty flag unset, write needs full flag unset */ +u32 flag = read ?SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY : +SUN4I_HDMI_DDC_FIFO_STATUS_FULL ; +int ret; + +/* Wait until error or FIFO ready */ + ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 62
Quoted 10 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +10
-0+ int_status, +is_err_status (int_status) || +is_fifo_flag_unset (hdmi, &fifo_status, flag), +min (len,SUN4I_HDMI_DDC_FIFO_SIZE ) * byte_time, + 100000); + +if (is_err_status (int_status)) +return -EIO ; +if (ret) +return -ETIMEDOUT ;Why not just have
ret = readl_poll_timeout(hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG, reg,Quoted 8 lines
!(reg & flag), 100, 100000);if (ret < 0)
if (is_err_status()) return -EIO; return ret;Quoted 8 lines
If I check error status after
readl_poll_timeoutand there is an error (e.g. the I2C address does not have a corresponding device connected or nothing connected to HDMI port) it will keep checking the fifo status even though error bit is set in the int status and then timeout after 100 ms. If it checks the int status register at the same time, it will error after 100 nanoseconds. I don't want to introduce unnecessary delays considering part of the reason for adding this driver to make it more usable for non-standard use cases.Quoted 3 lines
Well, polling for 100ms doesn't seem great either. What was the rationale behind that timeout?
Quoted 5 lines
When an error occurs one of the error bits will be set in the
INT_STATUSregister so this is detected very quickly if I check theINT_STATUSandFIFO_STATUSat the same time. The 100 ms timeout is in case the I2C slave does clock stretching in which case the transfer may take longer than the predicted time.
100ms isn't stretching anymore, it's worse than that.
Quoted 6 lines
Quoted 5 lines
And we can also reverse the check and look at the
INT_STATUSregister. The errors will be there, and we can program the threshold we want in both directions and use theDDC_FIFO_Request_Interrupt_Statusbit.
Quoted 7 lines
I did try that when I was doing the v3 patch but I couldn't get it to work as mentioned previously in the v3 patch discussion. I programmed the
FIFO_RX_TRIGGER_THRESandFIFO_TX_TRIGGER_THRESinDDC_FIFO_Ctrlregister at the same time as settingFIFO_Address_Clearbut the request interrupt status bit did not get updated to the appropriate state that is consistent with the FIFO level and the thresholds. I did try this several times for subsequent patch versions without success.
What values did you set it to?
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170630/0a1813b0/attachment.sig>
Hi Maxime,
Quoted 52 lines · Maxime Ripard
Hi,
Quoted 49 lines · Jonathan Liu
Hi Maxime,
Quoted 44 lines · Maxime Ripard
Quoted 31 lines · Jonathan Liu
Quoted 22 lines
Quoted 9 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +9
-0+u32 int_status; +u32 fifo_status; +/* Read needs empty flag unset, write needs full flag unset */ +u32 flag = read ?SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY : +SUN4I_HDMI_DDC_FIFO_STATUS_FULL ; +int ret; + +/* Wait until error or FIFO ready */ + ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c line 62
Quoted 10 lines
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file +10
-0+ int_status, +is_err_status (int_status) || +is_fifo_flag_unset (hdmi, &fifo_status, flag), +min (len,SUN4I_HDMI_DDC_FIFO_SIZE ) * byte_time, + 100000); + +if (is_err_status (int_status)) +return -EIO ; +if (ret) +return -ETIMEDOUT ;Why not just have
ret = readl_poll_timeout(hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG, reg,Quoted 8 lines
!(reg & flag), 100, 100000);if (ret < 0)
if (is_err_status()) return -EIO; return ret;Quoted 8 lines
If I check error status after
readl_poll_timeoutand there is an error (e.g. the I2C address does not have a corresponding device connected or nothing connected to HDMI port) it will keep checking the fifo status even though error bit is set in the int status and then timeout after 100 ms. If it checks the int status register at the same time, it will error after 100 nanoseconds. I don't want to introduce unnecessary delays considering part of the reason for adding this driver to make it more usable for non-standard use cases.Well, polling for 100ms doesn't seem great either. What was the rationale behind that timeout?
Quoted 8 lines
Quoted 5 lines
When an error occurs one of the error bits will be set in the
INT_STATUSregister so this is detected very quickly if I check theINT_STATUSandFIFO_STATUSat the same time. The 100 ms timeout is in case the I2C slave does clock stretching in which case the transfer may take longer than the predicted time.100ms isn't stretching anymore, it's worse than that.
What would you suggest?
Quoted 14 lines
Quoted 6 lines
Quoted 5 lines
And we can also reverse the check and look at the
INT_STATUSregister. The errors will be there, and we can program the threshold we want in both directions and use theDDC_FIFO_Request_Interrupt_Statusbit.Quoted 7 lines
I did try that when I was doing the v3 patch but I couldn't get it to work as mentioned previously in the v3 patch discussion. I programmed the
FIFO_RX_TRIGGER_THRESandFIFO_TX_TRIGGER_THRESinDDC_FIFO_Ctrlregister at the same time as settingFIFO_Address_Clearbut the request interrupt status bit did not get updated to the appropriate state that is consistent with the FIFO level and the thresholds. I did try this several times for subsequent patch versions without success.
Quoted 2 lines
What values did you set it to?
FIFO_RX_TRIGGER_THRES: 0FIFO_TX_TRIGGER_THRES: 15
Quoted 6 lines
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Regards,
Jonathan
Hi Maxime,
Quoted 62 lines · Jonathan Liu
Hi Maxime,
Quoted 58 lines · Maxime Ripard
Hi,
Quoted 54 lines · Jonathan Liu
Hi Maxime,
Quoted 41 lines · Maxime Ripard
Quoted 31 lines · Jonathan Liu
Quoted 22 lines
Quoted 9 lines
(quoted diff) +9
-0+ u32 int_status; + u32 fifo_status; + /* Read needs empty flag unset, write needs full flag unset */ + u32 flag = read ? SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY : + SUN4I_HDMI_DDC_FIFO_STATUS_FULL; + int ret; + + /* Wait until error or FIFO ready */ + ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,Review
Quoted 10 lines
(quoted diff) +10
-0+ int_status, + is_err_status(int_status) || + is_fifo_flag_unset(hdmi, &fifo_status, flag), + min(len, SUN4I_HDMI_DDC_FIFO_SIZE) * byte_time, + 100000); + + if (is_err_status(int_status)) + return -EIO; + if (ret) + return -ETIMEDOUT;Why not just have
ret = readl_poll_timeout(hdmi->base +SUN4I_HDMI_DDC_FIFO_STATUS_REG, reg,Quoted 8 lines
!(reg & flag), 100, 100000);if (ret < 0)
if (is_err_status()) return -EIO; return ret;Quoted 8 lines
If I check error status after
readl_poll_timeoutand there is an error (e.g. the I2C address does not have a corresponding device connected or nothing connected to HDMI port) it will keep checking the fifo status even though error bit is set in the int status and then timeout after 100 ms. If it checks the int status register at the same time, it will error after 100 nanoseconds. I don't want to introduce unnecessary delays considering part of the reason for adding this driver to make it more usable for non-standard use cases.Quoted 3 lines
Well, polling for 100ms doesn't seem great either. What was the rationale behind that timeout?
When an error occurs one of the error bits will be set in the
INT_STATUSregister so this is detected very quickly if I check theINT_STATUSandFIFO_STATUSat the same time. The 100 ms timeout is in case the I2C slave does clock stretching in which case the transfer may take longer than the predicted time.
Quoted 5 lines
Quoted 2 lines
100ms isn't stretching anymore, it's worse than that.
What would you suggest?
You need to consider the fact that there are I2C devices such as sensors that may do I2C clock stretching up to several tens of milliseconds. For example the HTU21D humidity sensor takes up to 50 ms max to perform measurement of temperature during which it is holding down the clock to do I2C clock stretching.
Quoted 22 lines
Quoted 14 lines
Quoted 6 lines
Quoted 5 lines
And we can also reverse the check and look at the
INT_STATUSregister. The errors will be there, and we can program the threshold we want in both directions and use theDDC_FIFO_Request_Interrupt_Statusbit.Quoted 7 lines
I did try that when I was doing the v3 patch but I couldn't get it to work as mentioned previously in the v3 patch discussion. I programmed the
FIFO_RX_TRIGGER_THRESandFIFO_TX_TRIGGER_THRESinDDC_FIFO_Ctrlregister at the same time as settingFIFO_Address_Clearbut the request interrupt status bit did not get updated to the appropriate state that is consistent with the FIFO level and the thresholds. I did try this several times for subsequent patch versions without success.Quoted 2 lines
What values did you set it to?
FIFO_RX_TRIGGER_THRES: 0FIFO_TX_TRIGGER_THRES: 15Quoted 2 lines
Maxime
Quoted 7 lines
Quoted 4 lines
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.comRegards,
Jonathan
Regards,
Jonathan
kbuild test robot
build boturl: https://github.com/0day-ci/linux/commits/Jonathan-Liu/drm-sun4i-hdmi-Implement-I2C-adapter-for-A10s-DDC-bus/20170629-001335 config: arm-sunxi_defconfig (attached as .config) compiler…
Hi Jonathan,
[auto build test WARNING on next-20170627]
[cannot apply to v4.12-rc7 v4.12-rc6 v4.12-rc5 v4.12-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Jonathan-Liu/drm-sun4i-hdmi-Implement-I2C-adapter-for-A10s-DDC-bus/20170629-001335
config: arm-sunxi_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All warnings (new ones prefixed by >>):
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c: In function 'fifo_transfer':
>> drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c:65:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
int level = (int)(fifo_status & SUN4I_HDMI_DDC_FIFO_STATUS_LEVEL_MASK);
^~~vim +65 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c
49 int ret;
50
51 /* Wait until error or FIFO ready */
52 ret = readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG,
53 int_status,
54 is_err_status(int_status) ||
55 is_fifo_flag_unset(hdmi, &fifo_status, flag),
56 min(len, SUN4I_HDMI_DDC_FIFO_SIZE) * byte_time,
57 100000);
58
59 if (is_err_status(int_status))
60 return -EIO;
61 if (ret)
62 return -ETIMEDOUT;
63
64 /* Read FIFO level */
> 65 int level = (int)(fifo_status & SUN4I_HDMI_DDC_FIFO_STATUS_LEVEL_MASK);
66
67 /* Limit transfer length using FIFO level to avoid underflow/overflow */
68 len = min(len, read ? level : (SUN4I_HDMI_DDC_FIFO_SIZE - level));
69
70 if (read)
71 readsb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len);
72 else
73 writesb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len);---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
Signature · 3 lines
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