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sunxi: usb_phy: Fix the phy_ctl offset on the A83T

PATCH New Maxime Ripard 2 participants 2 messages Jul 12, 2017

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/Allwinner sunXi SoC support
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Maxime Ripard

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#0 lore raw

PATCH 1/1 sunxi: usb_phy: Fix the phy_ctl offset on the A83T

The A83T, just like the A33, has a USB phy with the phy_ctl at 0x410 instead of 0x404.

Suggested-by Chen-Yu Tsai <[email protected]>
Signed-off-by Maxime Ripard <[email protected]>
---
 arch/arm/mach-sunxi/usb_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/mach-sunxi/usb_phy.c +1 -1
index 9bf0b5633d4a..1ca9739fbee3 100644
@@ -19,7 +19,7 @@
 #include <errno.h>
 
 #define SUNXI_USB_PMU_IRQ_ENABLE	0x800
-#ifdef CONFIG_MACH_SUN8I_A33
+#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN8I_A83T)
 #define SUNXI_USB_CSR			0x410
 #else
 #define SUNXI_USB_CSR			0x404
Signature · 1 line
2.13.0
#1 lore raw

PATCH 1/1 sunxi: usb_phy: Fix the phy_ctl offset on the A83T

Quoted 14 lines · On Wed, 12 Jul 2017 16:44:25 +0200 Maxime Ripard…

The A83T, just like the A33, has a USB phy with the phy_ctl at 0x410 instead of 0x404.

Suggested-by Chen-Yu Tsai <[email protected]>
Signed-off-by Maxime Ripard <[email protected]>
---
 arch/arm/mach-sunxi/usb_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/mach-sunxi/usb_phy.c +0 -0
index 9bf0b5633d4a..1ca9739fbee3 100644

arch/arm/mach-sunxi/usb_phy.c line 25

Quoted 8 lines
arch/arm/mach-sunxi/usb_phy.c +1 -1
@@ -19,7 +19,7 @@
 #include <errno.h>
 
 #define SUNXI_USB_PMU_IRQ_ENABLE	0x800
-#ifdef CONFIG_MACH_SUN8I_A33
+#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN8I_A83T)
 #define SUNXI_USB_CSR			0x410
 #else
 #define SUNXI_USB_CSR			0x404

Is only A83T affected? Just in case, please check which SUNXI_USB_CSR value is needed for the other SoC variants and add these SoCs explicitly to the ifdef checks.

It also makes a lot of sense to get rid of the default #else clause, because having it there is very error prone when adding support for new SoCs. One may end up with a wrong default without noticing.

Signature · 2 lines
Best regards,
Siarhei Siamashka